CN102427030A - Manufacturing method for high-K and metal gate electrode - Google Patents
Manufacturing method for high-K and metal gate electrode Download PDFInfo
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- CN102427030A CN102427030A CN2011103868883A CN201110386888A CN102427030A CN 102427030 A CN102427030 A CN 102427030A CN 2011103868883 A CN2011103868883 A CN 2011103868883A CN 201110386888 A CN201110386888 A CN 201110386888A CN 102427030 A CN102427030 A CN 102427030A
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Abstract
The invention discloses a manufacturing method for a high-K and metal gate electrode. The manufacturing method is characterized by comprising the following steps of: firstly, depositing a gate electrode stack layer on a silicon substrate where a plurality of field isolation regions are formed; secondly, etching the gate electrode stack layer to form an inverted trapezoidal gate electrode positioned between two phases of adjacent filed isolation regions; thirdly, carrying out shallow junction injection and annealing as well as source-and-drain injection and annealing to form paired source and drain electrodes; fourthly, depositing a dielectric material to cover the inverted trapezoidal gate electrode; fifthly, chemically and mechanically grinding with the inverted trapezoidal gate electrode as a stop layer; sixthly, removing the inverted trapezoidal gate electrode; seventhly, sequentially depositing a high-dielectric-constant material and a covering layer on the medium layer and the silicon substrate; eighthly, depositing a metal gate electrode material on the covering layer; and ninthly, manufacturing the metal gate electrode.
Description
Technical field
The present invention relates to a kind of technology method of semiconductor integrated circuit, be specifically related to the manufacture method of a kind of high K and metal gates.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOS transistor).Since metal-oxide-semiconductor was invented, its physical dimension was constantly being dwindled always, and its characteristic size has got into the 45nm scope at present.Under this size, various reality and basic restriction and technological challenge begin to occur, device size further dwindle the more and more difficult that just becomes.
Wherein, in the preparation of MOS transistor device and circuit, tool is challenging be the traditional cmos device in the process of dwindling because the higher grid Leakage Current that polysilicon/SiO2 or SiON gate oxide dielectric thickness reduce to bring.
For this reason, the solution that prior art has proposed is to adopt metal gate and high-k (K) gate medium to substitute traditional heavily doped polysilicon grid and SiO2 (or SiON) gate medium.According to integrated circuit technique development course figure, the practical application of metal gate, high-K gate dielectric will be in inferior 65nm technology.The formation method of metal gate and high K medium is divided into a variety of, mainly is divided into first grid (gate first) and back grid (gate late), and wherein the back grid is divided into high k (high k first) and back high k (high k last) earlier again.Behind the high k in back in the grid; Need to remove earlier polysilicon gate; Then high k material, cover layer and metal gate material are filled into the zone at polysilicon gate place; Because constantly the dwindling of semiconductor device, the process window of its gap fill is also more and more littler, develops into and will have to abandon grid processing procedure behind the high k in back below the 22nm because of filling.
Therefore, provide a kind of and can continue in the following technology of 22nm to use that the technology of grid just seems particularly important behind the high k in back.
Summary of the invention
The object of the invention is exactly a deficiency of avoiding can't in the following technology of 22nm, continuing in the prior art using the technology of grid behind the high k in back.
The present invention discloses the manufacture method of a kind of high K and metal gates, wherein, comprising:
Step 1 is being formed with deposit grid pile layer on the silicon substrate of some isolated areas;
Step 2, the said grid pile layer of etching forms trapezoidal grid, saidly falls trapezoidal grid and is positioned in the middle of the two opposite field isolated areas;
Step 3, shallow junction are injected and annealing, and the source is leaked and injected and annealing, is formed into right source, drain electrode;
Step 4, deposit dielectric material cover the said trapezoidal grid that falls;
Step 5 is fallen trapezoidal grid and is carried out cmp for stopping layer with said;
Step 6 is removed the said trapezoidal grid that falls
Step 7, depositing high dielectric constant material and cover layer on said dielectric material and silicon substrate successively;
Step 8, deposited metal gate material on cover layer;
Step 9 is made metal gates.
The above-mentioned high K medium and the manufacture method of metal gates, wherein, said grid pile layer comprises silicon dioxide and polysilicon.
The above-mentioned high K medium and the manufacture method of metal gates, wherein, said metal gate material is an aluminium.
The above-mentioned high K medium and the manufacture method of metal gates, wherein, said step 9 comprises:
Step 91, for stopping layer, etching forms the T type metal gates utmost point with cover layer.
The above-mentioned high K medium and the manufacture method of metal gates, wherein, said step 9 comprises:
Step 92, for stopping layer, cmp forms said metal gates with cover layer.
According to another aspect of the present invention, also disclose a kind of high K medium and metal gate structure, wherein, comprising:
Be formed with the silicon substrate of some isolated areas, have pair of source, drain electrode between the two opposite field isolated areas, be formed with raceway groove between said source, the drain electrode;
Dielectric material is positioned at said source, drain electrode top;
Be coated with high dielectric constant material and cover layer on the said dielectric material successively;
Said cover layer is positioned at said raceway groove top position and is filled with metal gates.
Above-mentioned high K medium and metal gate structure, wherein, said metal gates is an aluminium.
Above-mentioned high K medium and metal gate structure, wherein, said metal gates is the T type metal gates utmost point.
Advantage of the present invention is:
1, utilize the alternative spacer completion of trapezoidal grid shallow junction injection and source to leak and inject the minimizing processing step;
2, enlarged the process window of metal gates gap fill, reduced technology difficulty;
3, promoted the product yield;
4, expanded the use of gate last in processing procedure, it still can be used below 22nm.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, the part parts have been amplified.
Fig. 1 shows according to a specific embodiment of the present invention, the sketch map of a kind of high K medium and metal gate structure;
Fig. 2 shows in the method for making a kind of high K medium and metal gates, the sketch map behind the formation grid pile layer;
Fig. 3 shows in the method for making a kind of high K medium and metal gates, makes the sketch map of trapezoidal grid;
Fig. 4 shows in the method for making a kind of high K medium and metal gates, forms the sketch map of source-drain electrode;
Fig. 5 shows in the method for making a kind of high K medium and metal gates, the sketch map behind deposit dielectric material and the chemical-mechanical planarization;
Fig. 6 shows in the method for making a kind of high K medium and metal gates, removes the sketch map behind the grid pile layer;
Fig. 7 shows in the method for making a kind of high K medium and metal gates, depositing high dielectric constant material and tectal sketch map;
Fig. 8 shows in the method for making a kind of high K medium and metal gates, the sketch map of deposited metal gate material; And
Fig. 9 shows in the method for making a kind of high K medium and metal gates, makes the sketch map of T shape metal gates.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further elaborated.Embodiment described herein only is used to explain the present invention, and is not used in qualification protection scope of the present invention.
With reference to the sketch map of a kind of high K illustrated in fig. 1 and metal gate structure, in conjunction with Fig. 2 to Fig. 9, in one embodiment of the present of invention, the manufacture method of a kind of high K and metal gates 402 wherein, comprising:
Step 1, deposit grid pile layer 201 on the silicon substrate that is formed with some isolated areas 102 101 obtains like figure, the structure shown in 2;
Step 2, again with reference to figure 3, etching grid pile layer 201 forms trapezoidal grid 202, and the trapezoidal grid 202 that falls is positioned in the middle of the two opposite field isolated areas 102;
Step 3, shallow junction are injected and annealing, and the source is leaked and injected and annealing, is formed into right source, drain electrode, see source electrode 103 and drain electrode 104 among Fig. 3;
Step 4, deposit dielectric material 203 covers trapezoidal grid 202;
Step 5 is carried out cmp to fall trapezoidal grid 202 for stopping layer;
Step 6 removes trapezoidal grid 202;
Step 7, depositing high dielectric constant material 301 and cover layer 302 on dielectric material 203 and silicon substrate 101 successively;
Step 8, deposited metal gate 402 materials 401 on cover layer 302;
Step 9 is made metal gates 402.
In a preference, grid pile layer 201 comprises silicon dioxide and polysilicon.
Particularly, the material of metal gates 402 is an aluminium.
It will be appreciated by those skilled in the art that step 9 comprises with reference to figure 9:
Step 91, for stopping layer, etching forms the T type metal gates utmost point 403 with cover layer 302.
In a variant, with reference to figure 1, step 9 comprises:
Step 92, for stopping layer, cmp forms metal gates 402 with cover layer 302.
Structure with reference to shown in Figure 1 according to another aspect of the present invention, also discloses a kind of high K medium and metal gate structure, wherein, comprising:
Be formed with between silicon substrate 101, the two opposite field isolated areas 102 of some isolated areas 102 and have pair of source, drain electrode, be formed with the raceway groove (not shown in figure 1) between source, the drain electrode;
Be coated with high dielectric constant material 301 and cover layer 302 on the dielectric material 203 successively;
The place, top position that cover layer 302 is positioned at raceway groove is filled with metal gates 402.
In a specific embodiment, metal gates 402 is an aluminium.
With reference to figure 9, in a variant of the present invention, grid is the T type metal gates utmost point 403.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (8)
1. the manufacture method of one kind high K medium and metal gates is characterized in that, comprising:
Step 1 is being formed with deposit grid pile layer on the silicon substrate of some isolated areas;
Step 2, the said grid pile layer of etching forms trapezoidal grid, saidly falls trapezoidal grid and is positioned in the middle of the two opposite field isolated areas;
Step 3, shallow junction are injected and annealing, and the source is leaked and injected and annealing, is formed into right source, drain electrode;
Step 4, deposit dielectric material cover the said trapezoidal grid that falls;
Step 5 is fallen trapezoidal grid and is carried out cmp for stopping layer with said;
Step 6 is removed the said trapezoidal grid that falls
Step 7, depositing high dielectric constant material and cover layer on said dielectric material and silicon substrate successively;
Step 8, deposited metal gate material on cover layer;
Step 9 is made metal gates.
2. the manufacture method of high K medium according to claim 1 and metal gates is characterized in that said grid pile layer comprises silicon dioxide and polysilicon.
3. the manufacture method of high K medium according to claim 1 and metal gates is characterized in that said metal gate material is an aluminium.
4. the manufacture method of high K medium according to claim 1 and metal gates is characterized in that said step 9 comprises:
Step 91, for stopping layer, etching forms the T type metal gates utmost point with cover layer.
5. the manufacture method of high K medium according to claim 1 and metal gates is characterized in that said step 9 comprises:
Step 92, for stopping layer, cmp forms said metal gates with cover layer.
6. one kind high K medium and metal gate structure is characterized in that, comprising:
Be formed with the silicon substrate of some isolated areas, have pair of source, drain electrode between the two opposite field isolated areas, be formed with raceway groove between said source, the drain electrode;
Dielectric material is positioned at said source, drain electrode top;
Be coated with high dielectric constant material and cover layer on the said dielectric material successively;
Said cover layer is positioned at said raceway groove top position and is filled with metal gates.
7. high K medium according to claim 6 and metal gate structure is characterized in that said metal gates is an aluminium.
8. high K medium according to claim 6 and metal gate structure is characterized in that, said metal gates is the T type metal gates utmost point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2011103868883A CN102427030A (en) | 2011-11-29 | 2011-11-29 | Manufacturing method for high-K and metal gate electrode |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103868883A CN102427030A (en) | 2011-11-29 | 2011-11-29 | Manufacturing method for high-K and metal gate electrode |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1476064A (en) * | 2002-08-14 | 2004-02-18 | 上海宏力半导体制造有限公司 | Method of forming light doped drain electrode using inverse taper grid structure |
| US6767835B1 (en) * | 2002-04-30 | 2004-07-27 | Advanced Micro Devices, Inc. | Method of making a shaped gate electrode structure, and device comprising same |
| CN1846313A (en) * | 2003-09-09 | 2006-10-11 | 国际商业机器公司 | Structure and method for metal replacement gate of high performance device |
| CN102104070A (en) * | 2009-12-21 | 2011-06-22 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| CN102117750A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Metal-oxide-semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof |
-
2011
- 2011-11-29 CN CN2011103868883A patent/CN102427030A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6767835B1 (en) * | 2002-04-30 | 2004-07-27 | Advanced Micro Devices, Inc. | Method of making a shaped gate electrode structure, and device comprising same |
| CN1476064A (en) * | 2002-08-14 | 2004-02-18 | 上海宏力半导体制造有限公司 | Method of forming light doped drain electrode using inverse taper grid structure |
| CN1846313A (en) * | 2003-09-09 | 2006-10-11 | 国际商业机器公司 | Structure and method for metal replacement gate of high performance device |
| CN102104070A (en) * | 2009-12-21 | 2011-06-22 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| CN102117750A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Metal-oxide-semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof |
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Application publication date: 20120425 |