CN104867986A - Multi-time program memory (MTP) device structure and manufacturing method thereof - Google Patents
Multi-time program memory (MTP) device structure and manufacturing method thereof Download PDFInfo
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- CN104867986A CN104867986A CN201410058155.0A CN201410058155A CN104867986A CN 104867986 A CN104867986 A CN 104867986A CN 201410058155 A CN201410058155 A CN 201410058155A CN 104867986 A CN104867986 A CN 104867986A
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Abstract
The present invention provides an MTP device structure and a manufacturing method thereof. The manufacturing method comprises the steps of providing a semiconductor substrate, and making a shallow channel isolating structure used for isolating a first well region and a second well region in the semiconductor substrate; forming an N well in the first well region by an N-type doping ion implantation technology; forming a P-region at the lower part of the second well region by a P-type doping ion implantation technology; forming an N region at the upper part of the second well region by an N-type doping ion implantation technology; forming a floating gate structure covering the N well, the shallow channel isolating structure and a part of the N region. According to the present invention, by manufacturing an original P well region into the second well region composed of the lower P region and the upper N region, an erasing voltage of an MTP device can be improved greatly, and the erasing speed of the MTP device can be improved greatly without needing to increase the volume of an erasing capacitor. The manufacturing method of the present invention is simple, and is suitable for the industrial production by being compatible with a CMOS technology.
Description
Technical field
The present invention relates to a kind of semiconductor device and preparation method thereof, particularly relate to a kind of MTP device architecture and preparation method thereof.
Background technology
Time-after-time programmable memory ((Multi-Time Program Memory, MTP), compared to single programmable memory (onetime program Memory, OTP), have can repeatedly carry out data stored in, read, the action such as to erase, and stored in the data advantage that also can not disappear after a loss of power, become a kind of storage component part that the fields such as PC, electronic equipment, mobile storage extensively adopt gradually.
As shown in Figure 1, it comprises selection transistor 30 and one that a floating transistor 20, is connected with described floating gate transistor structures for controlling the erasing electric capacity 10 of the electric charge wiped in described floating transistor 20 to existing a kind of MTP circuit structure.For the MTP device of less than 0.13 μm, it requires very high erasing speed, and in above-mentioned existing structure, its erasing speed is about 230us, is far from meeting the requirements of erasing speed.In order to increase erasing speed, common practices is the volume increasing erasing electric capacity, but this way often reduces the bulk velocity of device and the integrated level of device greatly, therefore, the volume increasing erasing electric capacity is relied on to reach the method increasing erasing speed not fully up to expectations.
Existing a kind of MTP device architecture as shown in Figure 2, it comprises the isolation structure of shallow trench 202 of the arrangement of being separated by be formed in substrate 201, between described isolation structure of shallow trench and by by described isolation structure of shallow trench the N well region 203 that separates and P well region 204; Be covered in the floating gate structure of described isolation structure of shallow trench, N trap and part P well region, described floating gate structure comprises floating gate oxide layers 205 and floating gate polysilicon layer 206; And the N+ contact zone 207 be formed in the P well region that do not covered by described floating gate structure; In addition, described MTP device also comprises and is positioned at the device architectures 208 and 209 such as NMOS and PMOS outside described isolation structure of shallow trench.
The method for deleting of MT reconnaissance P device architecture can adopt FN (Fowler-Nordheim tunneling, Fowler-Nordheim tunnelling) mechanism.Apply erasing voltage to erasing end (being above-mentioned N+ contact zone) herein, meanwhile, the electromotive force of floating gate structure is maintained closely voltage.Now, the most of electronics in described floating gate polysilicon layer arrives P well region through the floating gate oxide layers of floating gate structure, realizes Fowler-Nordheim tunneling effect.By above method, electronics is removed from floating gate polysilicon layer, namely completes the erasing of the storage data of MTP device architecture.
Under the prerequisite that floating gate oxide layers thickness is certain, (one end is erasing voltage to the voltage difference at these floating gate oxide layers two ends, the other end is the ground voltage of floating gate polysilicon layer) the tunnelling field intensity of larger correspondence is also larger, the tunnelling current of Fowler-Nordheim tunnelling is also larger, and erasing speed is faster.In order to obtain erasing speed faster, wish that erasing voltage is the bigger the better.But for the MTP device architecture of said structure, its erasing voltage is generally 6V, reason can not bear higher voltage between N+ contact zone and P well region, in general, the puncture voltage of this structure is below 10V, and the increase of erasing voltage easily causes the destruction of device architecture.
Therefore, provide a kind of and effectively can improve erasing voltage and MTP device architecture of retainer member stability and preparation method thereof is necessary.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of MTP device architecture and preparation method thereof, for solving the problem that MTP device erasing speed in prior art is difficult to improve.
For achieving the above object and other relevant objects, the invention provides a kind of manufacture method of MTP device architecture, at least comprise the following steps:
Semi-conductive substrate is provided, in described Semiconductor substrate, produces the isolation structure of shallow trench for isolating the first well region and the second well region;
N-type Doped ions injection technology is adopted to form N trap in described first well region;
P type Doped ions injection technology is adopted to form P-region in described second well region bottom;
N-type Doped ions injection technology is adopted to form N-region in described second well region top;
Form the floating gate structure covering described N trap, isolation structure of shallow trench and part N-region.
As a kind of preferred version of the manufacture method of MTP device architecture of the present invention, also comprise step: in the N-region do not covered by described floating gate structure, form N+ contact zone.
As a kind of preferred version of the manufacture method of MTP device architecture of the present invention, the Doped ions that described P-region is injected is boron, and the scope of Implantation Energy is 160 ~ 240Kev, and the scope of implantation dosage is 1E12 ~ 5E12/cm
2.
As a kind of preferred version of the manufacture method of MTP device architecture of the present invention, the Doped ions that described N-region is injected is phosphorus, and the scope of Implantation Energy is 60 ~ 120Kev, and the scope of implantation dosage is 5E12 ~ 2E13/cm
2.
As a kind of preferred version of the manufacture method of MTP device architecture of the present invention, the degree of depth in described N-region is not more than the degree of depth of described isolation structure of shallow trench.
As a kind of preferred version of the manufacture method of MTP device architecture of the present invention, the making of described floating gate structure comprises step:
Formed successively and be covered in described isolation structure of shallow trench, the floating gate oxide layers in N trap and N-region and floating gate polysilicon layer;
Adopt photoetching process to remove floating gate oxide layers and the floating gate polysilicon layer of part, retain and be covered in described N trap, the floating gate oxide layers in isolation structure of shallow trench and part N-region and floating gate polysilicon layer;
Make sidewall structure in described floating gate oxide layers and floating gate polysilicon layer both sides, complete the making of floating gate structure.
The present invention also provides a kind of MTP device architecture, comprising:
Semiconductor substrate;
Isolation structure of shallow trench, is formed in described Semiconductor substrate;
First well region and the second well region, be formed in the Semiconductor substrate of described shallow trench isolation both sides respectively, described first well region is N trap, and described second well region comprises the P-region of bottom and the N-region on top;
Floating gate structure, is covered in described N trap, isolation structure of shallow trench and part N-region.
As a kind of preferred version of MTP device architecture of the present invention, also comprise the N+ contact zone in the N-region being formed at and not covered by described floating gate structure.
As a kind of preferred version of MTP device architecture of the present invention, the degree of depth in described N-region is not more than the degree of depth of described isolation structure of shallow trench.
As a kind of preferred version of MTP device architecture of the present invention, described floating gate structure comprises the sidewall structure being covered in described N trap, the floating gate oxide layers in isolation structure of shallow trench and part N-region and floating gate polysilicon layer and being formed at described floating gate oxide layers and floating gate polysilicon layer both sides.
As mentioned above, the invention provides a kind of MTP device architecture and preparation method thereof, described manufacture method comprises step: provide semi-conductive substrate, produces the isolation structure of shallow trench for isolating the first well region and the second well region in described Semiconductor substrate; N-type Doped ions injection technology is adopted to form N trap in described first well region; P type Doped ions injection technology is adopted to form P-region in described second well region bottom; N-type Doped ions injection technology is adopted to form N-region in described second well region top; Form the floating gate structure covering described N trap, isolation structure of shallow trench and part N-region.The present invention is by being made into the second well region be made up of the P-region of bottom and the N-region on top by original P well region, the erasing voltage of MTP device can be improve greatly, do not need the volume increasing erasing electric capacity just greatly can improve the erasing speed of MTP device.Manufacture method of the present invention is simple, compatible with CMOS technology, is applicable to industrial production.
Accompanying drawing explanation
Fig. 1 is shown as MTP device circuitry structural representation of the prior art.
Fig. 2 is shown as the concrete structure schematic diagram of a kind of MTP device architecture of the prior art.
Fig. 3 is shown as the steps flow chart schematic diagram of the manufacture method of MTP device architecture of the present invention.
The structural representation that each step S11 ~ S15 that Fig. 4 ~ Figure 11 is shown as the manufacture method of MTP device architecture of the present invention presents.
Element numbers explanation
101 Semiconductor substrate
102 isolation structure of shallow trench
103 N traps
104 P-regions
105 N-regions
106 floating gate oxide layers
107 floating gate polysilicon layers
108 sidewall structures
109 N+ contact zones
110 source regions
111 drain regions
S11 ~ S15 step
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 3 ~ Figure 11.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Fig. 3 ~ Figure 11, the present embodiment provides a kind of manufacture method of MTP device architecture, at least comprises the following steps:
As shown in figs. 3 and 4, first carry out step S11, semi-conductive substrate 101 is provided, in described Semiconductor substrate 101, produce the isolation structure of shallow trench 102 for isolating the first well region and the second well region.
Exemplarily, this step is also produced for isolating the isolation structure of shallow trench of other device architecture as CMOS etc. simultaneously, in the present embodiment, described Semiconductor substrate 101 is silicon substrate, certainly, in other embodiments, as silicon carbide substrates, germanium silicon substrate etc. are also applicable to the present invention.
Particularly, prior to defining active area in described Semiconductor substrate 101, comprise the regions such as the source-drain area of the first well region, the second well region and CMOS, then dry etching is adopted to etch groove in described Semiconductor substrate 101 according to above-mentioned zone, and the dielectrics such as silicon dioxide are filled in described groove, then adopt back the techniques such as quarter or CMP to form fleet plough groove isolation structure.
As depicted in figs. 3 and 5, then carry out step S12, adopt N-type Doped ions injection technology to form N trap 103 in described first well region.
Particularly, adopt phosphonium ion to carry out ion implantation as Doped ions to described first well region, inject the degree of depth and be generally the degree of depth exceeding described isolation structure of shallow trench 102, then form described N trap 103 after annealed activation.
As shown in Figure 3 and Figure 6, then carry out step S13, adopt P type Doped ions injection technology to form P-region 104 in described second well region bottom.
Particularly, the Doped ions that described P-region 104 is injected is boron, and the scope of Implantation Energy is 160 ~ 240Kev, and the scope of implantation dosage is 1E12 ~ 5E12/cm
2, after activating finally by annealing, form described P-region 104.In the present embodiment, the Implantation Energy making described P-region 104 is 200Kev, and implantation dosage is 3E12/cm
2, the injection degree of depth in described P-region 104 is greater than the degree of depth of described isolation structure of shallow trench 102.
As shown in Fig. 3 and Fig. 7, then carry out step S14, adopt N-type Doped ions injection technology to form N-region 105 in described second well region top.
Particularly, the Doped ions that described N-region 105 is injected is phosphorus, and the scope of Implantation Energy is 60 ~ 120Kev, and the scope of implantation dosage is 5E12 ~ 2E13/cm
2, after activating finally by annealing, form described N-region 105.In the present embodiment, the Implantation Energy making described N-region 105 is 80Kev, and implantation dosage is 1E13/cm
2.
In order to ensure to have higher puncture voltage between this N-region 105 and P trap, in the present embodiment, the degree of depth in described N-region 105 is not more than the degree of depth of described isolation structure of shallow trench 102.
As shown in Fig. 3 and Fig. 8 ~ Figure 11, finally carry out step S15, form the floating gate structure covering described N trap 103, isolation structure of shallow trench 102 and part N-region 105.
Particularly, the making of described floating gate structure comprises step:
As shown in Figure 8, formed successively and be covered in described isolation structure of shallow trench 102, the floating gate oxide layers 106 in N trap 103 and N-region 105 and floating gate polysilicon layer 107.Particularly, thermal oxidation process or plasma enhanced CVD method is adopted to make described floating gate oxide layers 106; The method of vapour phase epitaxy is adopted to make described floating gate polysilicon layer 107.
As shown in Figure 9, adopt photoetching process to remove floating gate oxide layers 106 and the floating gate polysilicon layer 107 of part, retain and be covered in described N trap 103, the floating gate oxide layers 106 in isolation structure of shallow trench 102 and part N-region 105 and floating gate polysilicon layer 107.
As shown in Figure 10, make sidewall structure 108 in described floating gate oxide layers 106 and floating gate polysilicon layer 107 both sides, complete the making of floating gate structure.Particularly, the material of described sidewall structure 108 is silicon dioxide or silicon nitride or silicon dioxide and silicon nitride stack.
Exemplarily, as shown in figure 11, also step is comprised: in the N-region 105 do not covered by described floating gate structure, form N+ contact zone 109.Certainly, also comprising other CMOS technology step, as made the step such as source region 110, drain region 111 of cmos device, can be realized by conventional CMOS technology.
As shown in figure 11, the present embodiment also provides a kind of MTP device architecture, comprising:
Semiconductor substrate 101;
Isolation structure of shallow trench 102, is formed in described Semiconductor substrate 101;
First well region and the second well region, be formed in the Semiconductor substrate 101 of described shallow trench isolation both sides respectively, described first well region is N trap 103, and described second well region comprises the P-region 104 of bottom and the N-region 105 on top;
Floating gate structure, is covered in described N trap 103, isolation structure of shallow trench 102 and part N-region 105.
Exemplarily, described MTP device architecture also comprises the N+ contact zone 109 in the N-region 105 being formed at and not covered by described floating gate structure.Certainly, Figure 11 also shows the structure such as source region 110, drain region 111 of cmos device.
In order to ensure to have higher puncture voltage between this N-region 105 and P trap, in the present embodiment, the degree of depth in described N-region 105 is not more than the degree of depth of described isolation structure of shallow trench 102.
Exemplarily, described floating gate structure comprises the sidewall structure 108 being covered in described N trap 103, the floating gate oxide layers 106 in isolation structure of shallow trench 102 and part N-region 105 and floating gate polysilicon layer 107 and being formed at described floating gate oxide layers 106 and floating gate polysilicon layer 107 both sides.
The present invention is by being made into the second well region be made up of the P-region 104 of bottom and the N-region 105 on top by original P well region, the erasing voltage of MTP device can be improve greatly, in fact the erasing voltage 6V of original device is increased to 12V(, the erasing voltage of MTP device architecture of the present invention reaches as high as 17.3V), do not need the volume increasing erasing electric capacity just greatly can improve the erasing speed of MTP device.
As mentioned above, the invention provides a kind of MTP device architecture and preparation method thereof, described manufacture method comprises step: provide semi-conductive substrate 101, produces the isolation structure of shallow trench 102 for isolating the first well region and the second well region in described Semiconductor substrate 101; N-type Doped ions injection technology is adopted to form N trap 103 in described first well region; P type Doped ions injection technology is adopted to form P-region 104 in described second well region bottom; N-type Doped ions injection technology is adopted to form N-region 105 in described second well region top; Form the floating gate structure covering described N trap 103, isolation structure of shallow trench 102 and part N-region 105.The present invention is by being made into the second well region be made up of the P-region 104 of bottom and the N-region 105 on top by original P well region, the erasing voltage of MTP device can be improve greatly, do not need the volume increasing erasing electric capacity just greatly can improve the erasing speed of MTP device.Manufacture method of the present invention is simple, compatible with CMOS technology, is applicable to industrial production.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a manufacture method for MTP device architecture, is characterized in that, at least comprises the following steps:
Semi-conductive substrate is provided, in described Semiconductor substrate, produces the isolation structure of shallow trench for isolating the first well region and the second well region;
N-type Doped ions injection technology is adopted to form N trap in described first well region;
P type Doped ions injection technology is adopted to form P-region in described second well region bottom;
N-type Doped ions injection technology is adopted to form N-region in described second well region top;
Form the floating gate structure covering described N trap, isolation structure of shallow trench and part N-region.
2. the manufacture method of MTP device architecture according to claim 1, is characterized in that: also comprise step: in the N-region do not covered by described floating gate structure, form N+ contact zone.
3. the manufacture method of MTP device architecture according to claim 1, is characterized in that: the Doped ions that described P-region is injected is boron, and the scope of Implantation Energy is 160 ~ 240Kev, and the scope of implantation dosage is 1E12 ~ 5E12/cm
2.
4. the manufacture method of MTP device architecture according to claim 1, is characterized in that: the Doped ions that described N-region is injected is phosphorus, and the scope of Implantation Energy is 60 ~ 120Kev, and the scope of implantation dosage is 5E12 ~ 2E13/cm
2.
5. the manufacture method of MTP device architecture according to claim 1, is characterized in that: the degree of depth in described N-region is not more than the degree of depth of described isolation structure of shallow trench.
6. the manufacture method of MTP device architecture according to claim 1, is characterized in that: the making of described floating gate structure comprises step:
Formed successively and be covered in described isolation structure of shallow trench, the floating gate oxide layers in N trap and N-region and floating gate polysilicon layer;
Adopt photoetching process to remove floating gate oxide layers and the floating gate polysilicon layer of part, retain and be covered in described N trap, the floating gate oxide layers in isolation structure of shallow trench and part N-region and floating gate polysilicon layer;
Make sidewall structure in described floating gate oxide layers and floating gate polysilicon layer both sides, complete the making of floating gate structure.
7. a MTP device architecture, is characterized in that, comprising:
Semiconductor substrate;
Isolation structure of shallow trench, is formed in described Semiconductor substrate;
First well region and the second well region, be formed in the Semiconductor substrate of described shallow trench isolation both sides respectively, described first well region is N trap, and described second well region comprises the P-region of bottom and the N-region on top;
Floating gate structure, is covered in described N trap, isolation structure of shallow trench and part N-region.
8. MTP device architecture according to claim 7, is characterized in that: also comprise the N+ contact zone in the N-region being formed at and not covered by described floating gate structure.
9. MTP device architecture according to claim 7, is characterized in that: the degree of depth in described N-region is not more than the degree of depth of described isolation structure of shallow trench.
10. MTP device architecture according to claim 7, is characterized in that: described floating gate structure comprises the floating gate oxide layers and floating gate polysilicon layer that are covered in described N trap, isolation structure of shallow trench and part N-region surface and the sidewall structure being formed at described floating gate oxide layers and floating gate polysilicon layer both sides.
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| CN111276485A (en) * | 2020-02-14 | 2020-06-12 | 上海华虹宏力半导体制造有限公司 | MTP device manufacturing method and MTP device |
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| WO2011050464A1 (en) * | 2009-10-30 | 2011-05-05 | Sidense Corp. | Twin well split-channel otp memory cell |
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Application publication date: 20150826 |