CN102386080B - Method for forming metal gate - Google Patents
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- CN102386080B CN102386080B CN201010275184.4A CN201010275184A CN102386080B CN 102386080 B CN102386080 B CN 102386080B CN 201010275184 A CN201010275184 A CN 201010275184A CN 102386080 B CN102386080 B CN 102386080B
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Abstract
The invention provides a method for forming a metal gate. The method comprises the following steps: providing a substrate with a formed gate dielectric layer; forming a sacrificial layer on the gate dielectric layer, wherein the sacrificial layer is doped with ions, the concentration of which is distributed in a gradient manner along with the thicknesses of the ions; etching the sacrificial layer to form a gate-replacing electrode layer which is provided with inclined side walls; forming a dielectric layer level to the surface of the gate-replacing electrode layer on the gate dielectric layer; removing the gate-replacing electrode layer to form a groove with the inclined side walls; and adopting filling materials to fill the groove and forming the metal gate. In the method, the gate-replacing electrode layer with the inclined side walls is formed by etching the sacrificial layer with the concentration of the doped ions being distributed in a gradient manner, and the groove with the inclined side walls is formed after the gate-replacing electrode layer is removed, so that the problems that the resistance value of the metal gate is higher than the target resistance value to be formed, and the higher resistance value causes the increase of power consumption are solved, and the reliability of a semiconductor device formed by the metal gate is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of formation method of metal gates.
Background technology
Along with the reduction of technology node, the continuous attenuation of traditional gate dielectric layer, transistor leakage amount increases thereupon, causes the problems such as semiconductor device power wastage.For addressing the above problem, prior art provides a kind of solution that metal gates is substituted to polysilicon gate.Wherein, " rear grid (gate last) " technique is for forming a main technique of metal gates.
The Chinese patent application that patent publication No. is CN101438389A provides a kind of use " rear grid " technique to form the method for metal gates, comprise: substrate is provided, in described substrate, is formed with alternative gate structure and is positioned at the interlayer dielectric layer that covers described alternative gate structure in described substrate; Using described alternative gate structure as stop-layer, described interlayer dielectric layer is carried out to CMP (Chemical Mechanical Polishing) process; After removing described alternative gate structure, form groove; Finally to described trench fill medium and metal, to form gate dielectric layer and metal gate electrode layer.
In practical application, find, the reliability of the semiconductor device forming by technique scheme is lower.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of metal gates, to solve the lower problem of reliability of the semiconductor device that adopts prior art formation.
For addressing the above problem, the invention provides a kind of formation method of metal gates, comprising:
Substrate is provided, in described substrate, is formed with gate dielectric layer;
On described gate dielectric layer, form sacrifice layer, the thickness that described sacrifice layer has with sacrifice layer is the doping ion that concentration gradient distributes;
Described in etching, sacrifice layer forms alternative gate electrode layer, and described alternative gate electrode layer has sloped sidewall;
On described gate dielectric layer, form dielectric layer, described dielectric layer surface flushes with alternative gate electrode layer surface;
Remove described alternative gate electrode layer, form the groove with sloped sidewall;
Adopt filler to fill described groove, form metal gates.
Optionally, described doping ion is one or more in phosphorus, boron, arsenic, germanium or silicon.
Optionally, the concentration that described gradient is distributed as doping ion increases progressively with the thickness of sacrifice layer or with the thickness-tapered of sacrifice layer.
Optionally, described gradient is distributed as linear distribution or nonlinear Distribution.
Optionally, described sacrificial layer material is one of polysilicon, amorphous silicon, monocrystalline silicon, polycrystalline germanium, amorphous germanium, monocrystalline germanium, SiGe.
Optionally, the etching technics of described sacrifice layer is for to complete by dry etch process is disposable.
Optionally, the etching gas of described dry etching comprises one or more in chlorine, hydrogen bromide or sulphur hexafluoride.
Optionally, the sidewall of described alternative gate electrode layer and the described gate dielectric layer surface scope that acutangulates are 82 ° to 89 °.
Optionally, the etching technics of described sacrifice layer completes jointly by dry etching and wet etching, comprising: described in dry etching, sacrifice layer forms initial alternative gate electrode layer, and described initial alternative gate electrode layer has the sidewall perpendicular to gate dielectric layer; Described in wet etching, initial alternative gate electrode layer forms the alternative gate electrode layer with sloped sidewall.
Optionally, the solution of described wet etching one of is following solution: the mixed solution of hydrofluoric acid and nitric acid; Hydrofluoric acid solution; Potassium hydroxide solution; Tetramethyl ammonium hydroxide solution; Hydrogen peroxide; The mixed solution of hydrogen chloride and hydrogen peroxide; The mixed solution of ammoniacal liquor and hydrogen peroxide.
Optionally, the sidewall of described alternative gate electrode layer and the described gate dielectric layer surface scope that acutangulates are 75 ° to 89 °.
Optionally, described gate dielectric layer is one of silica, silicon oxynitride, silicon nitride or combination.
Optionally, described gate dielectric layer is high K dielectric layer.
Compared with prior art, such scheme has the following advantages: the present invention is by carrying out etching to the sacrifice layer of doping ion concentration distribution gradient, form bottom little, opening is large, the alternative gate electrode layer with sloped sidewall, then after removing alternative gate electrode layer, form the groove with sloped sidewall, after having avoided filler, metal gates produces space, improve the quality of metal gates, avoid the resistance value higher and higher resistance value of target resistance values more to be formed of metal gates to cause the problems such as power consumption rising, improve the reliability of the semiconductor device that contains described metal gates.
Accompanying drawing explanation
Fig. 1 is the method for forming metallic grid schematic flow sheet of one embodiment of the invention.
Fig. 2 to Fig. 8 is the method for forming metallic grid structural representation of one embodiment of the invention.
Fig. 9 to Figure 10 is the method for forming metallic grid structural representation of another embodiment of the present invention.
Embodiment
The reliability of the semiconductor device that prior art forms is lower.Inventor finds, the reliability of semiconductor device is lower is that resistance value due to metal gates causes compared with target resistance values is higher, further studying to find it is because the filler inside of described metal gates exists space, the resistance value of metal gates can be improved in described space, makes it higher compared with target resistance values.
Inventor further finds, the reason that described space forms is as follows: in prior art, the lateral vertical of alternative gate structure is in substrate, so remove the sidewall of the groove that described alternative gate structure forms also perpendicular to described substrate, and the turning at described groove opening place is approximately right angle, so when groove is filled, be positioned near the deposition rate of opening higher, lower the closer to bottom deposition rate, finally will in metal gates, there is space.Along with reducing of grid length, the size of groove also reduces thereupon, will more become difficult to trench fill, further may form space.
For addressing the above problem, the invention provides a kind of formation method of metal gates, as shown in Figure 1, comprising:
Step S1, provides substrate, in described substrate, is formed with gate dielectric layer;
Step S2 forms sacrifice layer on described gate dielectric layer, and described sacrifice layer is doped with ion, and the ion concentration of described sacrifice layer doping is with the thickness distribution gradient of sacrifice layer;
Step S3, sacrifice layer forms alternative gate electrode layer described in etching, and described alternative gate electrode layer has the sidewall of inclination;
Step S4 forms dielectric layer on described gate dielectric layer, and described dielectric layer surface flushes with alternative gate electrode layer surface;
Step S5, removes described alternative gate electrode layer, forms the groove with sloped sidewall;
Step S6, adopts filler to fill described groove, forms metal gates.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 2 to Fig. 8 is the method for forming metallic grid structural representation of one embodiment of the invention.
As shown in Figure 2, provide substrate 110, in described substrate 110, be formed with gate dielectric layer 120.In described substrate 110, be also formed with isolation structure 100, for isolating the active area of follow-up formation.
Described substrate 110 can be selected from the silicon (SOI) on silicon base, insulating barrier or can also be other material, such as III-V compounds of group such as GaAs.Described gate dielectric layer 120 is one of silica, silicon oxynitride, silicon nitride or combination.
Continuation, with reference to figure 2, forms sacrifice layer 130 on described gate dielectric layer 120.The material of described sacrifice layer 130 is one of polysilicon, amorphous silicon, monocrystalline silicon, polycrystalline germanium, amorphous germanium, monocrystalline germanium, SiGe.
Described sacrifice layer 130 is doped with ion, described doping ion is corresponding as follows with the material of sacrifice layer 130: if the material of described sacrifice layer 130 is one of polysilicon, amorphous silicon, monocrystalline silicon, described doping ion can in phosphorus, boron, arsenic, germanium one or more; If the material of described sacrifice layer 130 is one of polycrystalline germanium, amorphous germanium, monocrystalline germanium, described doping ion can in phosphorus, boron, arsenic, silicon one or more; If the material of described sacrifice layer 130 is SiGe, described doping ion can be one or more in phosphorus, boron, arsenic.
Further, the ion doping concentration in described sacrifice layer 130 is with the thickness distribution gradient of sacrifice layer 130, and described gradient is distributed as that ion concentration increases progressively with the thickness of sacrifice layer 130 or with the thickness-tapered of sacrifice layer 130.It can also be linear distribution or nonlinear Distribution that described gradient distributes.
As an embodiment, described in there is concentration increasing or decreasing sacrifice layer 130 can distinguish in the following manner and obtain:
1, by chemical vapour deposition technique, form and there is concentration and increase progressively sacrifice layer 130, specifically comprise: in the time of deposition of sacrificial layer 130, adopt impurity gas to carry out ion doping to sacrifice layer 130, and along with the deposit thickness of described sacrifice layer 130 increases, increase gradually flow or the concentration of impurity gas, form the sacrifice layer 130 that ion concentration increases progressively with the thickness of sacrifice layer 130.The top doping ion concentration of described sacrifice layer 130 is maximum, and bottom doping ion concentration is minimum.
The sacrifice polysilicon layer that the formation boron ion concentration of take increases progressively with sacrifice polysilicon layer thickness is example, when adopting existing technique to form sacrifice polysilicon layer, adopts boron trifluoride (BF
3) sacrifice polysilicon layer is adulterated, along with the increase of polysilicon deposition thickness, increase boron trifluoride (BF
3) flow, form the sacrifice polysilicon layer that boron ion concentration increases progressively with sacrifice polysilicon layer thickness.
2, by chemical vapour deposition technique, form and there is the concentration sacrifice layer 130 that successively decreases, specifically comprise: in the time of deposition of sacrificial layer 130, adopt impurity gas to carry out ion doping to sacrifice layer 130, and along with the deposit thickness of described sacrifice layer 130 increases, reduce gradually flow or the concentration of impurity gas, form ion concentration with the sacrifice layer 130 of the thickness-tapered of sacrifice layer 130.The top doping ion concentration of described sacrifice layer 130 is minimum, and bottom doping ion concentration is maximum.
The sacrifice polysilicon layer that the formation phosphate ion concentration of take successively decreases with sacrifice polysilicon layer thickness is example, when adopting existing technique to form sacrifice polysilicon layer, adopts phosphine (PH
3) sacrifice polysilicon layer is adulterated, along with the increase of polysilicon deposition thickness, reduce phosphine (PH
3) flow, form the sacrifice polysilicon layer that phosphate ion concentration successively decreases with sacrifice polysilicon layer thickness.
As shown in Figure 3, form the hard mask layer 140 of patterning on described sacrifice layer 130, the pattern of described hard mask layer 140 is corresponding with the alternative gate electrode layer position of follow-up formation.
As shown in Figure 4, the described hard mask layer 140 of take is mask, and described sacrifice layer 130 is carried out to etching, forms alternative gate electrode layer 150.Along with the carrying out of etching, the sidewall of alternative gate electrode layer 150 will shrink gradually, finally obtain the alternative gate electrode layer 150 that a little top width of bottom width is large, have sloped sidewall.Through a large amount of creative work of inventor, find that the sidewall of described alternative gate electrode layer 150 is 82 ° to 89 ° with the acute angle scope that described gate dielectric layer 120 surfaces become, follow-up filling effect is more excellent.
Particularly, described etching gas comprises one or more in chlorine, hydrogen bromide or sulphur hexafluoride.Wherein, for having different ion concentration gradients, distribute, the selection of etching gas is different, specifically comprises:
1, the sacrifice layer 130 successively decreasing to bottom from top for ion concentration, the etching gas of selection has lower lateral etching rate to the higher sacrifice layer 130 of ion concentration, for the lower sacrifice layer 130 of ion concentration, has higher lateral etching rate.The etching of etching gas by having lateral etching rate difference to sacrifice layer 130, obtains the alternative gate metal level 150 that top width is greater than bottom width.
As an embodiment, the doping ion of take is phosphonium ion, the ion concentration of described sacrifice layer 130 is decremented to example, can select bromize hydrogen gas to carry out etching to described sacrifice layer 130, along with etching process, described etching gas lateral etching rate rate increases, and finally forms the alternative gate electrode layer 150 that top width is greater than bottom width.The flow of described bromize hydrogen gas is 50sccm to 250sccm, and described etch period is 10 seconds to 100 seconds; The chamber pressure of described etching is 5 millitorr to 50 millitorrs; Described etching power is 500 watts to 1000 watts.
2, the sacrifice layer 130 increasing progressively to bottom from top for ion concentration, the etching gas of selection has lower lateral etching rate to the lower sacrifice layer 130 of ion concentration, for the higher sacrifice layer 130 of ion concentration, has higher lateral etching rate.Etching by the described etching gas with lateral etching rate difference to sacrifice layer 130, obtains the alternative gate metal level 150 that top width is greater than bottom width.
As shown in Figure 5, remove hard mask layer 140; Then the described alternative gate electrode layer 150 of take is mask, in the interior formation shallow ion of described substrate 110 doped region 161; Then, in the substrate 110 of described alternative gate electrode layer 150 both sides, form side wall 170, and to take described side wall 170 be mask, in the interior formation of described substrate 110 source/drain region 162.In other embodiments, also can directly to the substrate 110 of alternative gate electrode layer 150 both sides, carry out source/leakage Implantation, formation source/drain region; The formation in described source/drain region also can form technique with reference to existing source/drain region, does not here just exemplify one by one.
As shown in Figure 6, metallization medium layer 180 on described gate dielectric layer 120, described dielectric layer 180 covers described alternative gate electrode layer 150; Then the described alternative gate electrode layer 150 of take is stop-layer, to described dielectric layer 180 planarizations.
As shown in Figure 7, remove described alternative gate electrode layer 150, form groove 151.Because described alternative gate electrode layer 150 has the sidewall of inclination, so remove the sidewall that the groove 151 of alternative gate electrode layer 150 rear formation also has inclination.In the present embodiment, the top width of described groove 151 is greater than bottom width, preferred, and its sidewall and the described gate dielectric layer 120 surface scopes that acutangulate are 82 ° to 89 °.
The removal method of described alternative gate electrode layer 150 can be dry etching or wet etching: if dry etching, can adopt comprise chloro, fluorine-based gas ions is carried out etching; If wet etching, can adopt Ammonia to carry out etching removal, or also can adopt the mixed solution of nitric acid and hydrofluoric acid to carry out etching removal.
As shown in Figure 8, adopt filler to fill described groove 151, form metal gate electrode layer 190.Described gate dielectric layer 120 and metal gate electrode layer 190 form metal gate structure.
Wherein, the material of described metal gate electrode layer 190 can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.
In the present embodiment, the gate dielectric layer that described gate dielectric layer 120 is metal gate structure, as other embodiment, can also adopt high K dielectric as the gate dielectric layer of metal gates, specifically comprise: before adopting filler to fill described groove 151, remove described gate dielectric layer 120, expose the surface of substrate 110; To exposing the groove 151 on substrate 110 surfaces, fill successively high K dielectric and metal, to form high-K gate dielectric layer and metal gates.
Described high K dielectric can be that hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc etc. are a kind of.Described metal gate electrode layer material can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.In the present embodiment, the formation method of described groove 151 is for to form by a step dry etching, its processing step is simple, save process costs, but a step dry etching usually faces the problem that etching precision is not high, the more difficult control of etching process, the present invention also provides a kind of formation method of metal gates, further to improve etching groove precision.
Fig. 9 to Figure 10 is the method for forming metallic grid structural representation of another embodiment of the present invention.
As shown in Figure 1, execution step S1～S4, the specific embodiment of described step can be with reference to aforementioned, simultaneously with reference to figure 2～3.Form structure as shown in Figure 3, comprise: substrate 110, be positioned at gate dielectric layer 120 and the sacrifice layer 130 of described substrate 110, and be positioned at the hard mask layer 140 of patterning on described sacrifice layer, the pattern of described hard mask layer 140 is corresponding with the alternative gate electrode layer position of follow-up formation.In described substrate 110, be also formed with isolation structure 100, for isolating the active area of follow-up formation.
As shown in Figure 9, the described hard mask layer 140 of take is mask, and described sacrifice layer 130 is carried out to etching, forms initial alternative gate electrode layer 210.The sidewall of described initial alternative gate electrode layer 210 is perpendicular to described gate dielectric layer 120.
Described etching technics can be existing etching technics, and particularly, the etching gas of selection can be one or more in chlorine, hydrogen bromide or sulphur hexafluoride.Described etching gas is insensitive to the ion concentration gradient of sacrifice layer 130, and etching forms sidewall perpendicular to described gate dielectric layer 120.
As shown in figure 10, described initial alternative gate electrode layer 210 is revised, formed alternative gate electrode layer 250.The described wet etching that is modified to.Described alternative gate electrode layer 250 has sloped sidewall, and the little top width of its bottom width is large.Wherein, the sidewall of described alternative gate electrode layer 250 and the described gate dielectric layer 120 surface scopes that acutangulate are 75 ° to 89 °.
Also it should be noted that, in the present embodiment, adopt first etching to form the alternative gate electrode layer of vertical sidewall, adopt wet-etching technology to form the alternative gate electrode layer with sloped sidewall again, have etching accurate, the alternative gate electrode layer precision with sloped sidewall of formation is high.And compare with the sidewall that a step dry etching forms, the acute angle scope that the sidewall that after the first dry etching of described employing, wet etching forms becomes with gate dielectric layer is larger.
The solution of described wet etching is one of following solution: the mixed solution of hydrofluoric acid and nitric acid; Hydrofluoric acid solution; Potassium hydroxide solution; Tetramethyl ammonium hydroxide solution; Hydrogen peroxide; The mixed solution of hydrogen chloride and hydrogen peroxide; The mixed solution of ammoniacal liquor and hydrogen peroxide.Wherein, for having different ion concentration gradients, distribute, the selection of described etching solution is different, specifically comprises:
1, the sacrifice layer 130 successively decreasing to bottom from top for ion concentration, the etching solution of selection has lower lateral etching rate to the higher sacrifice layer 130 of ion concentration, for the lower etching sacrificial layer 130 of ion concentration, has higher lateral etching rate.The etching of etching solution by having lateral etching rate difference to sacrifice layer 130, obtains the alternative gate metal level 150 that top width is greater than bottom width.
As an embodiment, the doping ion of take is phosphonium ion, the ion concentration of described sacrifice layer 130 is decremented to example from top to bottom, can select the mixed solution of hydrofluoric acid and nitric acid to carry out etching to described sacrifice layer 130, along with etching process, the mixed solution of hydrofluoric acid and nitric acid has lateral etching rate difference, finally forms the alternative gate electrode layer 150 that top width is greater than bottom width.Mixing ratio in the mixed solution of described hydrofluoric acid and nitric acid is 5: 1, and described etch period is 10 seconds to 100 seconds.
2, the sacrifice layer 130 increasing progressively to bottom from top for ion concentration, the etching solution of selection has lower lateral etching rate to the lower sacrifice layer 130 of ion concentration, for the higher sacrifice layer 130 of ion concentration, has higher lateral etching rate.Etching by the described etching solution with lateral etching rate difference to sacrifice layer 130, obtains the alternative gate metal level 150 that top width is greater than bottom width.
After formation has the alternative gate electrode layer 250 of sloped sidewall, also be included in metallization medium layer on described gate dielectric layer, remove alternative gate electrode layer formation groove, adopt filler filling groove to form the steps such as metal gate electrode layer, described step can, with reference to aforementioned, just not be described in detail herein.
The present invention is by carrying out etching to the sacrifice layer of doping ion concentration distribution gradient, utilize etching gas or etching solution the sacrifice layer of ion concentration distribution gradient to be there is to the difference of the lateral etching rate relevant to ion concentration simultaneously, form bottom little, the alternative gate electrode layer that opening is large, have sloped sidewall, then after removing alternative gate electrode layer, form the groove with sloped sidewall, after having avoided filler, metal gates produces space, improves the quality of metal gates.Further, the present invention adopts etching technics once to form to have the alternative gate electrode layer of sloped sidewall, has technique simple, and the advantage that processing step is saved, enhances productivity; The present invention adopts first etching to form the alternative gate electrode layer of vertical sidewall, then adopts wet-etching technology to form the alternative gate electrode layer with sloped sidewall, has etching accurate, and the alternative gate electrode layer precision with sloped sidewall of formation is high.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
Claims (13)
1. a formation method for metal gates, is characterized in that, comprising:
Substrate is provided, in described substrate, is formed with gate dielectric layer;
On described gate dielectric layer, form sacrifice layer, the thickness that described sacrifice layer has with sacrifice layer is the doping ion that concentration gradient distributes;
Described in etching, sacrifice layer forms alternative gate electrode layer, in the etching process of etching sacrificial layer, concentration gradient to the lateral etching speed of sacrifice layer along with the doping ion in sacrifice layer distributes and increases, described alternative gate electrode layer has sloped sidewall, and the little top width of the bottom width of described alternative gate electrode layer is large;
On described gate dielectric layer, form dielectric layer, described dielectric layer surface flushes with alternative gate electrode layer surface;
Remove described alternative gate electrode layer, form the groove with sloped sidewall;
Adopt filler to fill described groove, form metal gates.
2. the formation method of metal gates according to claim 1, is characterized in that, described doping ion is one or more in phosphorus, boron, arsenic, germanium or silicon.
3. the formation method of metal gates according to claim 1, is characterized in that, the concentration that described gradient is distributed as doping ion increases progressively with the thickness of sacrifice layer or with the thickness-tapered of sacrifice layer.
4. the formation method of metal gates according to claim 3, is characterized in that, described gradient is distributed as linear distribution or nonlinear Distribution.
5. the formation method of metal gates according to claim 1, is characterized in that, described sacrificial layer material is one of polysilicon, amorphous silicon, monocrystalline silicon, polycrystalline germanium, amorphous germanium, monocrystalline germanium, SiGe.
6. the formation method of metal gates according to claim 1, is characterized in that, the etching technics of described sacrifice layer is for to complete by dry etch process is disposable.
7. the formation method of metal gates according to claim 6, is characterized in that, the etching gas of described dry etching comprises one or more in chlorine, hydrogen bromide or sulphur hexafluoride.
8. the formation method of metal gates according to claim 7, is characterized in that, the sidewall of described alternative gate electrode layer and the described gate dielectric layer surface scope that acutangulates are 82 ° to 89 °.
9. the formation method of metal gates according to claim 1, it is characterized in that, the etching technics of described sacrifice layer completes jointly by dry etching and wet etching, comprise: described in dry etching, sacrifice layer forms initial alternative gate electrode layer, described initial alternative gate electrode layer has the sidewall perpendicular to gate dielectric layer; Described in wet etching, initial alternative gate electrode layer forms the alternative gate electrode layer with sloped sidewall.
10. the formation method of metal gates according to claim 9, is characterized in that, one of the solution of described wet etching is following solution: the mixed solution of hydrofluoric acid and nitric acid; Hydrofluoric acid solution; Potassium hydroxide solution; Tetramethyl ammonium hydroxide solution; Hydrogen peroxide; The mixed solution of hydrogen chloride and hydrogen peroxide; The mixed solution of ammoniacal liquor and hydrogen peroxide.
The 11. formation methods of metal gates according to claim 10, is characterized in that, the sidewall of described alternative gate electrode layer and the described gate dielectric layer surface scope that acutangulates are 75 ° to 89 °.
The 12. formation methods of metal gates according to claim 1, is characterized in that, described gate dielectric layer is one of silica, silicon oxynitride, silicon nitride or combination.
The 13. formation methods of metal gates according to claim 1, is characterized in that, described gate dielectric layer is high K dielectric layer.
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| CN103367133B (en) * | 2012-03-29 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | High-dielectric constant metal grid pole manufacture method |
| CN103515197A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned multi-patterning mask layer and formation method thereof |
| US8835237B2 (en) | 2012-11-07 | 2014-09-16 | International Business Machines Corporation | Robust replacement gate integration |
| JP2014116707A (en) * | 2012-12-07 | 2014-06-26 | Seiko Epson Corp | Method of manufacturing vibrator |
| CN104658895B (en) * | 2013-11-15 | 2017-10-17 | 中国科学院微电子研究所 | Sacrificial gate main body forming method and method, semi-conductor device manufacturing method that section improves |
| CN110148596B (en) * | 2018-02-12 | 2020-11-10 | 联华电子股份有限公司 | Bit line grid structure of dynamic random access memory and forming method thereof |
| CN111341652B (en) * | 2018-12-19 | 2023-04-28 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor device and forming method thereof |
| CN112670172A (en) * | 2020-12-29 | 2021-04-16 | 上海集成电路装备材料产业创新中心有限公司 | Preparation method of metal gate device |
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| US6433371B1 (en) * | 2000-01-29 | 2002-08-13 | Advanced Micro Devices, Inc. | Controlled gate length and gate profile semiconductor device |
| CN1476064A (en) * | 2002-08-14 | 2004-02-18 | 上海宏力半导体制造有限公司 | Method of forming light doped drain electrode using inverse taper grid structure |
| TW200903732A (en) * | 2007-07-03 | 2009-01-16 | Nanya Technology Corp | Method for manufacturing flash memory |
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| US6433371B1 (en) * | 2000-01-29 | 2002-08-13 | Advanced Micro Devices, Inc. | Controlled gate length and gate profile semiconductor device |
| CN1476064A (en) * | 2002-08-14 | 2004-02-18 | 上海宏力半导体制造有限公司 | Method of forming light doped drain electrode using inverse taper grid structure |
| TW200903732A (en) * | 2007-07-03 | 2009-01-16 | Nanya Technology Corp | Method for manufacturing flash memory |
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