CN220914254U - Photoelectric calculation unit and photoelectric calculation assembly - Google Patents

Abstract

The utility model discloses a photoelectric calculation unit with high photoelectric conversion efficiency and a photoelectric calculation assembly. The photoelectric computing unit comprises a grid region which is sequentially formed on a substrate collecting region and comprises a bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control grid, and a source end and a drain end which are formed on the same substrate collecting region and are positioned on two opposite sides of the grid region, wherein the source end and the drain end are respectively far away from the grid region by a preset threshold distance in the horizontal direction, so that the source end and the drain end are not vertically overlapped with the grid region due to the horizontal diffusion of the source end and the drain end caused by an annealing process. The photoelectric calculation unit performs large-space source end and drain end design, and ensures that the source end and the drain end respectively have small-gradient ion doping concentration distribution with the grid electrode region, so that the device realizes high-level light input efficiency.

Description

Photoelectric calculation unit and photoelectric calculation assembly

Technical Field

The present utility model relates to a device structure and a semiconductor process, and more particularly, to a photoelectric calculation unit capable of realizing optical input with high photoelectric conversion efficiency, and a photoelectric calculation assembly.

Background

In principle, the existing electronic computer can transfer, add, subtract, phase inversion and other characteristics of specific electric signals according to semiconductor materials, and can complete extremely complex operation through integration. This calculation has in fact formed an important basis for modern civilization.

Most of the conventional computers adopt von neumann architecture, however, the von neumann architecture memory cell and the operation unit are separated, and when processing a class of algorithms represented by a neural network algorithm, because the weights of the network need to be repeatedly called, the separation of the memory cell and the operation unit causes great energy consumption in data transmission and affects the operation speed. Meanwhile, in a series of algorithms represented by a neural network algorithm and a CT algorithm, a large amount of operation matrix vector multiplication is needed, and the scale of a traditional multiplier is very large, so that the energy efficiency ratio and the integration degree of the traditional calculation in processing the algorithms are greatly influenced.

To overcome this limitation, memory-accounting integrated devices have been proposed. Typical integrated memory devices are mainly two types, namely RRAM (memristor) and FLASH (FLASH memory), the RRAM can store resistance values influenced by input quantity of an electric input end of the RRAM for a long time after power failure, however, the RRAM does not support standard CMOS (complementary metal oxide semiconductor) process production, the yield and uniformity of the devices are not guaranteed, and the RRAM is unacceptable in a neural network algorithm which can be accelerated by using a large amount of integrated memory devices to form a network. If FLASH is to be used as a memory-to-compute device, this means that a single floating gate must store more than one bit of data, i.e., multi-valued storage, which is difficult to do with conventional FLASH that can only change threshold values using both erase and program modes.

As a typical integrated technical scheme for memory calculation, the photoelectric calculation unit (patent number: CN 111208865A) has the characteristics of good consistency, high single-device memory bit width, compatibility with standard CMOS (complementary metal oxide semiconductor) technology and the like, and in the patent photoelectric calculation unit, the photoelectric calculation array and the photoelectric calculation method (patent number: CN 111208865A) disclosed in 2018, numerous specific implementation schemes of the photoelectric calculation unit, and a calculation device and a calculation method based on the unit are provided. The implementation schemes of the photoelectric calculation unit, the photoelectric calculation array and the photoelectric calculation method (patent number: CN 111208865A) can realize high-bit nonvolatile storage of a single device level, the storage time can reach the order of 10 years at the highest, and have the advantages of greater use convenience and calculation energy efficiency.

Disclosure of utility model

According to one aspect of the present utility model, there is provided a photoelectric computing unit comprising a gate region including a bottom dielectric layer, a charge coupled layer, a top dielectric layer and a control gate electrode, formed in this order on a substrate collection region, and a source terminal and a drain terminal formed on the same substrate collection region and located on opposite sides of the gate region, wherein the source terminal and the drain terminal are respectively spaced apart from the gate region by a predetermined threshold distance in a horizontal direction, such that horizontal diffusion of the source terminal and the drain terminal caused by an annealing process does not vertically overlap the source terminal and the drain terminal with the gate region.

The photoelectric calculation unit provided by the embodiment of the utility model adopts the photoelectric property of the semiconductor material, and modulates the electric signals transmitted in the semiconductor material by using the external input optical signals so as to realize adders, multipliers and some advanced operations. In addition, the device can realize a high-precision integrated storage-calculation function, a single device can store the optical signal of the optical input end and store the optical signal for a long time after the optical signal is cut off, and the index of the exposure efficiency is subjected to targeted optimization, so that the device can realize shorter optical data writing time compared with the traditional scheme.

Wherein the source terminal and the drain terminal are respectively far away from the gate region by one tenth of the gate length or 20nm in the horizontal direction.

The junction formed by the source end and the substrate collecting region and the junction formed by the drain end and the substrate collecting region are respectively provided with a slowly-changing concentration gradient, so that the doping concentrations of the N-type source end and the N-type drain end which are prepared on the P-type substrate collecting region to the vertical section of the P-type substrate collecting region are respectively provided with n+/N/N-/P-/P concentration gradient distribution; or the doping concentration of the vertical section from the P type source end and the P type drain end which are prepared on the N type substrate collecting area to the N type substrate collecting area is provided with the concentration gradient distribution of p+/P/P-/N-/N respectively.

The thickness of the insulating side wall used for injecting the source end and the drain end at two sides of the grid electrode region is at least one fifth of the minimum value of the device grid electrode length and 0.1um, the side wall is used for a source-drain injection process of the photoelectric computing unit, and the source end and the drain end generated by an annealing process cannot vertically overlap with the grid electrode region due to horizontal diffusion of the source end and the drain end.

The photoelectric computing unit uses a mask plate and photoresist to define ion implantation positions of the source end and the drain end in a preparation process, wherein the width of the photoresist covered on the source end and/or the drain end is at least one fifth of the minimum value of the gate length and 0.1um of the device, so that the horizontal diffusion of the source end and the drain end generated by an annealing process can not cause the vertical overlapping of the source end and the drain end region and the gate region.

Two different ions are used in the process of source and drain ion implantation, so that a junction formed by the source end and the substrate collecting area and a junction formed by the drain end and the substrate collecting area are provided with a gradual concentration gradient.

And after etching the control grid and before depositing the side wall, injecting a doping layer with polarity opposite to that of the substrate collecting region into the photoelectric calculating unit in the preparation process, so that the doping concentration at the junction formed by the source end and the substrate collecting region and the junction formed by the drain end and the substrate collecting region is diluted to form a concentration gradient of N-/P-relative to the P-type substrate collecting region or a concentration gradient of P-/N-relative to the N-type substrate collecting region, and the photoelectric calculating unit is provided with a gradual concentration gradient at the junction formed by the source end and the substrate collecting region and the junction formed by the drain end and the substrate collecting region respectively.

The doping concentration in the depletion region of the substrate collecting region is high, and the doping outside the depletion region has a gradient structure which gradually changes from low to high, so that the doping concentration in the depletion region of the substrate collecting region changes from high-low to high.

According to another embodiment of the present utility model, there is provided a photoelectric computing assembly including a plurality of the photoelectric computing units as defined in any one of the above, a plurality of the photoelectric computing units being disposed on at least one plane, the operations of the plurality of the photoelectric computing units being controlled by wiring.

When a row and column site selection is carried out on one photoelectric computing unit in an array formed by a plurality of photoelectric computing units, the source ends and the drain ends of the photoelectric units in different rows float.

The utility model designs a photoelectric calculation unit by adopting photoelectric performance of semiconductor materials, and discloses various adders, multipliers and algorithm accelerators which are composed of the photoelectric calculation unit. Therefore, the utility model utilizes the photoelectric characteristic of the semiconductor material and the expansion application of the technology commonly used in the traditional optical field in the computing field, and provides a brand-new photoelectric computing unit which can realize the high-precision storage-calculation integrated function, a single device can store the optical signal of the optical input end and store the optical signal for a long time after the optical interruption, and can realize that the multiplication operation is completed by the single device, thereby being very suitable for accelerating algorithms which are represented by neural network algorithms and need 'storage parameters'.

Additional features and advantages of the utility model will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model. The objectives and other advantages of the utility model will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate the utility model and together with the embodiments of the utility model, and not constitute a limitation to the utility model, and wherein:

fig. 1 is a front view showing a related art photoelectric calculation unit.

Fig. 2 is a 3D schematic diagram showing a prior art photoelectric calculation unit.

Fig. 3 is a front view showing an optical-electrical computing unit according to a first embodiment of the present utility model.

Fig. 4 is a 3D schematic diagram showing a photoelectric calculation unit according to the first embodiment of the present utility model.

Fig. 5 is a schematic diagram showing a thickened sidewall source drain self-aligned implantation scheme according to a first embodiment of the present utility model.

Fig. 6 is a schematic diagram showing a structure after thickened sidewall source drain implantation according to the first embodiment of the present utility model.

Fig. 7 is a schematic diagram showing a photoresist source drain implantation scheme according to a first embodiment of the present utility model.

Fig. 8 is a schematic view showing a source-drain doping structure according to a second embodiment of the present utility model.

Fig. 9 is a schematic view showing a dilute doping process according to a second embodiment of the present utility model.

Fig. 10 is a schematic diagram showing the structure of a special doping profile photo-electric calculation unit according to a third embodiment of the present utility model.

Fig. 11 is a schematic diagram showing a photoelectric calculation unit of high photoelectric conversion efficiency according to a fourth embodiment of the present utility model.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, various embodiments according to the present utility model will be described in detail with reference to the accompanying drawings, in which substantially the same steps and elements are denoted by the same reference numerals, and repeated explanation of the steps and elements will be omitted.

It should be understood that the described embodiments are merely some, but not all embodiments of the present utility model. All other embodiments, which can be derived by a person skilled in the art without any inventive effort, based on the embodiments described in the present utility model shall fall within the scope of protection of the present utility model. Moreover, a detailed description of functions and configurations well known in the art will be omitted for the sake of clarity and conciseness of the present specification.

Hereinafter, 4 preferred embodiments of the photoelectric computing unit according to the present utility model will be described in detail with reference to the accompanying drawings. The embodiments described in the present utility model are merely examples and the steps and means in the embodiments of the present utility model are not limited to practice in a certain embodiment, and those skilled in the art may combine and combine some steps and means from the separately described embodiments according to the inventive concept to achieve the effects of the present utility model, and some variations, modifications, changes, additions and sub-combined embodiments of these embodiments are also included in the present utility model, which are not described one by one.

First embodiment

The details of the photoelectric calculation unit according to the related art and the photoelectric calculation unit according to the first embodiment of the present utility model are described with reference to fig. 1 to 7.

As shown in front and perspective views of the photoelectric computing units in the prior art of fig. 1 and 2, the source and drain terminals of the standard photoelectric computing unit are respectively adjacent to the gate region formed by the control gate, the top dielectric layer, the charge coupling layer and the bottom dielectric layer in the horizontal direction, while the photoelectric computing unit of the embodiment of the present utility model is shown in front and perspective views of the photoelectric computing units of fig. 3 and 4, and the source and drain terminals are respectively separated from the gate region by a predetermined threshold distance in the horizontal direction. Alternatively, the source terminal of the photo-calculation unit may be horizontally distant from the gate region first threshold. In addition, alternatively, the drain terminal of the photoelectric calculation unit may be distant from the gate region by the second threshold in the horizontal direction. Alternatively, the first threshold may be the same as or different from the second threshold. In one example, the first threshold and the second threshold may alternatively be one tenth of the gate length, respectively, i.e. the source terminal and the drain terminal may be at least one tenth of the gate length of the device, respectively, away from the gate region in the horizontal direction, wherein the gate length refers to the length of the gate region in the direction in which the source terminal and the drain terminal are connected. For example, the first threshold and/or the second threshold may be 15nm,25nm,35nm, etc. when the device gate length is 0.15um, and 10nm,20nm,30nm, etc. when the device gate length is 0.1 um. In another example, the first threshold and/or the second threshold may optionally be at least 20nm, for example, when the device gate length is 5um, the first threshold and/or the second threshold may be 20nm,30nm,50nm, etc., and when the device gate length is 10um, the first threshold and/or the second threshold may be 20nm,30nm,50nm, etc.

Firstly, the space between the source end and the drain end and the grid electrode region in the structure can be provided with a longer Lightly Doped Drain (LDD) region so as to reduce the curvature of a source-drain junction region which is most easy to generate avalanche breakdown and further increase the avalanche voltage; in addition, it is known that a larger junction depth of the source-drain junction represents a larger avalanche voltage, and the space can support the source-drain junction to be deeper so that diffusion in the horizontal direction does not go deep under the gate to compress the channel length, so that the structure can greatly improve the avalanche voltage of the photoelectric calculation unit.

The mechanism of the photoelectric calculation unit in the utility model for light input is substrate hot carrier injection, which needs to apply a negative voltage on the substrate to enable photo-generated electrons to accelerate into hot electrons in the depletion region of the substrate and inject into the charge coupling region. This means that the larger the absolute value of the substrate negative voltage applied at the time of light input, the larger the electric field can be formed in the substrate depletion layer to accelerate the photo-generated electrons, but the substrate voltage tends to be restricted by the avalanche mechanism, so increasing the avalanche voltage of the photoelectric calculation unit can allow an increase in the substrate voltage, thereby increasing the light input efficiency.

The utility model provides two schemes for forming the photoelectric calculation unit structure with the source end and the drain end respectively far away from the grid electrode area, which is specifically described as follows:

1. And when the photoelectric calculation unit is prepared, growing thicker side walls for enabling the source end and the drain end to be far away from the grid electrode area during source and drain injection. As shown in the schematic diagram of the thickened sidewall source drain self-aligned implantation scheme of fig. 5, in the conventional process flow, the source drain is implanted after the insulating sidewall is deposited, and in order to reduce the size of the device, the sidewall is made as thin as possible, so that after the source drain is implanted, the source end and the drain end diffuse along the horizontal direction so as to overlap the gate region in the vertical direction. The thickness of the side wall in the embodiment of the utility model is related to the size of the device, and is at least one fifth of the minimum value of the device gate length and 0.1um, for example, when the device gate length is 0.3um, the thickness of the side wall can be 0.06um, 0.1um and 0.2um; when the gate length of the device is 2um, the thickness of the side wall can be 0.1um,0.2um,0.4um and the like. The above selection of the thickness of the side wall is only an example, and in practical application, the side wall with the corresponding thickness can be selected according to the application scenario and the device requirement to prepare the photoelectric calculation unit.

2. And when the photoelectric computing unit is prepared, the source and the drain are injected by using a mask. After the side wall is deposited, a mask is applied to implant the control gate and the source drain, as shown in the schematic diagram of the photoresist source drain implantation scheme of fig. 7, in order to ensure that no gap is left between the photoresist and the gate region, the photoresist is made wider and covers a part of the gate region. For example, in the embodiment of the utility model, the typical width of the photoresist covered on the gate region may be 10-70 nm, the width of the photoresist covered on the source-drain region is related to the device size, which is at least one fifth of the device gate length and the minimum value of 0.1um, for example, the width of the photoresist in the source-drain region may be 0.06um, 0.1um and 0.2um when the device gate length is 0.3 um; when the gate length of the device is 2um, the width of the photoresist in the source-drain region can be 0.1um,0.2um,0.4um, etc. The above selection of the photoresist width of the source/drain region is merely an example, and in practical application, the sidewall with a corresponding thickness may be selected according to the application scenario and the device requirement to prepare the photoelectric calculation unit.

The two schemes for realizing the photoelectric calculation unit structure that the source end and the drain end are respectively far away from the grid electrode region can be respectively used in preparation, and can also be combined for use according to the requirements of practical application, and the scheme is not limited.

Second embodiment

A photoelectric calculation unit according to a second embodiment of the present utility model is described with reference to fig. 8 to 9.

As shown in the schematic diagram of the source-drain doping structure in fig. 8, the doping at the source-drain junction of the present utility model may take a highly graded structure, taking a P-type substrate collection region as an example, and the doping concentration of the vertical section from the N-type source-drain to the P-type substrate collection region may be a concentration gradient of n+/N/N-/P-/P. The smaller concentration gradient means a larger depletion region, and the avalanche threshold voltage is closely related to the thickness of the depletion region, so that the avalanche voltage can be effectively improved by implementing the source-drain doping structure.

The utility model provides two schemes for forming the photoelectric calculation unit with the source-drain doping structure, wherein the two schemes can be used simultaneously or respectively:

1. When the photoelectric calculation unit is prepared, two different ions are used during source and drain injection, the concentration gradient of the source and drain junction is smaller by utilizing the characteristic that the diffusion speed of the different ions is different, large-area depletion is formed, and the avalanche voltage is improved.

2. When the self-aligned implantation is prepared by the photoelectric calculation unit, a doping with the polarity opposite to that of the substrate collecting region is implanted after the control gate is etched and before photoresist for etching the control gate is removed so as to dilute the doping concentration of the substrate collecting region, which is positioned near the source-drain junction, of the substrate collecting region, and the doping is hereinafter referred to as diluted doping. And after diluted doping, removing photoresist, depositing a side wall and injecting source and drain. The concentration gradient of the source-drain junction is smaller due to dilution doping, so that large-area depletion is formed, and the avalanche voltage is improved. The dilute dopant implantation depth may be greater than the LDD with the purpose of diluting the substrate dopant concentration at the source-drain junction to form a smaller concentration gradient. For example, the implantation energy of the diluted doping may be 60keV to 150keV, so that the implantation depth is 0.1um to 0.3um, and because the implantation energy of the implantation is larger, if the conventional LDD implantation manner is adopted, the implantation is led to pass through the control gate and enter the charge coupling region, even enter the channel region between the source end and the drain end, so that the utility model can implant before removing the photoresist for etching the control gate, and the photoresist is used for preventing the doping from being implanted into the control gate region, as shown in the schematic diagram of the diluted doping process of fig. 9.

It should be noted that when one or both of the dilution doping schemes in the present embodiment are combined with one or both of the dilution doping schemes in the first embodiment in any combination, the doping will have a better wrapping effect on one end of the near-gate region of the source-drain junction, so as to achieve a larger avalanche voltage.

Third embodiment

A photoelectric calculation unit according to a third embodiment of the present utility model is described with reference to fig. 10.

As shown in the schematic structural diagram of the special doping distribution photoelectric calculation unit shown in fig. 10, in the embodiment of the utility model, the surface doping concentration of the substrate collecting area is higher; the doping from the middle to the bottom of the substrate collection region may exhibit a graded structure that is monotonically graded from low to high.

The area above the dotted line in fig. 10 is a depletion region, in which the potential difference in the substrate collection region is mostly, and the depletion region is also the main area for accelerating photo-generated electrons, and it is obvious that the larger the thickness of this area, the more photo-generated electrons generated inside the depletion region can be accelerated, however, the larger the thickness will increase the scattering probability of photoelectrons during acceleration, and this process is expressed by the following formula:

Wherein W is the depletion region width; n (W) is the number of electrons which can be accelerated into hot carriers in the depletion region when the width of the depletion region is W; v is the potential difference applied to the substrate collection area; d (x) is the concentration of photogenerated electrons at depth x; a (W) is the area of the acceleration region, i.e., the depletion region area; p (x) is the probability that electrons at depth x will not be scattered during acceleration, and it is known that the number of electrons that can be directly accelerated in the depletion region until hot carrier injection occurs is related to the depletion region width W and has an extremum, so we can modulate the depletion region width by controlling the carrier concentration in the depletion region and reach the extremum of the programming efficiency.

Considering the photo-generated carriers outside the depletion region, i.e. from the middle to the bottom of the substrate collection region, if the doping in the middle of the substrate collection region is larger than the bottom, electrons will diffuse from the bottom to the middle when not illuminated, drift from the middle to the bottom to establish a steady state, after illumination, a large amount of photo-generated electrons are generated in the substrate collection region, so that the diffusion current between the middle and the bottom becomes smaller, the drift force is larger than the diffusion force, electrons will drift from the middle of the substrate collection region to the bottom, which is opposite to the expected electron movement direction, so the doping concentration in the middle of the substrate collection region is set smaller than the bottom and monotonically graded, so that after illumination, photo-generated electrons will drift from the bottom to the middle and enter the depletion region to accelerate by the depletion region, achieving higher light input efficiency.

In combination with the above factors, the doping in the final substrate collection area is determined as: the doping concentration from the surface to the bottom is a high-low-high profile. The concentration distribution can be realized by at least two different doping processes, the first process is used for enabling the region in the depletion region to be heavily doped, the implantation energy can be 20-60 keV, and the concentration can be 5e 12-1 e14; the second channel is used to make the bottom of the substrate collection region outside the depletion region heavily doped, and its implantation energy is determined by the thickness of the substrate, and is typically above 300keV, and the concentration can be 2e 13-1 e14.

Fourth embodiment

A photoelectric calculation unit according to a fourth embodiment of the present utility model is described with reference to fig. 11.

As shown in the optical input schematic diagram of the photoelectric calculation units with high photoelectric conversion efficiency in fig. 11, when a certain photoelectric calculation unit is optically input by column and row addressing in the array formed by the photoelectric calculation units, the source ends and the drain ends of the photoelectric calculation units with different columns can be floated. The principle of implementing high photoelectric conversion efficiency in this embodiment is that, since the source end and the drain end of the photoelectric computing unit in a different column from the selected photoelectric computing unit float, the photo-generated electrons in the photoelectric computing unit cannot flow away from the source end and the drain end and flow to the selected photoelectric computing unit, and are accelerated into hot carriers to be injected into the charge coupling region of the selected photoelectric computing unit, which is equivalent to increasing the collecting region of the carriers of the selected photoelectric computing unit. When an active voltage is applied to the photoelectric computing units in different columns, even if the potentials of the source end and the drain end of the photoelectric computing unit are the same as those of the substrate collecting area, the photo-generated electrons of the photoelectric computing unit can still be pumped away, so that the purpose of improving the photoelectric conversion efficiency is not achieved.

As described above, the above-described specific embodiments of the present utility model are merely examples, and those skilled in the art may combine and combine some steps and means from the above-described embodiments separately to achieve the effects of the present utility model according to the concept of the present utility model, and such combined and combined embodiments are also included in the present utility model, and such combination and combination are not described herein.

Note that advantages, effects, and the like mentioned in the present utility model are merely examples and are not to be construed as necessarily essential to the various embodiments of the utility model. Furthermore, the specific details of the utility model described above are for purposes of illustration and understanding only, and are not intended to be limiting, as the utility model may be practiced with the specific details described above.

The block diagrams of the devices, apparatuses, devices, systems referred to in the present utility model are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

In addition, the steps and means in the various embodiments herein are not limited to practice in a certain embodiment, and indeed, some of the steps and some of the means associated with the various embodiments herein may be combined according to the concepts of the present utility model to contemplate new embodiments, which are also included within the scope of the present utility model.

The previous description of the inventive aspects is provided to enable any person skilled in the art to make or use the present utility model. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the utility model. Thus, the present utility model is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features herein.

Claims (6)

1. An optoelectronic computing unit comprising a gate region comprising a bottom dielectric layer, a charge coupled layer, a top dielectric layer and a control gate formed in sequence on a substrate collection region, and a source terminal and a drain terminal formed on the same substrate collection region and located on opposite sides of the gate region, wherein the source terminal and the drain terminal are respectively separated from the gate region by a predetermined threshold distance in a horizontal direction, such that horizontal diffusion of the source terminal and the drain terminal caused by an annealing process does not cause vertical overlapping of the source terminal and the drain terminal with the gate region.

2. The optoelectronic computing unit of claim 1, wherein,

The source and drain are horizontally separated from the gate region by a factor of one tenth of the gate length or 20nm, respectively.

3. The photovoltaic cell of claim 1, wherein the insulating sidewall thickness for source and drain implants on both sides of the gate region is at least a minimum of one fifth of the device gate length and 0.1um, the sidewall being used for a source and drain implant process of the photovoltaic cell and such that horizontal diffusion of source and drain generated by an annealing process does not vertically overlap the source and drain with the gate region.

4. The optoelectronic computing unit of claim 1, wherein the optoelectronic computing unit uses a reticle and photoresist to define locations of ion implants of the source and drain terminals during fabrication, wherein a width of the photoresist overlying the source and/or drain terminals is at least a minimum of one fifth of a device gate length and 0.1um such that horizontal diffusion of the source and drain terminals through an annealing process does not vertically overlap the source and drain terminal regions with the gate region.

5. A photoelectric computing assembly comprising a plurality of the photoelectric computing units according to any one of claims 1 to 4, the plurality of the photoelectric computing units being disposed on at least one plane, the operation of the plurality of the photoelectric computing units being controlled by wiring.

6. The optoelectronic computing assembly of claim 5, wherein the source and drain ends of the optoelectronic units of different columns float when an optical input is made to one optoelectronic computing unit at a row-column site in an array of a plurality of said optoelectronic computing units.