CN107134416A - Shadow effect analytical structure and preparation method thereof and analysis method - Google Patents
Shadow effect analytical structure and preparation method thereof and analysis method Download PDFInfo
- Publication number
- CN107134416A CN107134416A CN201610109509.9A CN201610109509A CN107134416A CN 107134416 A CN107134416 A CN 107134416A CN 201610109509 A CN201610109509 A CN 201610109509A CN 107134416 A CN107134416 A CN 107134416A
- Authority
- CN
- China
- Prior art keywords
- shadow effect
- silicon substrate
- concave panel
- preparation
- analytical structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a kind of shadow effect analytical structure and preparation method thereof and analysis method, wherein, preparation method includes：Processing is just ground sideways in silicon substrate, and concave panel is formed with the positive side in the silicon substrate；At least two grid structures are formed on the concave panel；Photoresist coating is formed on the concave panel for forming the grid structure；Processing is patterned to the photoresist according to default domain, to form the shadow effect analytical structure of any one grid structure.By technical solution of the present invention, the preparation cost of shadow effect analytical structure is reduced, reliability of technology is improved.
Description
Technical field
The present invention relates to technology of semiconductor chips field, analyzed in particular to a kind of shadow effect
The preparation method of structure, a kind of shadow effect analytical structure and a kind of analysis method of shadow effect.
Background technology
In the preparation process of transistor, in order to prevent tunnel-effect, generally using the note of certain angle
Enter mode, if the areas adjacent injected just there are other figure (photoresist or other blocking junctions
Structure), shadow effect is may result in, accordingly, it would be desirable to carry out being analysed to ensure that device can to shadow effect
By property.
As shown in figure 1, the preparation method of the shadowing analysis structure in correlation technique includes：In silicon substrate
Gate oxide 102 and grid structure 103 are formed on 101, convex is obtained by adjusting spin coating rotating speed
The photoresist coating in face, and form after photoetching the photoresist post 104 of different height and imitated as shade
Analytical structure is answered, finally using the ion implantation technology (105 in trajectory such as Fig. 1 of specified angle
It is shown) and annealing process processing, to analyze shadow effect.
But, the technical scheme that the photoresist post of different height is obtained based on photoresist spin coating proceeding can not
It is higher by property, for example, the adhesiveness and mobility of photoresist, ambient humidity and temperature and silicon substrate
Preliminary drying temperature etc., all affects the flatness of photoresist, in addition, be more easy to acquisition in the prior art is
The high photoresist coating of flatness.
Therefore, the preparation side of a kind of low cost and the high shadow effect analytical structure of reliability how is designed
Case, to analyze shadow effect as technical problem urgently to be resolved hurrily.
The content of the invention
The present invention is based at least one above-mentioned technical problem, it is proposed that a kind of new shadow effect point
The preparation scheme of structure is analysed, by being just ground sideways to form concave panel in silicon substrate, and
Photoresist coating is formed on concave panel, and then by the photoresist of graphical photoetching acquisition different height,
So as to obtain the shadow effect analytical structure of low cost, reliability of technology is high, is compatible with standard
CMOS technology.
In view of this, a kind of embodiment according to the first aspect of the invention, it is proposed that shadow effect point
The preparation method of structure is analysed, including：Processing is just ground sideways in silicon substrate, with the silicon
The positive side of substrate forms concave panel；At least two grid structures are formed on the concave panel；In shape
Photoresist coating is formed on into the concave panel of the grid structure；According to default domain to the photoresist
Processing is patterned, to form the shadow effect analytical structure of any one grid structure.
In the technical scheme, by being just ground sideways to form concave panel in silicon substrate, and
Photoresist coating is formed on concave panel, and then passes through the photoetching of graphical photoetching acquisition different height
Glue, so as to obtain the shadow effect analytical structure of low cost, reliability of technology is high, is compatible with standard
CMOS technology.
Specifically, the grinding technics for silicon substrate is usually to combine wet grinding and dry grinding,
I.e. while spraying chemical reagent to silicon substrate, while being carried out using special grinding abrasive disk to silicon substrate rotary
Physical grinding, due to the centrifugal action of rotation, chemical reagent needs to be sprayed in silicon substrate
The heart, is faster than fringe region which results in the grinding rate of central area, so as to generate concave panel
Effect.
In addition, after grinding forms concave panel, it is necessary to silicon substrate process routinely clean, and cleaning
After carry out photoetching, based on photoetching process obtain photoresist upper surface it is smooth, the lower surface of photoresist
Adhere on concave panel, therefore, form the photoresist post of multiple different heights as shadow effect point
Analyse structure.
And the thickness of photoresist can be measured by film thickness gauge, controllability is high, and process costs
It is low.
In the above-mentioned technical solutions, it is preferable that at least two grid knots are formed on the concave panel
Structure, specifically includes following steps：It is 900~1000 DEG C of thermal oxidation technology described using temperature range
Gate oxide is formed on concave panel；Using temperature range as 500~700 DEG C of chemical vapor deposition method shape
Into polysilicon layer；Processing is patterned to the polysilicon layer and the gate oxide, to be formed
State grid structure.
In any of the above-described technical scheme, it is preferable that on the concave panel of the grid structure is formed
Photoresist coating is formed, following steps are specifically included：The shower nozzle of glue spreader is controlled to be directed at the concave panel
Normal axis；The shower nozzle is controlled to spray photoresist to the concave panel；Control to be used to fix the silicon
The base of substrate is rotated with specified rotating speed.
In any of the above-described technical scheme, it is preferable that the speed range of the specified rotating speed is
0~6000RPM.
A kind of embodiment according to the second aspect of the invention, it is proposed that shadow effect analytical structure, is adopted
It is prepared from the preparation method of the shadow effect analytical structure described in any one technical scheme as described above.
In any of the above-described technical scheme, it is preferable that the shadow effect analytical structure adheres to silicon
On the concave panel of substrate, meanwhile, the height of shadow effect analytical structure is differed described at least two.
In the technical scheme, by being just ground sideways to form concave panel in silicon substrate, and
Photoresist coating is formed on concave panel, and then passes through the photoetching of graphical photoetching acquisition different height
Glue, so as to obtain the shadow effect analytical structure of low cost, reliability of technology is high, is compatible with standard
CMOS technology.
A kind of embodiment according to the third aspect of the invention we, it is proposed that analysis method of shadow effect,
The analysis method of the shadow effect includes：At least two Si-gate knots are formed on silicon substrate to be analyzed
After the shadow effect analytical structure of structure and any one grid structure, to specify implant angle to described
The injection reserved area of silicon substrate carries out ion implanting；After the ion implanting is completed, to the silicon
Substrate is made annealing treatment, and the temperature range of the annealing is 800~1200 DEG C, the annealing
The time range of processing is 0~5min, wherein, the specified implant angle is the grid structure
Angle between the trajectory of plumb line and the ion implanting, during using the plumb line as starting point, institute
State trajectory and be present in the offside of the plumb line with the side wall.
In any of the above-described technical scheme, it is preferable that the scope of the specified implant angle is
3~30 °.
In any of the above-described technical scheme, it is preferable that the scope of the specified implant angle is 7 °.
In the technical scheme, by determining to specify the scope of implant angle (to avoid tunnel-effect for 7 °
Most rationality implant angle), can be while tunnel-effect be at utmost avoided, to above-mentioned injection
The shadow effect that technique is caused is analyzed exactly.
In any of the above-described technical scheme, it is preferable that also include：Complete the annealing
Afterwards, the threshold voltage and leakage current of the reserved area are detected；It is determined that the threshold voltage belongs to pre-
If threshold voltage ranges, and the leakage current is when belonging to default leakage current scope, determines the shade effect
Should be in tolerable scope.
By above technical scheme, by being just ground sideways to form concave panel in silicon substrate,
And photoresist coating is formed on concave panel, and then pass through the photoetching of graphical photoetching acquisition different height
Glue, so as to obtain the shadow effect analytical structure of low cost, reliability of technology is high, is compatible with standard
CMOS technology.
Brief description of the drawings
Fig. 1 shows the cross-sectional view of shadow effect analytical structure in correlation technique；
Fig. 2 shows showing for the preparation method of shadow effect analytical structure according to an embodiment of the invention
Meaning flow chart；
Fig. 3 to Fig. 7 shows the preparation of shadow effect analytical structure according to an embodiment of the invention
The diagrammatic cross-section of journey；
Fig. 8 shows the exemplary flow of the analysis method of shadow effect according to an embodiment of the invention
Figure.
Embodiment
In order to be more clearly understood that the above objects, features and advantages of the present invention, with reference to attached
The present invention is further described in detail for figure and embodiment.It should be noted that not
In the case of conflict, the feature in embodiments herein and embodiment can be mutually combined.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still,
The present invention can also be different from third party's mode described here to implement using third party, therefore, this
The protection domain of invention is not limited by following public specific embodiment.
With reference to systems of the Fig. 2 to Fig. 8 to shadow effect analytical structure according to an embodiment of the invention
Preparation Method is specifically described.
As shown in Figures 2 to 7, the preparation of shadow effect analytical structure according to an embodiment of the invention
Method, including：Step 202, processing is just ground sideways in silicon substrate 301, with described
The positive side of silicon substrate 301 forms concave panel；At least two grid structures are formed on the concave panel
303；Step 204, photoresist coating is formed on the concave panel for forming the grid structure 303；
Step 206, processing is patterned to the photoresist according to default domain, to form any one institute
State the shadow effect analytical structure 304 of grid structure 303.
In the technical scheme, pass through being just ground sideways to form spill in silicon substrate 301
Face, and form on concave panel photoresist coating, and then pass through graphical photoetching and obtain different height
Photoresist, so as to obtain the shadow effect analytical structure 304 of low cost, reliability of technology is high, simultaneous
It is dissolved in standard CMOS process.
Specifically, the grinding technics for silicon substrate 301 is usually to be ground with reference to wet grinding and dry method
Mill, namely while chemical reagent is sprayed to silicon substrate 301, while using special grinding abrasive disk to silicon substrate
301 carry out revolving physical grinding, due to the centrifugal action of rotation, and chemical reagent needs spraying
In the center of silicon substrate 301, it is faster than fringe region which results in the grinding rate of central area, from
And generate the effect of concave panel.
In addition, after grinding forms concave panel, it is necessary to the process of silicon substrate 301 routinely clean, and
Photoetching is carried out after cleaning, the upper surface of the photoresist obtained based on photoetching process is smooth, under photoresist
Surface adhesion is on concave panel, and therefore, the photoresist post for foring multiple different heights is imitated as shade
Answer analytical structure 304.
And the thickness of photoresist can be measured by film thickness gauge, controllability is high, and process costs
It is low.
In the above-mentioned technical solutions, it is preferable that at least two grid structures are formed on the concave panel
303, specifically include following steps：It is 900~1000 DEG C of thermal oxidation technology described using temperature range
Gate oxide 302 is formed on concave panel；Using temperature range as 500~700 DEG C of chemical vapor deposition work
Skill formation polysilicon layer；Processing is patterned to the polysilicon layer and the gate oxide 302,
To form the grid structure 303.
In any of the above-described technical scheme, it is preferable that forming the spill of the grid structure 303
Photoresist coating is formed on face, following steps are specifically included：Control the shower nozzle alignment of glue spreader described recessed
The normal axis in shape face；The shower nozzle is controlled to spray photoresist to the concave panel；Control to be used to fix institute
The base of silicon substrate 301 is stated to specify rotating speed to rotate.
In any of the above-described technical scheme, it is preferable that the speed range of the specified rotating speed is
0~6000RPM.
As shown in Figures 2 to 7, the shadow effect analysis of embodiment according to the second aspect of the invention
Structure, using the preparation method system of the shadow effect analytical structure described in any one technical scheme as described above
It is standby to form.
In any of the above-described technical scheme, it is preferable that the shadow effect analytical structure 304 is adhered to
In on the concave panel of silicon substrate 301, meanwhile, shadow effect analytical structure 304 described at least two
Highly differ.
In the technical scheme, pass through being just ground sideways to form spill in silicon substrate 301
Face, and form on concave panel photoresist coating, and then pass through graphical photoetching and obtain different height
Photoresist, so as to obtain the shadow effect analytical structure 304 of low cost, reliability of technology is high, simultaneous
It is dissolved in standard CMOS process.
As shown in Fig. 2 to Fig. 8, the analysis method of shadow effect, is wrapped according to an embodiment of the invention
Include：Step 802, at least two silicon gate structures and any one are formed on silicon substrate 301 to be analyzed
After the shadow effect analytical structure 304 of the grid structure 303, to specify implant angle α to described
The injection reserved area of silicon substrate 301 carries out ion implanting；Step 804, the ion note is completed
After entering, the silicon substrate 301 is made annealing treatment, the temperature range of the annealing is
800~1200 DEG C, the time range of the annealing is 0~5min, wherein, the specified injection
Angle [alpha] is between the plumb line of the grid structure 303 and the trajectory 305 of the ion implanting
Angle [alpha], during with the plumb line 305 for starting point, the trajectory 305 is present in the side wall
The offside of the plumb line.
In the technical scheme, pass through being just ground sideways to form spill in silicon substrate 301
Face, and form on concave panel photoresist coating, and then pass through graphical photoetching and obtain different height
Photoresist, so as to obtain the shadow effect analytical structure 304 of low cost, reliability of technology is high, simultaneous
It is dissolved in standard CMOS process.
In any of the above-described technical scheme, it is preferable that the scope of the specified implant angle α is
3~30 °.
In any of the above-described technical scheme, it is preferable that the scope of the specified implant angle α is
7°。
In the technical scheme, by determining to specify implant angle α scope (to avoid tunnel from imitating for 7 °
The most rationality implant angle α answered), can be while tunnel-effect be at utmost avoided, to above-mentioned
The shadow effect that injection technology is caused is analyzed exactly.
In any of the above-described technical scheme, it is preferable that also include：Complete the annealing
Afterwards, the threshold voltage and leakage current of the reserved area are detected；It is determined that the threshold voltage belongs to pre-
If threshold voltage ranges, and the leakage current is when belonging to default leakage current scope, determines the shade effect
Should be in tolerable scope.
Technical scheme is described in detail above in association with accompanying drawing, it is contemplated that proposed in correlation technique
How to design a kind of preparation scheme of inexpensive shadow effect analytical structure, to improve shadow effect
Technical problem, the present invention propose a kind of preparation scheme of new shadow effect analytical structure, pass through
In the side side wall formation side wall of grid structure, only by once specifying the ion implanting of implant angle to change
Kind shadow effect, improves the stability and device reliability of technique, while reducing production cost.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for
For those skilled in the art, the present invention can have various modifications and variations.All essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements made etc. should be included in the present invention
Protection domain within.
Claims (10)
1. a kind of preparation method of shadow effect analytical structure, it is characterised in that including：
Processing is just ground sideways in silicon substrate, and spill is formed with the positive side in the silicon substrate
Face；
At least two grid structures are formed on the concave panel；
Photoresist coating is formed on the concave panel for forming the grid structure；
Processing is patterned to the photoresist according to default domain, to form any one described grid
The shadow effect analytical structure of structure.
2. the preparation method of shadow effect analytical structure according to claim 1, its feature exists
In forming at least two grid structures on the concave panel, specifically include following steps：
By 900~1000 DEG C of thermal oxidation technology of temperature range gate oxidation is formed on the concave panel
Layer；
Polysilicon layer is formed by 500~700 DEG C of chemical vapor deposition method of temperature range；
Processing is patterned to the polysilicon layer and the gate oxide, to form the grid knot
Structure.
3. the preparation method of shadow effect analytical structure according to claim 1 or 2, it is special
Levy and be, form photoresist coating on the concave panel for forming the grid structure, specifically include following
Step：
The shower nozzle of glue spreader is controlled to be directed at the normal axis of the concave panel；
The shower nozzle is controlled to spray photoresist to the concave panel；
Control for fixing the base of the silicon substrate to specify rotating speed to rotate.
4. the preparation method of shadow effect analytical structure according to claim 3, its feature exists
In the speed range of the specified rotating speed is 0~6000RPM.
5. a kind of shadow effect analytical structure, it is characterised in that using as in Claims 1-4
The preparation method of shadow effect analytical structure described in any one is prepared from.
6. shadow effect analytical structure according to claim 5, it is characterised in that described the moon
Shadow effect analysis structure is adhered on the concave panel of silicon substrate, meanwhile, shadow effect described at least two
The height of analytical structure is differed.
7. a kind of analysis method of shadow effect, it is adaptable to the shade as described in claim 5 or 6
Effect analysis structure, it is characterised in that the analysis method of the shadow effect includes：
At least two silicon gate structures and any one grid structure are formed on silicon substrate to be analyzed
After shadow effect analytical structure, to specify implant angle to carry out the injection reserved area of the silicon substrate
Ion implanting；
After the ion implanting is completed, the silicon substrate is made annealing treatment, the annealing
Temperature range be 800~1200 DEG C, the time range of the annealing is 0~5min,
Wherein, the specified implant angle is the plumb line and the ion implanting of the grid structure
Angle between trajectory, during using the plumb line as starting point, the trajectory exists with the side wall
In the offside of the plumb line.
8. the analysis method of shadow effect according to claim 7, it is characterised in that described
The scope for specifying implant angle is 3~30 °.
9. the analysis method of shadow effect according to claim 8, it is characterised in that described
The scope for specifying implant angle is 7 °.
10. the analysis method of the shadow effect according to any one of claim 7 to 9, it is special
Levy and be, in addition to：
After the annealing is completed, the threshold voltage and leakage current of the reserved area are detected；
It is determined that the threshold voltage belongs to predetermined threshold value voltage scope, and the leakage current belongs to default
During leakage current scope, determine the shadow effect in tolerable scope.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610109509.9A CN107134416A (en) | 2016-02-26 | 2016-02-26 | Shadow effect analytical structure and preparation method thereof and analysis method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610109509.9A CN107134416A (en) | 2016-02-26 | 2016-02-26 | Shadow effect analytical structure and preparation method thereof and analysis method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107134416A true CN107134416A (en) | 2017-09-05 |
Family
ID=59720661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610109509.9A Pending CN107134416A (en) | 2016-02-26 | 2016-02-26 | Shadow effect analytical structure and preparation method thereof and analysis method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107134416A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928159A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Trimming method of MOSFET device layout |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6733936B1 (en) * | 2002-09-19 | 2004-05-11 | Integrated Device Technology, Inc. | Method for generating a swing curve and photoresist feature formed using swing curve |
| CN102468274A (en) * | 2010-11-15 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Shadow effect analyzing structure, and forming method and analyzing method thereof |
| CN104009021A (en) * | 2014-06-12 | 2014-08-27 | 上海华力微电子有限公司 | Silicon wafer for photoresist thickness swing curve test and manufacturing method |
-
2016
- 2016-02-26 CN CN201610109509.9A patent/CN107134416A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6733936B1 (en) * | 2002-09-19 | 2004-05-11 | Integrated Device Technology, Inc. | Method for generating a swing curve and photoresist feature formed using swing curve |
| CN102468274A (en) * | 2010-11-15 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Shadow effect analyzing structure, and forming method and analyzing method thereof |
| CN104009021A (en) * | 2014-06-12 | 2014-08-27 | 上海华力微电子有限公司 | Silicon wafer for photoresist thickness swing curve test and manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928159A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Trimming method of MOSFET device layout |
| CN112928159B (en) * | 2021-01-22 | 2023-11-24 | 上海华虹宏力半导体制造有限公司 | Method for trimming MOSFET device layout |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9170496B2 (en) | Method of pre-treating a wafer surface before applying a solvent-containing material thereon | |
| CN108666375A (en) | A kind of nano lamellar transverse direction homogeneity PN diodes and the preparation method and application thereof | |
| US9633834B2 (en) | Photolithographic method for forming a coating layer | |
| US5874128A (en) | Method and apparatus for uniformly spin-coating a photoresist material | |
| CN103346108A (en) | Device and method for improving smoothness of wafer edge | |
| CN105122440B (en) | The method and apparatus that the through silicon via back side is appeared | |
| CN107134416A (en) | Shadow effect analytical structure and preparation method thereof and analysis method | |
| US6281068B1 (en) | Method for buried plate formation in deep trench capacitors | |
| CN101740385A (en) | Method for forming channel in LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor | |
| CN103715131A (en) | High depth width ratio TSV through hole step-by-step etching and side wall modification method | |
| CN102496632B (en) | Ultra-thin silicon PIN high energy particle detector based on bonding substrate and manufacturing method thereof | |
| CN103681266B (en) | The ion injection method of active area | |
| CN113171936A (en) | Glue spreading method in photoetching process | |
| CN103295880B (en) | The modified node method and preparation method thereof of control wafer and using method in a kind of polycrystalline silicon furnace tube technique | |
| CN103441086A (en) | Method for detecting light resistance layer ion implantation stopping capacity | |
| CN103606518A (en) | A wet etching method and a wet etching apparatus | |
| CN102706785A (en) | Method for testing blocking ability of photoresist layer for ion implantation | |
| CN104600027B (en) | A kind of preparation technology of TSV through hole | |
| TW200627518A (en) | Method of coating photoresist and photoresist layer formed by the same | |
| KR20080046248A (en) | A method of and an apparatus for processing a substrate | |
| CN102522424A (en) | CMOS device capable of reducing charge sharing effect and manufacturing method thereof | |
| KR100731104B1 (en) | Well photoresist pattern of semiconductor device and method for forming the same | |
| CN101995765A (en) | Photoetching method | |
| CN106373889A (en) | Method for improving NMOS hot carrier effect | |
| JPS6387741A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170905 |
|
| RJ01 | Rejection of invention patent application after publication |