CN103715131A - High depth width ratio TSV through hole step-by-step etching and side wall modification method - Google Patents

High depth width ratio TSV through hole step-by-step etching and side wall modification method Download PDF

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CN103715131A
CN103715131A CN201210371478.6A CN201210371478A CN103715131A CN 103715131 A CN103715131 A CN 103715131A CN 201210371478 A CN201210371478 A CN 201210371478A CN 103715131 A CN103715131 A CN 103715131A
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etching
initial value
hole
performance number
bias
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CN103715131B (en
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单光宝
刘松
孙有民
蔚婷婷
李翔
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771 Research Institute of the Ninth Research Institute of China Aerospace Science and Technology Corporation Co.,Ltd.
Zhuhai Tiancheng Advanced Semiconductor Technology Co ltd
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771 Research Institute of 9th Academy of CASC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

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Abstract

The invention discloses a high depth width ratio TSV through hole step-by-step etching and side wall modification method. The method comprises the steps that a layer of SiO2 is deposited on the surface of a P (100) type single crystal silicon wafer by using a PE CVD method; photoresist is coated on the surface of the SiO2; exposing and developing are carried out; a silicon dioxide window needing etching is exposed; a plasma dry etching method is used to carry out the etching of a silicon dioxide layer on the exposed window, and etching is carried out until the surface of the single crystal silicon wafer; and an optimized multiple-step Bosch etching process is carried out. According to the invention, K+ pollution is not introduced; high temperature process processing is avoided; the size of a through hole occupies a small chip area; the economic benefit is high; the method is compatible with an IC technology; the through hole of high density and high depth width ratio can be produced; the 'scallop' size of a side wall of the through hole can be reduced; the roughness of the side wall is improved; the difficulty of a subsequent side wall insulation process is reduced; the breakdown voltage can be enhanced; and the reliability of a TSV three-dimensional integrated device is improved.

Description

Large depth-to-width ratio TSV through hole step etching and sidewall method of modifying
Technical field
The present invention relates to microelectronics technology.
Background technology
At present conventional TSV through hole manufacturing technology mainly adopts ICP lithographic technique Bosch technique to realize the making of large depth-to-width ratio TSV through hole.In " U.S.PatentNo.5501893 " patent, write: Bosch technique is to utilize the method that passivation, etching hocket to carry out deep hole etching.First with C4F8 deposition one layer of polymeric for sidewall protection, then with SF6 again by polymer and silicon eating away in the same time.Passivation, etch step high speed alternate cycles, finally reach anisotropic etching effect.But the shortcoming of the method is: the SF6 that traditional Bosch technique is used has isotropic etching characteristic, thus meeting lateral etching sidewall in etching process, thus form small cambered structure.Through follow-up several passivation, etch step circulation, finally can form " scallop type " sidewall.In addition, owing to adopting static process parameter, control Bosch technique, so can cause TSV through hole top " scallop " structure larger, middle part dwindles gradually, bottom minimal characteristic, has a strong impact on sidewall integral smoothness (referring to Fig. 1), and this will make follow-up through-hole side wall insulation, barrier/seed layers, via metal metallization processes produces and has a strong impact on, and cause electric leakage increase, withstand voltage reduction, affect three-dimensional integrated device Performance And Reliability.In order to address this problem, to have and continued literature research mutually based on KOH wet etching formation TSV through hole and thermal oxidation method modification sidewall minimizing TSV through-hole side wall " scallop " structure technology.
KOH wet etching technology is introduced in " exploitation of interconnecting silicon through holes technology and application (the < < Chinese Integrated Circuit > > third phase in 2007) ": KOH wet etching is to utilize (111) crystal face automatic stop technology to form TSV through hole.But there are two subject matters in the method: the one, and due to the existence of (111) crystal face and the intrinsic angle of (100) crystal face, TSV via openings can become large and increase along with corrosion depth, makes such TSV through hole area occupied excessive, economical poor; The 2nd, this technique is used KOH easily to introduce K+ pollution as attached liquid, can cause K+ to pollute to CMOS processing line.
In " a kind of TSV method for forming via and through hole modification method (NO.201010250521) " patent, propose to eliminate with growth thermooxidative layer the method for sidewall " scallop " structure.Its principle is: first under high temperature (>1000 ℃) environment, to having the TSV through hole of " scallop " structure, carry out long period heat treatment, guarantee that oxygen and sidewall " scallop " structure fully reacts, make " scallop " structure SiO2 of being oxidized to as much as possible, and then remove SiO2 with HF acid rinse, and then reduce " scallop structure ".But the method shortcoming is: the one, need the high-temperature technology of long period, and cannot be for completing the Via-last TSV technique after metallization process; The 2nd, for SOI material, while utilizing " scallop " structure of HF acid corrosion oxidation TSV sidewall oxidation, can erode oxygen buried layer simultaneously, cause TSV through-hole structure between top layer silicon and silicon base, to form empty structure, follow-up insulating barrier, barrier layer, Seed Layer be fracture herein easily, form hidden danger, the device based on SOI material cannot adopt the method; The 3rd, for the TSV through hole of smaller aperture due, due to surface tension of liquid effect, HF acid cannot enter and deeply reach tens of microns of through hole inside, and deoxidation layer step is difficult to realize.
Summary of the invention
For fear of existing through hole manufacturing technology, can not obtain higher density, larger depth-to-width ratio and upper side wall evenness, and affect the deficiency of lateral wall insulation characteristic and device performance, patent of the present invention proposes the multistep Bosch etching process of optimizing, and carries out large depth-to-width ratio TSV via etch and sidewall and modifies.Compare with high temperature thermal oxidation method with KOH wet etching method, the inventive method is not introduced K+ and is polluted, and without high-temperature technology, processes, and has that clear size of opening chip occupying area is little, economic benefit is high, with IC process compatible, be applicable to the feature of the three-dimensional integrated application of SOI material devices and all TSV technological processes.Can not only produce high density, large depth-to-width ratio through hole, reduce through-hole side wall " scallop " size, improve sidewall evenness, reduce follow-up lateral wall insulation technology difficulty, can also promote puncture voltage, increase the three-dimensional integrated device reliability of TSV.
The technical solution adopted for the present invention to solve the technical problems comprises the following steps:
1) on P<100> type monocrystalline silicon wafer crystal surface, use PE CVD method deposit one deck 1 μ m ~ 1.5 μ m SiO 2, and at SiO 2surface resist coating, exposure imaging, exposes and needs the silicon dioxide of etching window, and described graph window is circular hole, bore dia 5 μ m ~ 30 μ m.
2) by dry plasma etch method, at the window place of exposing, carry out the etching of silicon dioxide layer, be etched to monocrystalline silicon wafer crystal surface always.
3) the multistep Bosch etching technics being optimized, etching gas is used SF 6, passivation gas is used C 4f 8, etching machine bench Bias, Source performance number, gas flow value, etching/passivation time than all changing on the basis at initial value when following each step changes, and described initial value is the set point of single step Bosch etching technics parameter, and concrete technology step is as follows:
During step 1. etching through hole top, C 4f 8flow increases 1/6 ~ 1/3 of initial value, SF 6flow reduces 1/6 ~ 1/3 of initial value; On the basis of initial value, increase passivation time 1s ~ 2s, reduce etch period 1s ~ 2s, Bias is initial value, Source performance number reduces 1/6 ~ 1/5 of initial value; This step activity duration is 10min ~ 15min;
During step 2. etching through hole middle part, gas flow value, etching/passivation time ratio, Source performance number change initial value into, and Bias performance number increases 1/5 ~ 1/4 of initial value; This step activity duration 20min ~ 30min;
During step 3. etching through hole bottom, on the basis of initial value, increase 1/6 ~ 1/3SF 6flow, reduces by 1/6 ~ 1/3C 4f 8flow, increases 1s ~ 2s between etching, reduces passivation time 1s ~ 2s; Bias performance number increases 1/4 ~ 1/2 of initial value, and Source performance number increases 1/6 ~ 1/5 of initial value; This step activity duration 10min ~ 15min;
The step 4. via etch degree of depth reaches after requirement, stops passivation gas C 4f 8protection, passes into isotropic etching gas SF 6, SF 6gas flow 100sccm ~ 150sccm, Bias, Source performance number are initial value; This step activity duration 30s ~ 1min.
The invention has the beneficial effects as follows: because traditional B osch technique can cause via top " scallop " large, middle part dwindles gradually, bottom minimal characteristic, so the Bosch etching technics that the multistep that the present invention proposes is optimized adopts Dynamic parameters control, increase along with etching depth, technological parameter also can change accordingly, guaranteeing to process high density, in the time of the TSV through hole of the about 10:1 of depth-to-width ratio, by TSV through-hole side wall " scallop " structure decrease to being less than 70nm, thereby reduce the difficulty of follow-up lateral wall insulation technique, solve the electric leakage of TSV via top large, withstand voltage low problem, promote TSV through hole integral body withstand voltage (>70V) characteristic, reduce electric leakage, promote three-dimensional integrated device performance.
Compare with KOH wet etching method, this invention can not introduced K+ and pollute, owing to not having (111) crystal face and the intrinsic angle of (100) crystal face in anisotropic etch, so via openings can be along with etching depth increases and becomes large, than KOH wet etching saving chip area more, have more economic benefit.
Compare with high temperature thermal oxidation method, this invention is processed without high-temperature technology, avoided the follow-up HF deoxidation of high temperature thermal oxidation method layer to be difficult to realize and can cause to SOI material structure the shortcoming of technique hidden danger, have and traditional IC process compatible, be applicable to the feature of the three-dimensional integrated application of SOI material devices and all TSV technological processes.
Accompanying drawing explanation
Fig. 1 is traditional B osch etching technics schematic diagram, wherein, (a) is traditional B osch etching technics etching through hole schematical top view, but (b) is traditional B osch technique etching through hole middle part and bottom schematic view.
Fig. 2 is the multistep Bosch etch process flow schematic diagram of optimizing,
Wherein, 1-Si substrate, 2-SiO 2mask,
(a) be step 1 via top etching schematic diagram; Increase C 4f 8flow, reduces SF 6flow or increase passivation time, reduce the passivation protection that etch period strengthens via top;
(b) be step 2 through hole middle part etching schematic diagram; On the basis of step 1, suitably increase SF 6flow, reduces C 4f 8flow or by increasing between etching, reduces passivation time;
(c) be step 3 via bottoms etching schematic diagram; On the basis of step 2, further strengthen longitudinal etching effect;
(d) be step 4 via etch reprocessing schematic diagram, carry out suitable isotropic etching and process.
Fig. 3 is the FB(flow block) of etching technics of the present invention,
Wherein, step before 3-TSV via etch, 4-TSV via etch step.
embodiment
Below in conjunction with drawings and Examples, the present invention is further described.
For fear of existing through hole manufacturing technology, can not obtain higher density, larger depth-to-width ratio and upper side wall evenness, and affect the deficiency of lateral wall insulation characteristic and device performance.For the large depth-to-width ratio TSV via etch of tradition, adopt static process parameter to control Bosch technique, cause TSV through hole top " scallop " structure large, middle part dwindles gradually, the feature (referring to Fig. 1) that bottom is minimum, patent of the present invention proposes the multistep Bosch etching process of optimizing, and carries out large depth-to-width ratio TSV via etch and sidewall and modifies.
Technical scheme
1. first on P<100> type monocrystalline silicon wafer crystal surface, use PE CVD method deposit one deck 1 μ m ~ 1.5 μ m SiO 2, and at SiO 2surface resist coating, exposure imaging, exposes and needs the silicon dioxide of etching window (graph window is circular hole, bore dia 5 μ m ~ 30 μ m).
2. then by dry plasma etch method, at the window place of exposing, carry out the etching of silicon dioxide layer, be etched to monocrystalline silicon wafer crystal surface always.
3. then carry out the multistep Bosch etching technics of the optimization of proposition of the present invention, etching gas is used SF 6, passivation gas is used C 4f 8, etching machine bench Bias(bias voltage), Source(source power) performance number, gas flow value, etching/passivation time is than all change (initial value is the set point of single step Bosch etching technics parameter) on the basis at initial value when following each step changes.
The multistep Bosch etching technics of optimizing, is characterized in that processing step is as follows:
During step 1. etching through hole top, C 4f 8flow increases 1/6 ~ 1/3 of initial value, SF 6flow reduces 1/6 ~ 1/3 of initial value.On the basis of initial value, increase passivation time 1s ~ 2s, reduce etch period 1s ~ 2s, Bias is initial value, Source performance number reduces 1/6 ~ 1/5 of initial value.This step activity duration is that 10min～15min(is referring to Fig. 2 (a)).
During step 2. etching through hole middle part, gas flow value, etching/passivation time ratio, Source performance number changes initial value into, and Bias performance number increases 1/5 ~ 1/4 of initial value.This step activity duration, 20min ~ 30min(was referring to Fig. 2 (b)).
During step 3. etching through hole bottom, on the basis of step 2, need further to strengthen longitudinal etching effect, so increase 1/6 ~ 1/3SF on the basis of initial value 6flow, reduces by 1/6 ~ 1/3C 4f 8flow, increases 1s ~ 2s between etching, reduces passivation time 1s ~ 2s.Bias performance number can increase 1/4 ~ 1/2 of initial value, and Source performance number can increase 1/6 ~ 1/5 of initial value.This step activity duration, 10min ~ 15min(was referring to Fig. 2 (c)).
The step 4. via etch degree of depth reaches after requirement, stops passivation gas C 4f 8protection, passes into isotropic etching gas SF 6, SF 6gas flow 100sccm ~ 150sccm, Bias, Source performance number are initial value.This step activity duration, 30s ~ 1min(was referring to Fig. 2 (d)).
Whole processing step can be referring to Fig. 3 FB(flow block).
Embodiment 1:
The present embodiment is for diameter 10 μ m, and depth-to-width ratio requires to make for the TSV through hole of 10:1.Hole etching material is P<100> type silicon, and mask is the thick SiO of 1 μ m 2.ICP etching machine bench model is Alcatel AMS-100, specifically walks implement rapid following (referring to Fig. 3) according to the present invention:
1. first on P<100> type monocrystalline silicon wafer crystal surface, use PE CVD method deposit one deck 1 μ m SiO 2, and at SiO 2surface resist coating, exposure imaging, exposes and needs the silicon dioxide of etching window (graph window is circular hole, bore dia 10 μ m).
2. then by dry plasma etch method, at the window place of exposing, carry out the etching of silicon dioxide layer, be etched to monocrystalline silicon wafer crystal surface always.
3. then carry out the multistep Bosch etching technics of the optimization of proposition of the present invention, etching gas is used SF 6, passivation gas is used C 4f 8, etching gas SF 6initial value 300sccm, passivation gas C 4f 8initial value 300sccm, board Bias initial setting power 80W, Source initial setting power 1500w, etching/passivation time is 1s:9s than initial value, the multistep Bosch etching technics step following (referring to Fig. 2) of optimization:
Step 1: referring to Fig. 2 (a), for the larger-size situation in top " scallop " after traditional B osch technique etching, should weaken top etching effect, strengthen passivation protection.Now, Bias power setting is 80w, and Source power setting is 1250w, sets gas flow to be: SF 6250sccm, C 4f 8350sccm.Etching/passivation time ratio: 2s:8s.This step time is set as 13min.
Step 2: referring to Fig. 2 (b), for middle part " scallop " size after traditional B osch technique etching, be less than the situation at top, should be on the basis of step 1 suitable enhanced etching effect, strengthen etching power longitudinally.Now, Bias power setting is 95w, and Source power setting is 1500w, sets gas flow to be: SF 6300sccm, C 4f 8300sccm.Etching/passivation time ratio: 1s:9s.This step time is set as 25min.。
Step 3: referring to Fig. 2 (c), much smaller than the situation at top, in order to reach etching desired depth, should further strengthen longitudinal etching effect for bottom " scallop " size after traditional B osch technique etching on the basis of step 2.Now, Bias power setting is 100w, and Source power setting is 1750w, sets gas flow to be: SF 6350sccm, C 4f 8250sccm.Etching/passivation time ratio: 2s:8s.This step time is set as 13min.
Step 4: referring to Fig. 2 (d), in order further to reduce " scallop " size, pass into suitable isotropism gas and carry out isotropic etching.Now, setting gas flow is: SF 6120sccm, C 4f 80sccm, Bias 80W, Source 1500w.This step time is set 40s.
Embodiment 2:
The present embodiment is for diameter 5 μ m, and depth-to-width ratio requires to make for the TSV through hole of 10:1.Hole etching material is P<100> type silicon, and mask is the thick SiO of 1.5 μ m 2.ICP etching machine bench model is Alcatel AMS-100, specifically walks implement rapid following (referring to Fig. 3) according to the present invention:
1. first on P<100> type monocrystalline silicon wafer crystal surface, use PE CVD method deposit one deck 1.5 μ m SiO 2, and at SiO 2surface resist coating, exposure imaging, exposes and needs the silicon dioxide of etching window (graph window is circular hole, bore dia 5 μ m).
2. then by dry plasma etch method, at the window place of exposing, carry out the etching of silicon dioxide layer, be etched to monocrystalline silicon wafer crystal surface always.
3. then carry out the multistep Bosch etching technics of the optimization of proposition of the present invention, etching gas is used SF 6, passivation gas is used C 4f 8, etching gas SF 6initial value 300sccm, passivation gas C 4f 8initial value 300sccm, board Bias initial setting power 80W, Source initial setting power 1500w, etching/passivation time is 1s:9s than initial value, the multistep Bosch etching technics step following (referring to Fig. 2) of optimization:
Step 1: referring to Fig. 2 (a), for the larger-size situation in top " scallop " after traditional B osch technique etching, should weaken top etching effect, strengthen passivation protection.Now, Bias power setting is 80w, and Source power setting is 1200w, sets gas flow to be: SF 6200sccm, C 4f 8400sccm.Etching/passivation time ratio: 3s:7s.This step time is set as 10min.
Step 2: referring to Fig. 2 (b), for middle part " scallop " size after traditional B osch technique etching, be less than the situation at top, should be on the basis of step 1 suitable enhanced etching effect, strengthen etching power longitudinally.Now, Bias power setting is 100w, and Source power setting is 1500w, sets gas flow to be: SF 6300sccm, C 4f 8300sccm.Etching/passivation time ratio: 1s:9s.This step time is set as 20min.。
Step 3: referring to Fig. 2 (c), much smaller than the situation at top, in order to reach etching desired depth, should further strengthen longitudinal etching effect for bottom " scallop " size after traditional B osch technique etching on the basis of step 2.Now, Bias power setting is 120w, and Source power setting is 1800w, sets gas flow to be: SF 6400sccm, C 4f 8250sccm.Etching/passivation time ratio: 2s:8s.This step time is set as 10min.
Step 4: referring to Fig. 2 (d), in order further to reduce " scallop " size, pass into suitable isotropism gas and carry out isotropic etching.Now, setting gas flow is: SF 6150sccm, C 4f 80sccm, Bias 80W, Source1500w.This step time is set 1min.
Embodiment 3:
The present embodiment is for diameter 30 μ m, and depth-to-width ratio requires to make for the TSV through hole of 10:1.Hole etching material is P<100> type silicon, and mask is the thick SiO of 1.5 μ m 2.ICP etching machine bench model is Alcatel AMS-100, specifically walks enforcement rapid as follows according to the present invention:
1. first on P<100> type monocrystalline silicon wafer crystal surface, use PE CVD method deposit one deck 1.5 μ m SiO 2, and at SiO 2surface resist coating, exposure imaging, exposes and needs the silicon dioxide of etching window (graph window is circular hole, bore dia 30 μ m).
2. then by dry plasma etch method, at the window place of exposing, carry out the etching of silicon dioxide layer, be etched to monocrystalline silicon wafer crystal surface always.
3. then carry out the multistep Bosch etching technics of the optimization of proposition of the present invention, etching gas is used SF 6, passivation gas is used C 4f 8, etching gas SF 6initial value 300sccm, passivation gas C 4f 8initial value 300sccm, board Bias initial setting power 80W, Source initial setting power 1500w, etching/passivation time is 1s:9s than initial value, the multistep Bosch etching technics step following (referring to Fig. 2) of optimization:
Step 1: referring to Fig. 2 (a), for the larger-size situation in top " scallop " after traditional B osch technique etching, should weaken top etching effect, strengthen passivation protection.Now, Bias power setting is 80w, and Source power setting is 1280w, sets gas flow to be: SF 6220sccm, C 4f 8370sccm.Etching/passivation time ratio: 2s:8s.This step time is set as 15min.
Step 2: referring to Fig. 2 (b), for middle part " scallop " size after traditional B osch technique etching, be less than the situation at top, should be on the basis of step 1 suitable enhanced etching effect, strengthen etching power longitudinally.Now, Bias power setting is 95w, and Source power setting is 1500w, sets gas flow to be: SF 6300sccm, C 4f 8300sccm.Etching/passivation time ratio: 1s:9s.This step time is set as 25min.。
Step 3: referring to Fig. 2 (c), much smaller than the situation at top, in order to reach etching desired depth, should further strengthen longitudinal etching effect for bottom " scallop " size after traditional B osch technique etching on the basis of step 2.Now, Bias power setting is 110w, and Source power setting is 1750w, sets gas flow to be: SF 6380sccm, C 4f 8220sccm.Etching/passivation time ratio: 2s:8s.This step time is set as 15min.
Step 4: referring to Fig. 2 (d), in order further to reduce " scallop " size, pass into suitable isotropism gas and carry out isotropic etching.Now, setting gas flow is: SF 6100sccm, C 4f 80sccm, Bias 80W, Source 1500w.This step time is set 20s.

Claims (1)

1. large depth-to-width ratio TSV through hole step etching and a sidewall method of modifying, is characterized in that comprising the steps:
1) on P<100> type monocrystalline silicon wafer crystal surface, use PE CVD method deposit one deck 1 μ m ~ 1.5 μ m SiO 2, and at SiO 2surface resist coating, exposure imaging, exposes and needs the silicon dioxide of etching window, and described graph window is circular hole, bore dia 5 μ m ~ 30 μ m;
2) by dry plasma etch method, at the window place of exposing, carry out the etching of silicon dioxide layer, be etched to monocrystalline silicon wafer crystal surface always;
3) the multistep Bosch etching technics being optimized, etching gas is used SF 6, passivation gas is used C 4f 8, etching machine bench Bias, Source performance number, gas flow value, etching/passivation time than all changing on the basis at initial value when following each step changes, and described initial value is the set point of single step Bosch etching technics parameter, and concrete technology step is as follows:
During step 1. etching through hole top, C 4f 8flow increases 1/6 ~ 1/3 of initial value, SF 6flow reduces 1/6 ~ 1/3 of initial value; On the basis of initial value, increase passivation time 1s ~ 2s, reduce etch period 1s ~ 2s, Bias is initial value, Source performance number reduces 1/6 ~ 1/5 of initial value; This step activity duration is 10min ~ 15min;
During step 2. etching through hole middle part, gas flow value, etching/passivation time ratio, Source performance number change initial value into, and Bias performance number increases 1/5 ~ 1/4 of initial value; This step activity duration 20min ~ 30min;
During step 3. etching through hole bottom, on the basis of initial value, increase 1/6 ~ 1/3SF 6flow, reduces by 1/6 ~ 1/3C 4f 8flow, increases 1s ~ 2s between etching, reduces passivation time 1s ~ 2s; Bias performance number increases 1/4 ~ 1/2 of initial value, and Source performance number increases 1/6 ~ 1/5 of initial value; This step activity duration 10min ~ 15min;
The step 4. via etch degree of depth reaches after requirement, stops passivation gas C 4f 8protection, passes into isotropic etching gas SF 6, SF 6gas flow 100sccm ~ 150sccm, Bias, Source performance number are initial value; This step activity duration 30s ~ 1min.
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CN105575787A (en) * 2014-10-16 2016-05-11 中芯国际集成电路制造(上海)有限公司 Formation method of semiconductor structure
CN106564855A (en) * 2015-10-08 2017-04-19 北京北方微电子基地设备工艺研究中心有限责任公司 Deep silicon etching method
CN107611027A (en) * 2017-08-16 2018-01-19 江苏鲁汶仪器有限公司 A kind of method for improving deep silicon etching sidewall roughness
CN110233102A (en) * 2019-06-18 2019-09-13 北京北方华创微电子装备有限公司 Lithographic method
CN113283053A (en) * 2021-04-17 2021-08-20 山西潞安太阳能科技有限责任公司 Method for establishing pecvd coating process parameters of crystalline silicon battery
CN113345836A (en) * 2021-06-01 2021-09-03 浙江集迈科微电子有限公司 TSV electroplating process
CN115206796A (en) * 2022-09-16 2022-10-18 杭州中欣晶圆半导体股份有限公司 Method for performing fixed-point deep silicon etching on surface of silicon wafer
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Cited By (11)

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CN105575787A (en) * 2014-10-16 2016-05-11 中芯国际集成电路制造(上海)有限公司 Formation method of semiconductor structure
CN105575787B (en) * 2014-10-16 2018-02-16 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN106564855A (en) * 2015-10-08 2017-04-19 北京北方微电子基地设备工艺研究中心有限责任公司 Deep silicon etching method
CN106564855B (en) * 2015-10-08 2019-05-31 北京北方华创微电子装备有限公司 A kind of deep silicon etching method
CN107611027A (en) * 2017-08-16 2018-01-19 江苏鲁汶仪器有限公司 A kind of method for improving deep silicon etching sidewall roughness
CN110233102A (en) * 2019-06-18 2019-09-13 北京北方华创微电子装备有限公司 Lithographic method
US12033852B2 (en) 2019-07-31 2024-07-09 Kokusai Electric Corporation Method of processing substrate, method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
CN113283053A (en) * 2021-04-17 2021-08-20 山西潞安太阳能科技有限责任公司 Method for establishing pecvd coating process parameters of crystalline silicon battery
CN113283053B (en) * 2021-04-17 2022-09-30 山西潞安太阳能科技有限责任公司 Method for establishing pecvd coating process parameters of crystalline silicon battery
CN113345836A (en) * 2021-06-01 2021-09-03 浙江集迈科微电子有限公司 TSV electroplating process
CN115206796A (en) * 2022-09-16 2022-10-18 杭州中欣晶圆半导体股份有限公司 Method for performing fixed-point deep silicon etching on surface of silicon wafer

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