CN113725213A - Transient voltage suppression protection device with compensation trap silicon controlled structure and manufacturing method thereof - Google Patents
Transient voltage suppression protection device with compensation trap silicon controlled structure and manufacturing method thereof Download PDFInfo
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- 230000001629 suppression Effects 0.000 title claims abstract description 20
- 230000001052 transient effect Effects 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 229910052710 silicon Inorganic materials 0.000 title abstract description 9
- 239000010703 silicon Substances 0.000 title abstract description 9
- 238000002347 injection Methods 0.000 claims abstract description 61
- 239000007924 injection Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 230000007935 neutral effect Effects 0.000 claims abstract description 13
- 238000002513 implantation Methods 0.000 claims description 54
- 239000002184 metal Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 230000002457 bidirectional effect Effects 0.000 description 5
- 239000000243 solution Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The invention provides a transient voltage suppression protection device with a compensation trap silicon controlled structure, which comprises an N-type substrate; a left P-type well and a right P-type well are formed at the top of the N-type substrate at intervals; a first P + injection region and a first N + injection region are formed in the left P-type well; a second P + injection region and a second N + injection region are formed in the right P-type well; a first N-type well, a second N-type well and a third N-type well are respectively manufactured in the middle of the left P-type well and the right P-type well, on the outer side of the left P-type well and on the outer side of the right P-type well, the left P-type well is respectively intersected with the second N-type well and the first N-type well on the two sides of the left P-type well, and the right P-type well is respectively intersected with the first N-type well and the third N-type well on the two sides of the right P-type well; the intersection region of the left P-type well and the N-type wells on the two sides of the intersection region, and the intersection region of the right P-type well and the N-type wells on the two sides of the intersection region respectively form neutral regions formed by impurity compensation; the device is more compact and saves cost.
Description
Technical Field
The invention relates to a transient voltage suppression protection device with a silicon controlled structure, in particular to a transient voltage suppression protection device with a compensation trap silicon controlled structure and a manufacturing method thereof.
Background
Transient Voltage Suppression (TVS) protection devices, referred to as TVS devices for short, are necessary surge protection devices in system application, and the applications of various TVS devices are different; in a dual power line system, two power supplies often have different voltages, so an asymmetric TVS device is required to be designed in a floating manner between the two power supplies, and the TVS device is usually realized in a manner of a diode string; the diode string has high clamping voltage and weak protection capability, and a plurality of devices are required to be connected in series for high-voltage application, so that the chip area is large, the cost is high, the cost efficiency is low, and the optimization is not performed;
for surge protection, the bidirectional NPN structure shown in fig. 1 is a reliable device that can be used for surge design of a 5V power supply, but it is difficult to apply to surge protection of an asymmetric power supply because of the symmetric characteristics of the bidirectional NPN structure.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a transient voltage suppression protection device with a well compensation silicon controlled rectifier structure and a manufacturing method thereof. In order to achieve the technical purpose, the embodiment of the invention adopts the technical scheme that:
in a first aspect, an embodiment of the present invention provides a transient voltage suppression protection device with a compensated well thyristor structure, including an N-type substrate;
a left P-type well and a right P-type well are formed at the top of the N-type substrate at intervals; a first P + injection region and a first N + injection region are formed in the left P-type well, and the first N + injection region is positioned on the right side of the first P + injection region; a second P + injection region and a second N + injection region are formed in the right P-type well, and the second N + injection region is positioned on the left side of the second P + injection region;
a first N-type well, a second N-type well and a third N-type well are respectively manufactured in the middle of the left P-type well and the right P-type well, on the outer side of the left P-type well and on the outer side of the right P-type well, the left P-type well is respectively intersected with the second N-type well and the first N-type well on the two sides of the left P-type well, and the right P-type well is respectively intersected with the first N-type well and the third N-type well on the two sides of the right P-type well; the intersection region of the left P-type well and the N-type wells on the two sides of the intersection region, and the intersection region of the right P-type well and the N-type wells on the two sides of the intersection region respectively form neutral regions formed by impurity compensation;
the first P + injection region and the first N + injection region are connected through a first metal to form one of an anode and a cathode of the device, and the second P + injection region and the second N + injection region are connected through a second metal to form the other of the anode and the cathode of the device.
Preferably, the doping concentrations of the left P-type well, the right P-type well, the first N-type well, the second N-type well and the third N-type well are the same.
Preferably, the junction depths of the left P-type well, the right P-type well, the first N-type well, the second N-type well and the third N-type well are the same.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a transient voltage suppression protection device with a compensated well thyristor structure, including:
step S10, providing an N-type substrate, and respectively manufacturing a left P-type well and a right P-type well at the top of the N-type substrate at intervals;
step S20, respectively manufacturing a first N-type well, a second N-type well and a third N-type well with the same dosage in the middle of the left P-type well and the right P-type well, outside the left P-type well and outside the right P-type well, and simultaneously annealing and junction pushing; the left P-type well is respectively intersected with the second N-type well and the first N-type well on the two sides of the left P-type well, and the right P-type well is respectively intersected with the first N-type well and the third N-type well on the two sides of the right P-type well; the intersection region of the left P-type well and the N-type wells on the two sides of the intersection region, and the intersection region of the right P-type well and the N-type wells on the two sides of the intersection region respectively form neutral regions formed by impurity compensation;
step S30, forming a first P + implantation region and a first N + implantation region in the left P-type well by ion implantation, the first N + implantation region being located on the right side of the first P + implantation region; forming a second P + injection region and a second N + injection region in the right P-type well through ion injection, wherein the second N + injection region is positioned on the left side of the second P + injection region;
step S40, connecting the first P + implantation region and the first N + implantation region through a first metal to form one of an anode and a cathode of the device, and connecting the second P + implantation region and the second N + implantation region through a second metal to form the other of the anode and the cathode of the device.
In a third aspect, an embodiment of the present invention provides a transient voltage suppression protection device with a compensated well thyristor structure, including a P-type substrate;
a left N-type well and a right N-type well are formed at the top of the P-type substrate at intervals; a first P + injection region and a first N + injection region are formed in the left N-type well, and the first N + injection region is positioned on the right side of the first P + injection region; a second P + injection region and a second N + injection region are formed in the right N-type well, and the second N + injection region is positioned on the left side of the second P + injection region;
a first P-type well, a second P-type well and a third P-type well are respectively manufactured in the middle of the left N-type well and the right N-type well, on the outer side of the left N-type well and on the outer side of the right N-type well, the left N-type well is respectively intersected with the second P-type well and the first P-type well on the two sides of the left N-type well, and the right N-type well is respectively intersected with the first P-type well and the third P-type well on the two sides of the right N-type well; the intersection region of the left N-type well and the P-type wells on the two sides of the intersection region, and the intersection region of the right N-type well and the P-type wells on the two sides of the intersection region respectively form neutral regions formed by impurity compensation;
the first P + injection region and the first N + injection region are connected through a first metal to form one of an anode and a cathode of the device, and the second P + injection region and the second N + injection region are connected through a second metal to form the other of the anode and the cathode of the device.
Preferably, the doping concentrations of the left N-type well, the right N-type well, the first P-type well, the second P-type well and the third P-type well are the same.
Preferably, the junction depths of the left N-type well, the right N-type well, the first P-type well, the second P-type well and the third P-type well are the same.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
1) compared with the TVS device with the existing bidirectional NPN structure, the TVS device has lower junction capacitance performance.
2) Compared with the TVS device with the existing diode string structure, the device is more compact, and the cost is saved.
3) The process is simple and has feasibility of mass production.
4) The method can be applied to surge protection of the asymmetric power supply.
Drawings
Fig. 1 is a schematic structural diagram of a TVS device with a conventional bidirectional NPN structure.
Fig. 2 is a schematic structural diagram of a TVS device in embodiment 1 of the present invention.
Fig. 3 is a schematic structural diagram of a TVS device in embodiment 2 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1;
as shown in fig. 2, the transient voltage suppression protection device with a compensated trap silicon controlled rectifier (SCR for short) structure according to the present embodiment includes an N-type substrate 1, and a left P-type well 2 and a right P-type well 3 are fabricated at an interval on the top of the N-type substrate 1; a first P + implantation region 201 and a first N + implantation region 202 are formed in the left P-type well 2, and the first N + implantation region 202 is located at the right side of the first P + implantation region 201; a second P + implantation region 301 and a second N + implantation region 302 are formed in the right P-type well 3, and the second N + implantation region 302 is located on the left side of the second P + implantation region 301;
a first N-type well 4, a second N-type well 5 and a third N-type well 6 are respectively manufactured in the middle of the left P-type well 2 and the right P-type well 3, on the outer side of the left P-type well 2 and on the outer side of the right P-type well 3, the left P-type well 2 is respectively intersected with the second N-type well 5 and the first N-type well 4 on the two sides of the left P-type well 2, and the right P-type well 3 is respectively intersected with the first N-type well 4 and the third N-type well 6 on the two sides of the right P-type well 3; the intersection region of the left P-type well 2 and the N-type wells on the two sides thereof and the intersection region of the right P-type well 3 and the N-type wells on the two sides thereof respectively form a neutral region 7 formed by impurity compensation;
it should be noted that, in order to form the ideal neutral region 7, the doping concentration of all P or N well regions must be the same and the junction depths are not greatly different; preferably, the doping concentrations of the left P-type well 2, the right P-type well 3, the first N-type well 4, the second N-type well 5 and the third N-type well 6 are the same, and the junction depths are the same;
the first P + implantation region 201 and the first N + implantation region 202 are connected through the first metal 8 to form one of an anode and a cathode of the device (when the first metal 8 is used as the anode, the second metal 9 is used as the cathode, or vice versa), and the second P + implantation region 301 and the second N + implantation region 302 are connected through the second metal 9 to form the other of the anode and the cathode of the device;
as shown in fig. 1, the parasitic capacitance of the SCR in the conventional bidirectional NPN structure is formed by two P-type wells (Pw in fig. 1) connected in series with two junction capacitances of an N-type epitaxial layer (N-epi in fig. 1); the P substrate in fig. 1 represents a P-type substrate, a represents a device anode, K represents a device cathode, P + represents a P + implantation region, and N + represents an N + implantation region; according to the method, through an impurity compensation well structure, a first N-type well 4 is formed between two P-type wells (namely a left P-type well 2 and a right P-type well 3) in an intersecting mode, the junction capacitance of the P-type well and the N-type well is greatly reduced by utilizing a neutral region formed by impurity compensation of the two P-type wells (namely the left P-type well 2 and the right P-type well 3) and the first N-type well 4, and meanwhile, the first N-type well 4 has a blocking effect on transverse diffusion of the two P-type wells (namely the left P-type well 2 and the right P-type well 3), so that the distance between the two P-type wells (namely the left P-type well 2 and the right P-type well 3) of a device can be properly reduced, and the area of a silicon wafer is saved;
according to the device structure, the total parasitic capacitance can be obviously reduced through the impurity compensation well; besides, the impurity compensation well can reduce the capacitance, and the double wells (P wells or N wells) of the device can avoid the problem of punch-through caused by transverse diffusion after annealing in the traditional structure, so that the layout of the device is more compact, and the cost is saved;
the method for manufacturing the transient voltage suppression protection device with the compensated trap silicon controlled structure provided by the embodiment comprises the following steps:
step S10, providing an N-type substrate 1, and manufacturing a left P-type well 2 and a right P-type well 3 at the top of the N-type substrate 1 at intervals;
step S20, respectively manufacturing a first N-type well 4, a second N-type well 5 and a third N-type well 6 with the same dosage in the middle of the left P-type well 2 and the right P-type well 3, outside the left P-type well 2 and outside the right P-type well 3, and simultaneously annealing and junction pushing; the left P-type well 2 is respectively intersected with a second N-type well 5 and a first N-type well 4 on two sides of the left P-type well, and the right P-type well 3 is respectively intersected with a first N-type well 4 and a third N-type well 6 on two sides of the right P-type well; the intersection region of the left P-type well 2 and the N-type wells on the two sides thereof and the intersection region of the right P-type well 3 and the N-type wells on the two sides thereof respectively form a neutral region 7 with low impurity concentration formed due to impurity compensation;
step S30, forming a first P + implantation region 201 and a first N + implantation region 202 in the left P-type well 2 by ion implantation, respectively, the first N + implantation region 202 being located on the right side of the first P + implantation region 201; forming a second P + implantation region 301 and a second N + implantation region 302 in the right P-type well 3 by ion implantation, respectively, the second N + implantation region 302 being located on the left side of the second P + implantation region 301;
step S40, connecting the first P + implantation region 201 and the first N + implantation region 202 through the first metal 8 to form one of an anode and a cathode of the device, and connecting the second P + implantation region 301 and the second N + implantation region 302 through the second metal 9 to form the other of the anode and the cathode of the device;
in the above process steps, the ultra-low impurity concentration is realized by the impurity compensation of the first N-type well 4 and the left and right P- type wells 2 and 3, so that the low junction capacitance is realized; according to the manufacturing method, because the epitaxial layer is not adopted, all layers are common layers in the semiconductor process, the process is simple, the feasibility of mass production is realized, and meanwhile, the TVS device with better performance can be designed due to the lower junction capacitance performance.
Example 2;
as shown in fig. 3, the transient voltage suppression protection device with a compensated well thyristor structure according to the embodiment includes a P-type substrate 1 ', wherein a left N-type well 2' and a right N-type well 3 'are formed at an interval on a top of the P-type substrate 1'; a first P + implantation region 201 and a first N + implantation region 202 are formed in the left N-type well 2', and the first N + implantation region 202 is located at the right side of the first P + implantation region 201; a second P + implantation region 301 and a second N + implantation region 302 are formed in the right N-type well 3', and the second N + implantation region 302 is located on the left side of the second P + implantation region 301;
a first P-type well 4 ', a second P-type well 5 ' and a third P-type well 6 ' are respectively manufactured in the middle of the left N-type well 2 ' and the right N-type well 3 ', the outer side of the left N-type well 2 ' and the outer side of the right N-type well 3 ', the left N-type well 2 ' is respectively intersected with the second P-type well 5 ' and the first P-type well 4 ' on the two sides of the left N-type well, and the right N-type well 3 ' is respectively intersected with the first P-type well 4 ' and the third P-type well 6 ' on the two sides of the right N-type well; the intersection region of the left N-type well 2 'and the P-type wells on the two sides thereof, and the intersection region of the right N-type well 3' and the P-type wells on the two sides thereof respectively form a neutral region 7 formed due to impurity compensation;
it should be noted that, in order to form the ideal neutral region 7, the doping concentration of all P or N well regions must be the same and the junction depths are not greatly different; preferably, the doping concentrations of the left N-type well 2 ', the right N-type well 3 ', the first P-type well 4 ', the second P-type well 5 ' and the third P-type well 6 ' are the same, and the junction depths are the same;
the first P + implantation region 201 and the first N + implantation region 202 are connected through a first metal 8 to form one of an anode and a cathode of the device, and the second P + implantation region 301 and the second N + implantation region 302 are connected through a second metal 9 to form the other of the anode and the cathode of the device;
the manufacturing method of this embodiment is similar to that of embodiment 1, and the description is omitted.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (7)
1. A transient voltage suppression protection device with a compensated trap controlled silicon structure comprises an N-type substrate (1),
a left P-type well (2) and a right P-type well (3) are formed at the top of the N-type substrate (1) at intervals; a first P + injection region (201) and a first N + injection region (202) are formed in the left P-type well (2), and the first N + injection region (202) is positioned on the right side of the first P + injection region (201); a second P + injection region (301) and a second N + injection region (302) are formed in the right P-type well (3), and the second N + injection region (302) is positioned on the left side of the second P + injection region (301);
a first N-type well (4), a second N-type well (5) and a third N-type well (6) are respectively manufactured in the middle of the left P-type well (2) and the right P-type well (3), on the outer side of the left P-type well (2) and on the outer side of the right P-type well (3), the left P-type well (2) is respectively intersected with the second N-type well (5) and the first N-type well (4) on the two sides of the left P-type well, and the right P-type well (3) is respectively intersected with the first N-type well (4) and the third N-type well (6) on the two sides of the right P-type well; the intersection region of the left P-type trap (2) and the N-type traps on the two sides of the intersection region, and the intersection region of the right P-type trap (3) and the N-type traps on the two sides of the intersection region respectively form neutral regions (7) formed by impurity compensation;
the first P + injection region (201) and the first N + injection region (202) are connected through a first metal (8) to form one of an anode and a cathode of the device, and the second P + injection region (301) and the second N + injection region (302) are connected through a second metal (9) to form the other of the anode and the cathode of the device.
2. The transient voltage suppression protection device with a compensated well thyristor structure of claim 1,
the doping concentrations of the left P-type well (2), the right P-type well (3), the first N-type well (4), the second N-type well (5) and the third N-type well (6) are the same.
3. The transient voltage suppression protection device with a compensated well thyristor structure of claim 1,
the junction depths of the left P-type well (2), the right P-type well (3), the first N-type well (4), the second N-type well (5) and the third N-type well (6) are the same.
4. A method for manufacturing a transient voltage suppression protection device with a well-compensated thyristor structure is characterized by comprising the following steps:
step S10, providing an N-type substrate (1), and manufacturing a left P-type well (2) and a right P-type well (3) at intervals on the top of the N-type substrate (1);
step S20, respectively manufacturing a first N-type well (4), a second N-type well (5) and a third N-type well (6) with the same dosage in the middle of the left P-type well (2) and the right P-type well (3), on the outer side of the left P-type well (2) and on the outer side of the right P-type well (3), and simultaneously annealing and junction pushing; the left P-type well (2) is respectively intersected with a second N-type well (5) and a first N-type well (4) on two sides of the left P-type well, and the right P-type well (3) is respectively intersected with the first N-type well (4) and a third N-type well (6) on two sides of the right P-type well; the intersection region of the left P-type trap (2) and the N-type traps on the two sides of the intersection region, and the intersection region of the right P-type trap (3) and the N-type traps on the two sides of the intersection region respectively form neutral regions (7) formed by impurity compensation;
step S30, respectively forming a first P + implantation region (201) and a first N + implantation region (202) in the left P-type well (2) by ion implantation, wherein the first N + implantation region (202) is positioned at the right side of the first P + implantation region (201); forming a second P + implantation region (301) and a second N + implantation region (302) in the right P-type well (3) by ion implantation, respectively, the second N + implantation region (302) being located on the left side of the second P + implantation region (301);
step S40, the first P + injection region (201) and the first N + injection region (202) are connected through the first metal (8) to form one of the anode and the cathode of the device, and the second P + injection region (301) and the second N + injection region (302) are connected through the second metal (9) to form the other of the anode and the cathode of the device.
5. A transient voltage suppression protection device with a compensated trap controlled silicon structure comprises a P-type substrate (1'), and is characterized in that,
a left N-type trap (2 ') and a right N-type trap (3 ') are manufactured at the top of the P-type substrate (1 ') at intervals; a first P + injection region (201) and a first N + injection region (202) are formed in the left N-type well (2'), and the first N + injection region (202) is positioned at the right side of the first P + injection region (201); a second P + injection region (301) and a second N + injection region (302) are formed in the right N-type well (3'), and the second N + injection region (302) is positioned on the left side of the second P + injection region (301);
a first P-type well (4 '), a second P-type well (5 ') and a third P-type well (6 ') are respectively manufactured in the middle of the left N-type well (2 ') and the right N-type well (3 '), on the outer side of the left N-type well (2 ') and the outer side of the right N-type well (3 '), the left N-type well (2 ') is respectively intersected with the second P-type well (5 ') and the first P-type well (4 ') on the two sides of the left N-type well, and the right N-type well (3 ') is respectively intersected with the first P-type well (4 ') and the third P-type well (6 ') on the two sides of the left N-type well; the intersection region of the left N-type trap (2 ') and the P-type traps on the two sides of the left N-type trap, and the intersection region of the right N-type trap (3') and the P-type traps on the two sides of the right N-type trap respectively form a neutral region (7) formed due to impurity compensation;
the first P + injection region (201) and the first N + injection region (202) are connected through a first metal (8) to form one of an anode and a cathode of the device, and the second P + injection region (301) and the second N + injection region (302) are connected through a second metal (9) to form the other of the anode and the cathode of the device.
6. The transient voltage suppression protection device with a compensated well thyristor structure of claim 5,
the doping concentrations of the left N-type well (2 '), the right N-type well (3 '), the first P-type well (4 '), the second P-type well (5 ') and the third P-type well (6 ') are the same.
7. The transient voltage suppression protection device with a compensated well thyristor structure of claim 5,
the junction depths of the left N-type well (2 '), the right N-type well (3 '), the first P-type well (4 '), the second P-type well (5 ') and the third P-type well (6 ') are the same.
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| CN116598309A (en) * | 2023-07-14 | 2023-08-15 | 江苏应能微电子股份有限公司 | Ultralow-capacitance bidirectional SCR-TVS device |
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| CN102522404A (en) * | 2011-12-30 | 2012-06-27 | 无锡新硅微电子有限公司 | Bidirectional SCR ESD protective circuit for low triggered voltage |
| CN105489503A (en) * | 2016-01-27 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure, forming method thereof, and electrostatic protection circuit |
| CN110047921A (en) * | 2018-01-15 | 2019-07-23 | 中芯国际集成电路制造(上海)有限公司 | Bidirectional triode thyristor structure |
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| CN102522404A (en) * | 2011-12-30 | 2012-06-27 | 无锡新硅微电子有限公司 | Bidirectional SCR ESD protective circuit for low triggered voltage |
| CN105489503A (en) * | 2016-01-27 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure, forming method thereof, and electrostatic protection circuit |
| CN110047921A (en) * | 2018-01-15 | 2019-07-23 | 中芯国际集成电路制造(上海)有限公司 | Bidirectional triode thyristor structure |
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