CN105489503A - Semiconductor structure, forming method thereof, and electrostatic protection circuit - Google Patents

Semiconductor structure, forming method thereof, and electrostatic protection circuit Download PDF

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Publication number
CN105489503A
CN105489503A CN201610056876.7A CN201610056876A CN105489503A CN 105489503 A CN105489503 A CN 105489503A CN 201610056876 A CN201610056876 A CN 201610056876A CN 105489503 A CN105489503 A CN 105489503A
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grid
region
well region
substrate
well
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CN201610056876.7A
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Chinese (zh)
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CN105489503B (en
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胡剑
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上海华虹宏力半导体制造有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

The invention provides a semiconductor structure, a forming method thereof, and an electrostatic protection circuit. The forming method includes the following steps: providing a substrate including a device zone; forming a plurality of well regions, in the substrate of the device zone, that are isolated through the substrate; forming grid structures on the surfaces of the well regions; and forming a source region at one side of each grid structure in the corresponding well region, and forming a drain region at the other side of each grid structure in the substrate, wherein the drain regions cross the adjacent well regions, and the adjacent grid structures share the source regions and the drain regions. A plurality of well regions are formed in the substrate of the device zone and are isolated by means of the substrate, so part of the drain regions are positioned in the well regions and part of the drain regions are positioned in the substrate. The stray capacitance of a GGNMOS (Gated Grounded NMOS) is influenced by the concentration of doped ions, and the lower the concentration of the doped ions is, the lower the stray capacitance is, while the concentration of doped ions of the substrate is smaller than the concentration of doped ions of the well regions. Therefore, the stray capacitance of the GGNMOS can be made to be reduced, the input/output time delay can be reduced, and the working speed of a chip can be increased.

Description

Semiconductor structure and forming method thereof, electrostatic discharge protective circuit

Technical field

The present invention relates to semiconductor applications, particularly relate to a kind of semiconductor structure and forming method thereof, electrostatic discharge protective circuit.

Background technology

The utilization of semiconductor chip is more and more extensive, and the factor causing semiconductor chip to be subject to electrostatic damage also gets more and more.In existing chip design, often adopt electrostatic discharge protective circuit (ESD, ElectrostaticDischarge) to reduce chip damage.The design and devdlop of existing ESD protection circuit comprises: the n type field effect transistor (GateGroundedNMOS of grid ground connection; be called for short GGNMOS) protective circuit, controllable silicon (SiliconControlledRectifier; be called for short SCR) protective circuit, horizontal proliferation field-effect transistor (LaterallyDiffusedMOS; be called for short LDMOS) protective circuit, bipolar junction transistor (BipolarJunctionTransistor is called for short BJT) protective circuit etc.Wherein, be widely used because GGNMOS and integrated circuit technology have compatible preferably.

But along with the development trend of very lagre scale integrated circuit (VLSIC), integrated circuit feature scales reduces, and the performance of prior art GGNMOS has much room for improvement.

Summary of the invention

The problem that the present invention solves is to provide a kind of semiconductor structure and forming method thereof, electrostatic discharge protective circuit, optimizes the performance of GGNMOS.

For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprise the steps: to provide substrate, described substrate comprises device region, several well regions are formed in the substrate of described device region, described well region comprises the first well region, the second well region, and one or several the 3rd well regions between described first well region and the second well region, isolated by described substrate between several well regions described, form grid structure on described well region surface, described grid structure comprises the first grid structure being positioned at described first well region surface, is positioned at the second grid structure on described second well region surface, is positioned at two the 3rd grid structures on described 3rd well region surface, source area is formed in described well region, described source area comprises and is positioned at first source area of described first grid structure away from described 3rd grid structure side, be positioned at second source area of described second grid structure away from described 3rd grid structure side, and the 3rd source area in same 3rd well region and between described two the 3rd grid structures, in described first grid structure or the substrate between second grid structure and adjacent 3rd grid structure, or, drain region is formed in substrate between adjacent 3rd grid structure of some 3rd well regions, described drain region comprises the first drain region in the substrate between described first grid structure and adjacent 3rd grid structure, described first drain region is across described first well region and the 3rd adjacent well region, the second drain region in substrate between described second grid structure and adjacent 3rd grid structure, described second drain region is across described second well region and the 3rd adjacent well region.

Optionally, the quantity of described 3rd well region is several, is formed in the step of described drain region, and described drain region also comprises the 3rd drain region between adjacent 3rd well region in substrate, and described 3rd drain region is across described the 3rd adjacent well region.

Optionally, before the described well region of formation, also comprise: in described substrate, form the first isolation structure and the second isolation structure; Formed in the step of described first well region and the second well region, form the first well region surrounding described first isolation structure, form the second well region surrounding described second isolation structure; Formed in the step of described source area, in the first well region between described first isolation structure and first grid structure, form described first source area, in the second well region between described second isolation structure and second grid structure, form described second source area.

Optionally, after becoming described well region, the first isolation structure and the second isolation structure, described formation method also comprises: form body contact region at described first isolation structure away from described first grid structure side, and the described body contact region of part is positioned at described first well region, form the second body contact zone at described second isolation structure away from described second grid structure side, and the described second body contact zone of part is positioned at described second well region.

Optionally, described semiconductor structure is grid ground connection n type field effect transistor, for electrostatic protection; The type that described well region, body contact region and the second body contact zone inject ion is P type, and the type that ion is injected in described drain region and source area is N-type.

Accordingly, the present invention also provides a kind of semiconductor structure, comprising: substrate, and described substrate comprises device region, be formed at several well regions in substrate, several well regions described comprise the first well region, the second well region that are positioned at described device region, and one or several the 3rd well regions between described first well region and the second well region, isolated by described substrate between several well regions described, be formed at the grid structure on described well region surface, described grid structure comprises the first grid structure being positioned at described first well region surface, is positioned at the second grid structure on described second well region surface, is positioned at two the 3rd grid structures on described 3rd well region surface, be positioned at the source area of described well region, described source area comprises and is positioned at first source area of described first grid structure away from described 3rd grid structure side, be positioned at second source area of described second grid structure away from described 3rd grid structure side, and the 3rd source area in same 3rd well region and between described 3rd grid structure, in described first grid structure or between second grid structure and adjacent 3rd grid structure, or, drain region between adjacent 3rd grid structure of some 3rd well regions in substrate, described drain region comprises the first drain region in the substrate between described first grid structure and adjacent 3rd grid structure, described first drain region is across described first well region and the 3rd adjacent well region, the second drain region in substrate between described second grid structure and adjacent 3rd grid structure, described second drain region is across described second well region and the 3rd adjacent well region.

Optionally, described semiconductor structure also comprises the first isolation structure being positioned at described first well region, and is positioned at the second isolation structure of described second well region; Described first isolation structure is positioned at first well region of described first source area away from described first grid structure side, and described second isolation structure is positioned at second well region of described second source area away from described second grid structure side.

Optionally, described semiconductor structure also comprises: be positioned at the body contact region of described first isolation structure away from described first grid structure side, a part for described body contact region is positioned at described first well region; Be positioned at the second body contact zone of described second isolation structure away from described second grid structure side, a part for described second body contact zone is positioned at described second well region.

Optionally, described semiconductor structure is grid ground connection n type field effect transistor, for electrostatic protection; The type of the Doped ions of described well region, body contact region and the second body contact zone is P type, and the type of described drain region and source area Doped ions is N-type.

Accordingly, the present invention also provides a kind of electrostatic discharge protective circuit, comprising: electrostatic input; Earth terminal; Semiconductor structure of the present invention, described substrate, source area and grid structure are connected to earth terminal, and described drain region and electrostatic input are electrical connected.

Compared with prior art, technical scheme of the present invention has the following advantages:

The present invention by forming several well regions in the substrate of device region, isolated by substrate between several well regions described, make drain region be positioned at described well region across adjacent well region, and part drain region is positioned at described well region, part drain region is positioned at described substrate.Parasitic capacitance due to GGNMOS is subject to the impact of Doped ions concentration, the less parasitic capacitance of Doped ions concentration is less, and the Doped ions concentration of described substrate is less than the Doped ions concentration of described well region, therefore the parasitic capacitance of GGNMOS can be made to reduce, thus the problem of input and output time delay can be reduced, and then promote the operating rate of chip.

Accompanying drawing explanation

Fig. 1 is the structural representation of prior art semiconductor structure one embodiment;

Fig. 2 to Fig. 5 is structural representation corresponding to formation method one embodiment of semiconductor structure of the present invention;

Fig. 6 is the structural representation of electrostatic discharge protective circuit one embodiment of the present invention.

Embodiment

From background technology, the performance of prior art GGNMOS has much room for improvement.Analyze its reason to be:

As shown in Figure 1, the structure of GGNMOS mono-embodiment comprises: substrate 100; Be arranged in the P type trap zone 110 of described substrate 100, be arranged in the isolation structure 150 of described P type trap zone 110, multiple grid structures between isolation structure 150 on described substrate 100, N-type doped region between grid structure or between grid structure and isolation structure 150, described N-type doped region is arranged in described P type trap zone 110.

Particularly, described multiple grid structure comprises first grid structure 121, second grid structure 122, the 3rd grid structure 123 and the 4th grid structure 124 successively between isolation structure 150.N-type doped region between first grid structure 121 and second grid structure 122, between the 3rd grid structure 123 and the 4th grid structure 124 is common drain district 130, and the N-type doped region between first grid structure 121 and isolation structure 150, between second grid structure 122 and the 3rd grid structure 123, between the 4th grid structure 124 and isolation structure 150 is source area 140.

Described common drain district 130 is electrical connected with described ESD input 170, described source area 140 and described grid structure ground connection.

GGNMOS comprises the parasitic NPN triode be made up of source area 140, common drain district 130 and the P type trap zone between described source area 140 and drain region 130 110.When ESD input 170 is subject to ESD electrostatic pulse; the transient potential in common drain district 130 is too high and trigger GGNMOS endoparasitism NPN triode ON; electric current flows into described common drain district 130 by described ESD input 170; and flow into described source area 140 by described common drain district 130; release ESD, to realize the effect of esd protection.

Between first grid structure 121 and second grid structure 122, the 3rd grid structure 123 and the 4th grid structure 124 share a common drain district 130, is equivalent to multiple NMOS and is connected in parallel, to improve the ability of esd protection.But the area as the described common drain district 130 of common field is comparatively large, therefore, the parasitic capacitance between described common drain district 130 to described well region 110 is corresponding also comparatively large, thus adds the time delay of input and output, and then reduces the operating rate of chip.

In order to solve the technical problem, the invention provides a kind of manufacture method of flash memory structure, comprising: providing substrate, described substrate comprises device region, several well regions are formed in the substrate of described device region, described well region comprises the first well region, the second well region that are positioned at described device region, and one or several the 3rd well regions between described first well region and the second well region, isolated by described substrate between several well regions described, form grid structure on described well region surface, described grid structure comprises the first grid structure being positioned at described first well region surface, is positioned at the second grid structure on described second well region surface, is positioned at two the 3rd grid structures on described 3rd well region surface, source area is formed in described well region, described source area comprises and is positioned at first source area of described first grid structure away from described 3rd grid structure side, be positioned at second source area of described second grid structure away from described 3rd grid structure side, and the 3rd source area in same 3rd well region and between described 3rd grid structure, in described first grid structure or the substrate between second grid structure and adjacent 3rd grid structure, or, drain region is formed in substrate between adjacent 3rd grid structure of some 3rd well regions, described drain region comprises the first drain region in the substrate between described first grid structure and adjacent 3rd grid structure, described first drain region is across described first well region and the 3rd adjacent well region, the second drain region in substrate between described second grid structure and adjacent 3rd grid structure, described second drain region is across described second well region and the 3rd adjacent well region.

The present invention by forming several well regions in the substrate of device region, isolated by substrate between several well regions described, make drain region be positioned at described well region across adjacent well region, and part drain region is positioned at described well region, part drain region is positioned at described substrate.Parasitic capacitance due to GGNMOS is subject to the impact of Doped ions concentration, the less parasitic capacitance of Doped ions concentration is less, and the Doped ions concentration of described substrate is less than the Doped ions concentration of described well region, therefore the parasitic capacitance of GGNMOS can be made to reduce, thus the problem of input and output time delay can be reduced, and then promote the operating rate of chip.

For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.

Fig. 2 to Fig. 5 is structural representation corresponding to formation method one embodiment of semiconductor structure of the present invention.

With reference to figure 2, provide substrate 200, described substrate 200 comprises device region I.

In the present embodiment, described device region I substrate 200 is for the formation of grid ground connection n type field effect transistor (GGNMOS, GateGroundedNMOS), and described substrate 200 is P type substrate.Wherein, described GGNMOS is used for static discharge (ESD, ElectrostaticDischarge) protection.

Described substrate 200 can be silicon substrate, germanium substrate, silicon carbide substrates or germanium silicon substrate.In the present embodiment, described substrate 200 is monocrystalline substrate.

It should be noted that, described substrate 200 is the intrinsic semiconductor of non-Doped ions; Or the Doped ions concentration of described substrate 200 is lower.

Also it should be noted that, described substrate also comprises the bonding pad II being positioned at both sides, described device region I.Described bonding pad II is for being connected to ground wire GND when subsequent metal interconnects by described substrate 200.

With reference to figure 3, several well regions are formed in described device region I substrate 200, described well region comprises the first well region 221, second well region 222, and one or several the 3rd well regions 223 between described first well region 221 and the second well region 222, isolated by described substrate 200 between several well regions described.

Described device region I substrate 200 is for the formation of GGNMOS; for esd protection; described well region and the follow-up adjacent source regions that formed in described well region both sides and drain region form parasitic NPN, and for realizing the function of Electro-static Driven Comb, described well region is equivalent to the base of NPN triode.

Accordingly, described well region is P type trap zone, and described first well region 221, second well region 222 is identical with concentration with the type of the 3rd well region 223 Doped ions.Particularly, described Doped ions can be B ion or BF ion, and the dosage of Doped ions is 1E12 to 1E13 atom per square centimeter.

In the present embodiment, the quantity of described 3rd well region 223 is one.

In other embodiments, the quantity of described 3rd well region is random natural number n, and n >=2.

It should be noted that, before the described well region of formation, also comprise: in described substrate 200, form the first isolation structure 211 and the second isolation structure 212.The step forming some well regions comprises: form the first well region 221 surrounding described first isolation structure 211, forms the second well region 222 surrounding described second isolation structure 212.

Particularly, described first isolation structure 211 is positioned at described first well region 221, and described second isolation structure 212 is positioned at described second well region 222.

With reference to figure 4, grid structure is formed on described well region surface, described grid structure comprises the first grid structure 231 being positioned at described first well region 221 surface, is positioned at the second grid structure 232 on described second well region 222 surface, is positioned at two the 3rd grid structures 233 on described 3rd well region 223 surface.

In the present embodiment, described grid structure is as the grid structure of GGNMOS.

It should be noted that; the electrostatic protection ability played owing to only relying on single GGNMOS is less; therefore form multiple grid structure and adopt adjacent transistor to share the mode of same source area or drain region, to realize the parallel connection of transistor, and then increasing the area of esd protection.

In the present embodiment, the quantity of described 3rd well region 223 is one, and accordingly, the quantity of described 3rd grid structure 233 is two.In other embodiments, the quantity of described 3rd well region is random natural number n, and n >=2, accordingly, the quantity of described 3rd grid structure is 2n.

In the present embodiment, the material of described grid structure is polysilicon.

It should be noted that, described first grid structure 231 is positioned at first well region 221 surface of described first isolation structure 211 near adjacent 3rd grid structure 233 side, described second grid structure 232 is positioned at second well region 222 surface of described second isolation structure 212 near adjacent 3rd grid structure 233 side, in the well region of described grid structure side, form source area so that follow-up, between the neighboring gate structures of different well region, form drain region.

With reference to figure 5, source area is formed in described well region, described source area comprises and is positioned at first source area 241 of described first grid structure 231 away from described 3rd grid structure 233 side, be positioned at second source area 242 of described second grid structure 232 away from described 3rd grid structure 233 side, and the 3rd source area 243 in same 3rd well region 223 and between described two the 3rd grid structures 233.

The drain region adjacent with described source area of described well region, source area and follow-up formation forms parasitic NPN triode, for realizing the function of Electro-static Driven Comb.Described source area is equivalent to the emitter region of NPN triode.

It should be noted that, the first isolation structure 211 is formed in described first well region 221, the second isolation structure 212 is formed in described second well region 222, in the present embodiment, form described first source area 241 in the first well region 221 between described first isolation structure 211 and first grid structure 231, in the second well region 222 between described second isolation structure 212 and second grid structure 232, form described second source area 242.

In the present embodiment, described semiconductor structure is GGNMOS, accordingly, the Doped ions type of described first source area 242, source area 241, second and the 3rd source area 243 is N-type ion, and described first source area 242, source area 241, second is identical with concentration with the type of the 3rd source area 243 Doped ions.Particularly, described Doped ions can be P ion, As ion or Sb ion, and the dosage of Doped ions is 1E12 to 1E13 atom per square centimeter.

Continue with reference to figure 5, in described first grid structure 231 or the substrate 200 between second grid structure 232 and adjacent 3rd grid structure 233, or, drain region is formed in substrate 200 between adjacent 3rd grid structure 233 of some 3rd well regions 223, described drain region comprises the first drain region 251 in the substrate 200 between described first grid structure 231 and adjacent 3rd grid structure 233, described first drain region 251 is across described first well region 221 and the 3rd adjacent well region 223, the second drain region 252 in substrate 200 between described second grid structure 232 and adjacent 3rd grid structure 233, described second drain region 252 is across described second well region 222 and the 3rd adjacent well region 233.

In the present embodiment, the quantity of described 3rd well region 223 is one, and described drain region comprises the first drain region 251 and the second drain region 252.In other embodiments, the quantity of described 3rd well region is random natural number n, and n >=2, accordingly, formed in the step of described drain region, described drain region also comprises the 3rd drain region between adjacent 3rd well region in substrate, and described 3rd drain region is across described the 3rd adjacent well region.

The NPN triode of adjacent described source area and drain region and the formation of the well region between described source area and drain region parasitism, for realizing the function of Electro-static Driven Comb.Described drain region is equivalent to the collector area of NPN triode.Such as, described first source area 241, first well region 221 and the first drain region 251 form a NPN triode.

It should be noted that, described drain region is the common drain district of adjacent NPN triode.

In the present embodiment, described semiconductor structure is GGNMOS, and accordingly, the Doped ions type of described first drain region 251 and the second drain region 252 is N-type ion, and described first drain region 251 is identical with concentration with the type of the second drain region 252 Doped ions.Particularly, described Doped ions can be P ion, As ion or Sb ion, and the dosage of Doped ions is 1E12 to 1E13 atom per square centimeter.

It should be noted that, described drain region is formed in ion doping technique with described source area.In other embodiments, described drain region and source area can also be formed respectively in different ions doping process.

In the present embodiment, after forming described well region, the first isolation structure 211 and the second isolation structure 212, also comprise: form body contact region 261 at described first isolation structure 211 away from described first grid structure 231 side, and the described body contact region 261 of part is positioned at described first well region 221, form the second body contact zone 262 at described second isolation structure 212 away from described second grid structure 232 side, and the described second body contact zone 262 of part is positioned at described second well region 222.Wherein, described body contact region 261 is formed in ion doping technique with described second body contact zone 262.

Described body contact region 261 and the second body contact zone 262 are for being connected to ground wire GND when subsequent metal interconnects by described substrate 200, described body contact region 261 is identical with the doping type of described substrate 200 with the doping type of the second body contact zone 262, and doping content is higher than described substrate 200, in order to reduce contact resistance.Particularly, the type of described body contact region 261 and the second body contact zone 262 Doped ions is P type ion, and described P type ion can be B ion or BF ion, and the dosage of Doped ions is 1E12 to 1E13 atom per square centimeter.

It should be noted that, in the present embodiment, first form described drain region and source area, then form described body contact region 261 and the second body contact zone 262.In other embodiments, first can also form body contact region and the second body contact zone, then form drain region and source area.

The present invention by forming several well regions in device region substrate 200, isolated by described substrate 200 between several well regions described, make common drain district across adjacent well region, and part drain region is positioned at described well region, part drain region is positioned at described substrate 200.Parasitic capacitance due to GGNMOS is subject to the impact of Doped ions concentration, the less parasitic capacitance of Doped ions concentration is less, the Doped ions concentration of substrate 200 described in the present embodiment is less than the Doped ions concentration of described well region, therefore compared with prior art, the parasitic capacitance of GGNMOS of the present invention reduces, thus the problem of input and output time delay can be reduced, and then promote the operating rate of chip.

Correspondingly, the embodiment of the present invention also provides a kind of semiconductor structure, continues with reference to figure 5, shows the schematic diagram of embodiment of the present invention semiconductor structure.Described semiconductor structure comprises:

Substrate 200, described substrate comprises device region I;

Be formed at several well regions in substrate 200, several well regions described comprise the first well region 221, second well region 222 being positioned at described device region I, and one or several the 3rd well regions 223 between described first well region 221 and the second well region 222, isolated by described substrate 200 between several well regions described;

Be formed at the grid structure on described well region surface, described grid structure comprises the first grid structure 231 being positioned at described first well region 221 surface, be positioned at the second grid structure 232 on described second well region 222 surface, and be positioned at two the 3rd grid structures 233 on described 3rd well region 223 surface;

Be positioned at the source area of described well region, described source area comprises and is positioned at first source area 241 of described first grid structure 231 away from described 3rd grid structure 233 side, be positioned at second source area 242 of described second grid structure 232 away from described 3rd grid structure 233 side, and the 3rd source area 243 at same 3rd well region 223 and between described two the 3rd grid structures 233;

In described first grid structure 231 or between second grid structure 232 and adjacent 3rd grid structure 233, or, drain region between adjacent 3rd grid structure 233 of some 3rd well regions 223 in substrate 200, described drain region comprises the first drain region 251 in the substrate 200 between described first grid structure 231 and adjacent 3rd grid structure 233, described first drain region 251 is across described first well region 221 and the 3rd adjacent well region 223, the second drain region 252 in substrate between described second grid structure 232 and adjacent 3rd grid structure 233, described second drain region 252 is across described second well region 222 and the 3rd adjacent well region 223.

In the present embodiment, the part surface of described drain region contacts with described well region, part surface contacts with described substrate 200, parasitic capacitance due to GGNMOS is subject to the impact of Doped ions concentration, the less parasitic capacitance of Doped ions concentration is less, the Doped ions concentration of substrate 200 described in the present embodiment is less than the Doped ions concentration of described well region, therefore, compared with prior art, the parasitic capacitance of GGNMOS of the present invention reduces, thus the problem of input and output time delay can be reduced, and then promote the operating rate of chip.

In the present embodiment, the quantity of described 3rd well region 223 is one, and the quantity of described 3rd grid structure 233 is two.

In other embodiments, the quantity of described 3rd well region is random natural number n, and n >=2.Accordingly, the quantity of described 3rd grid structure 233 is 2n, and described drain region also comprises the 3rd drain region (not shown) between adjacent 3rd well region in substrate, and described 3rd drain region is across described the 3rd adjacent well region.

In the present embodiment, described semiconductor structure also comprises the first isolation structure 211 being positioned at described first well region 221, and is positioned at the second isolation structure 212 of described second well region 222; Described first isolation structure 211 is positioned at first well region 221 of described first source area 241 away from described first grid structure 231 side, and described second isolation structure 212 is positioned at second well region 222 of described second source area 242 away from described second grid structure 232 side.

It should be noted that, described semiconductor structure also comprises: be positioned at the body contact region 261 of described first isolation structure 211 away from described first grid structure 231 side, a part for described body contact region 261 is positioned at described first well region 221; Be positioned at the second body contact zone 262 of described second isolation structure 212 away from described second grid structure 232 side, a part for described second body contact zone 262 is positioned at described second well region 222.

In the present embodiment, described substrate 200 also comprises the bonding pad II being positioned at both sides, described device region I.A part for described body contact region 261 is also positioned at described bonding pad II, and a part for described second body contact zone 262 is also positioned at described bonding pad II.

Described body contact region 261 and the second body contact zone 262 are for being connected to ground wire GND by described substrate 200, described body contact region 261 is identical with the doping type of described substrate 200 with the doping type of the second body contact zone 262, and doping content is higher than described substrate 200, in order to reduce contact resistance.

In the present embodiment, described semiconductor structure is grid ground connection n type field effect transistor (GGNMOS, GateGroundedNMOS), for esd protection.Adjacent described source area and drain region and the well region between described source area and drain region form NPN triode, for realizing the function of Electro-static Driven Comb, described drain region is equivalent to the collector area of NPN triode, described source area is equivalent to the emitter region of NPN triode, and described well region is equivalent to the base of NPN triode.Such as, described first source area 241, first well region 221 and the first drain region 251 form a NPN triode.

Accordingly, the type of the Doped ions of described well region, body contact region 261 and the second body contact zone 262 is P type, and the type of described drain region and source area Doped ions is N-type.

Particularly, the Doped ions of described first well region 221, second well region 222 and the 3rd well region 223 can be B ion or BF ion, and the dosage of Doped ions is 1E12 to 1E13 atom per square centimeter; The Doped ions of described first source area 242, source area 241, second and the 3rd source area 243 can be P ion, As ion or Sb ion, and the dosage of Doped ions is 1E12 to 1E13 atom per square centimeter; The Doped ions of described first drain region 251 and the second drain region 252 can be P ion, As ion or Sb ion, and the dosage of Doped ions is 1E12 to 1E13 atom per square centimeter.

With reference to figure 6, the embodiment of the present invention also provides a kind of electrostatic discharge protective circuit, comprising:

Electrostatic input 380;

Earth terminal (not shown);

Semiconductor structure provided by the invention, described substrate 200, source area and grid structure are connected to earth terminal, and described drain region and electrostatic input 380 are electrical connected.

In the present embodiment, described semiconductor structure is grid ground connection n type field effect transistor (GGNMOS, GateGroundedNMOS), specifically with reference to the explanation of a upper embodiment, can not repeat them here.

In the present embodiment, described electrostatic input 380 realizes being electrical connected by contact hole plug 370 and described drain region.Particularly, the material of described contact hole plug 370 is tungsten.

In the present embodiment, the part surface of described GGNMOS drain region contacts with described well region, part surface contacts with described substrate 200 (as shown in Figure 5), parasitic capacitance due to GGNMOS is subject to the impact of Doped ions concentration, the less parasitic capacitance of Doped ions concentration is less, the Doped ions concentration of substrate 200 described in the present embodiment is less than the ion doping concentration of described well region, therefore, compared with prior art, the parasitic capacitance of GGNMOS of the present invention reduces, thus the problem of input and output time delay can be reduced, and then promote the operating rate of chip.

It should be noted that, optionally, described semiconductor structure has body contact region 261 and the second body contact zone 262.Described body contact region 261 and the second body contact zone 262 are held with being also connected to.

Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (10)

1. a formation method for semiconductor structure, is characterized in that, comprising:
There is provided substrate, described substrate comprises device region;
Several well regions are formed in the substrate of described device region, described well region comprises the first well region, the second well region, and one or several the 3rd well regions between described first well region and the second well region, isolated by described substrate between several well regions described;
Form grid structure on described well region surface, described grid structure comprises the first grid structure being positioned at described first well region surface, is positioned at the second grid structure on described second well region surface, is positioned at two the 3rd grid structures on described 3rd well region surface;
Source area is formed in described well region, described source area comprises and is positioned at first source area of described first grid structure away from described 3rd grid structure side, be positioned at second source area of described second grid structure away from described 3rd grid structure side, and the 3rd source area in same 3rd well region and between described two the 3rd grid structures;
In described first grid structure or the substrate between second grid structure and adjacent 3rd grid structure, or, drain region is formed in substrate between adjacent 3rd grid structure of some 3rd well regions, described drain region comprises the first drain region in the substrate between described first grid structure and adjacent 3rd grid structure, described first drain region is across described first well region and the 3rd adjacent well region, the second drain region in substrate between described second grid structure and adjacent 3rd grid structure, described second drain region is across described second well region and the 3rd adjacent well region.
2. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the quantity of described 3rd well region is several, formed in the step of described drain region, described drain region also comprises the 3rd drain region between adjacent 3rd well region in substrate, and described 3rd drain region is across described the 3rd adjacent well region.
3. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, before the described well region of formation, also comprises: in described substrate, form the first isolation structure and the second isolation structure;
Formed in the step of described first well region and the second well region, form the first well region surrounding described first isolation structure, form the second well region surrounding described second isolation structure;
Formed in the step of described source area, in the first well region between described first isolation structure and first grid structure, form described first source area, in the second well region between described second isolation structure and second grid structure, form described second source area.
4. the formation method of semiconductor structure as claimed in claim 3, it is characterized in that, after forming described well region, the first isolation structure and the second isolation structure, described formation method also comprises: form body contact region at described first isolation structure away from described first grid structure side, and the described body contact region of part is positioned at described first well region, form the second body contact zone at described second isolation structure away from described second grid structure side, and the described second body contact zone of part is positioned at described second well region.
5. the formation method of semiconductor structure as claimed in claim 4, it is characterized in that, described semiconductor structure is grid ground connection n type field effect transistor, for electrostatic protection;
The type that described well region, body contact region and the second body contact zone inject ion is P type, and the type that ion is injected in described drain region and source area is N-type.
6. a semiconductor structure, is characterized in that, comprising:
Substrate, described substrate comprises device region;
Be formed at several well regions in substrate, several well regions described comprise the first well region, the second well region that are positioned at described device region, and one or several the 3rd well regions between described first well region and the second well region, isolated by described substrate between several well regions described;
Be formed at the grid structure on described well region surface, described grid structure comprises the first grid structure being positioned at described first well region surface, is positioned at the second grid structure on described second well region surface, is positioned at two the 3rd grid structures on described 3rd well region surface;
Be positioned at the source area of described well region, described source area comprises and is positioned at first source area of described first grid structure away from described 3rd grid structure side, be positioned at second source area of described second grid structure away from described 3rd grid structure side, and the 3rd source area in same 3rd well region and between described 3rd grid structure;
In described first grid structure or between second grid structure and adjacent 3rd grid structure, or, drain region between adjacent 3rd grid structure of some 3rd well regions in substrate, described drain region comprises the first drain region in the substrate between described first grid structure and adjacent 3rd grid structure, described first drain region is across described first well region and the 3rd adjacent well region, the second drain region in substrate between described second grid structure and adjacent 3rd grid structure, described second drain region is across described second well region and the 3rd adjacent well region.
7. semiconductor structure as claimed in claim 6, it is characterized in that, described semiconductor structure also comprises the first isolation structure being positioned at described first well region, and is positioned at the second isolation structure of described second well region;
Described first isolation structure is positioned at first well region of described first source area away from described first grid structure side, and described second isolation structure is positioned at second well region of described second source area away from described second grid structure side.
8. semiconductor structure as claimed in claim 7, it is characterized in that, described semiconductor structure also comprises:
Be positioned at the body contact region of described first isolation structure away from described first grid structure side, a part for described body contact region is positioned at described first well region;
Be positioned at the second body contact zone of described second isolation structure away from described second grid structure side, a part for described second body contact zone is positioned at described second well region.
9. semiconductor structure according to claim 8, is characterized in that, described semiconductor structure is grid ground connection n type field effect transistor, for electrostatic protection;
The type of the Doped ions of described well region, body contact region and the second body contact zone is P type, and the type of described drain region and source area Doped ions is N-type.
10. an electrostatic discharge protective circuit, is characterized in that, comprising:
Electrostatic input;
Earth terminal;
Semiconductor structure described in any one of claim 6 to 9, described substrate, source area and grid structure are connected to earth terminal, and described drain region and electrostatic input are electrical connected.
CN201610056876.7A 2016-01-27 2016-01-27 Semiconductor structure and forming method thereof, electrostatic discharge protective circuit CN105489503B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866922A (en) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 GGNMOS device used in ESD protective circuit
US20100301418A1 (en) * 2009-05-28 2010-12-02 BauaBTech Electrostatic discharge protection device
CN102315217A (en) * 2010-06-29 2012-01-11 上海宏力半导体制造有限公司 Multi-finger strip-type gate-ground N-channel metal oxide semiconductor (GGNMOS) and electrostatic protection circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100301418A1 (en) * 2009-05-28 2010-12-02 BauaBTech Electrostatic discharge protection device
CN101866922A (en) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 GGNMOS device used in ESD protective circuit
CN102315217A (en) * 2010-06-29 2012-01-11 上海宏力半导体制造有限公司 Multi-finger strip-type gate-ground N-channel metal oxide semiconductor (GGNMOS) and electrostatic protection circuit

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