CN102466777A

CN102466777A - Integrated circuit testing device

Info

Publication number: CN102466777A
Application number: CN2010105628377A
Authority: CN
Inventors: 刘甲全
Original assignee: Raydium Semiconductor Corp
Current assignee: Raydium Semiconductor Corp
Priority date: 2010-11-12
Filing date: 2010-11-23
Publication date: 2012-05-23
Also published as: TW201219806A

Abstract

The invention discloses an integrated circuit testing device. The integrated circuit test device includes a plurality of input terminals, conversion modules and output terminals. These input terminals are used to input a plurality of low-frequency signals in parallel. The conversion module is used to convert the low-frequency signals into a plurality of high-frequency signals. The output terminal is used to output the high-frequency signals sequentially. The ratio of the output frequency of the high-frequency signals to the input frequency of the low-frequency signals is related to the number of the input terminals.

Description

Arrangement for testing integrated circuit

Technical field

The present invention is relevant with integrated circuit testing (integrated circuit test); Particularly about a kind of arrangement for testing integrated circuit; The mode that converts the high frequency logic signal of sequence output through the low frequency logical signal with a plurality of parallel inputs into significantly increases its output frequency, so can the higher integrated circuit of test job frequency.

Background technology

In recent years, along with electronics technology is constantly progressive, the integrated circuit related industry also develops vigorously, and wherein the integrated circuit testing industry is an example.Generally speaking, its restriction of high output frequency is all arranged in order to the arrangement for testing integrated circuit that integrated circuit is tested, thereby the inconvenience when causing practical application.

For example; Suppose that the highest output frequency that a certain arrangement for testing integrated circuit has is 500Mbps; Representing this arrangement for testing integrated circuit the highest can be the work that the integrated circuit of 500Mbps is tested to frequency of operation only; Therefore, if the frequency of operation of integrated circuit is 1Gbps or 2Gbps, this arrangement for testing integrated circuit promptly can't be tested it.

Especially in today that the frequency of operation of integrated circuit improves constantly; Need constantly to upgrade the upgrading arrangement for testing integrated circuit for the integrated circuit that can test high frequency; Will make the testing cost of integrated circuit significantly increase; Do not meet productivity effect, also cause the market competitiveness of integrated circuit to reduce.

Summary of the invention

Therefore, the present invention proposes a kind of arrangement for testing integrated circuit, to address the above problem.

First specific embodiment according to the present invention is a kind of arrangement for testing integrated circuit.In this embodiment, arrangement for testing integrated circuit comprises a plurality of input ends, modular converter and output terminal.Modular converter couples these input ends.Output terminal couples modular converter.Input end is in order to import a plurality of low frequency signals respectively abreast.Modular converter is in order to convert these low frequency signals into a plurality of high-frequency signals.Output terminal is in order to these high-frequency signals of sequence ground output.The output frequency of these high-frequency signals is relevant with the number of these input ends with the ratio of the incoming frequency of these low frequency signals.

In practical application, if the incoming frequency of these low frequency signals of these input ends of input is F, and the number of these input ends is n, and then the incoming frequency of these high-frequency signals of this output terminal sequence output is (F*n), and n is a positive integer.

Modular converter can include a plurality of input logic elements and output logic element, and each the input logic element in these input logic elements is corresponding respectively and is coupled to these input ends that the output logic element is corresponding and is coupled to output terminal.Each input logic element in these input logic elements and the output logic element can be and (AND) lock element, anti-and (NAND) lock element or (OR) lock element, anti-or (NOR) lock element, mutual exclusion (XOR) lock element or anti-mutual exclusion (XNOR) lock element.

Modular converter can by element programmable logic gate array (Field Programmable Gate Array, FPGA) or ASIC (Application Specific Integrated Circuit ASIC) constitutes.Output terminal can be according to these high-frequency signals of particular order sequence ground output, and wherein, particular order can be to produce at random or relevant with putting in order of these input ends.

Compared to prior art; Arrangement for testing integrated circuit according to the present invention is the framework that adopts a plurality of input ends and single output terminal; Convert the mode of the high frequency logic signal of sequence output into through low frequency logical signal, make the output frequency of arrangement for testing integrated circuit to double, so can test integrated circuit with higher operational frequency with a plurality of parallel inputs; So can save the testing cost of integrated circuit effectively, promote the market competitiveness of integrated circuit thus.

In addition; Because the increase multiple of the output frequency of arrangement for testing integrated circuit is proportional with the number of its input end; Therefore; The number of the input end of the demand adjustment arrangement for testing integrated circuit when the integrated circuit testing personnel can test according to reality, as long as make the output frequency of arrangement for testing integrated circuit can be higher than the frequency of operation of integrated circuit, the elasticity in the time of also can increasing integrated circuit testing.

Can graphicly further be understood through following detailed Description Of The Invention and appended about advantage of the present invention and spirit.

Description of drawings

Fig. 1 is the functional block diagram that illustrates according to the arrangement for testing integrated circuit of a specific embodiment of the present invention.

Fig. 2 illustrates the synoptic diagram that modular converter among Fig. 1 comprises logic element.

Fig. 3 is the functional block diagram that illustrates according to the arrangement for testing integrated circuit of another specific embodiment of the present invention.

Fig. 4 illustrates the synoptic diagram that modular converter among Fig. 3 comprises the first input logic element, the second input logic element and output logic element.

The main element symbol description

1,2: arrangement for testing integrated circuit

11: 12: the second input ends of first input end

13,26: modular converter 14,25: output terminal

LF1: the first low frequency signal LF2: second low frequency signal

HF1: the first high-frequency signal HF2: second high-frequency signal

130: logic element P _In1: the first input pin

P _In2: the second input end P _Out: output connecting pin

21～24: input end 264: the output logic element

262: the second input logic elements of 260: the first input logic elements

Embodiment

A specific embodiment according to the present invention is a kind of arrangement for testing integrated circuit.As its name suggests, arrangement for testing integrated circuit is in order to carry out various test job to integrated circuit.

In fact; The kind of the integrated circuit of tested person and form do not have specific restriction, can be simulation (analog) integrated circuit, numeral (digital) integrated circuit, wireless telecommunications (wireless communication) integrated circuit, ASIC (ASIC) or other integrated circuit arbitrarily.

Also not having specific restriction as for arrangement for testing integrated circuit for the test event that integrated circuit carried out, can be proof voltage test, anti-testing current or the relevant testing electrical property project of other integrated circuit.

Please with reference to Fig. 1, Fig. 1 is the functional block diagram that illustrates the arrangement for testing integrated circuit of this embodiment.As shown in Figure 1, arrangement for testing integrated circuit 1 comprises first input end 11, second input end 12, modular converter 13 and output terminal 14.Wherein, the first input end 11 and second input end 12 are coupled to modular converter 13, and modular converter 13 is coupled to output terminal 14.

Only comprise two input ends though it should be noted that the arrangement for testing integrated circuit 1 among this embodiment, in fact the number of input end can also be three, four even more a plurality of, and the demand when looking integrated circuit testing and deciding does not have specific restriction.

The first input end 11 and second input end 12 are in order to import the first low frequency signal LF1 and the second low frequency signal LF2 respectively abreast.That is to say that the first low frequency signal LF1 inputs to modular converter 13, the second low frequency signal LF2 through first input end 11 to input to modular converter 13 through second input end 12.

Then, modular converter 13 promptly can convert the first low frequency signal LF1 and the second low frequency signal LF2 into the first high-frequency signal HF1 and the second high-frequency signal HF2, and the first high-frequency signal HF1 after will changing and the second high-frequency signal HF2 are sent to output terminal 14.

In practical application; Modular converter 13 can be by element programmable logic gate array (Field Programmable Gate Array; FPGA) or ASIC (Application Specific Integrated Circuit ASIC) constitutes, but not as limit.

In this embodiment; Because arrangement for testing integrated circuit 1 comprises two input ends (first input end 11 and second input end 12) and an output terminal 14; Therefore; As shown in Figure 2, modular converter 13 comprises logic element 130 accordingly, and logic element 130 has two input pins (first input pin P _In1And the second input end P _In2) and an output connecting pin P _OutWherein, the first input pin P _In1Correspondence also is coupled to first input end 11; The second input end P _In2Correspondence also is coupled to second input end 12; Output connecting pin P _OutCorrespondence also is coupled to output terminal 14.

In practical application, above-mentioned logic element 130 can be and (AND) lock element, anti-and (NAND) lock element or (OR) lock element, anti-or (NOR) lock element, mutual exclusion (XOR) lock element or anti-mutual exclusion (XNOR) lock element, but not as limit.

Like Fig. 3 and shown in Figure 4; In another embodiment; Suppose that arrangement for testing integrated circuit 2 comprises four input ends 21～24 and an output terminal 25, then its modular converter 26 will comprise the first input logic element 260, the second input logic element 262 and output logic element 264 accordingly.Wherein,

input end

21 and 22 corresponding and be coupled to the first input logic element 260;

Input end

23 and 24 correspondences also are coupled to the second input logic element 262; The first input logic element 260 and the second input logic element 262 are coupled to output logic element 264; Output logic element 264 correspondences also are coupled to output terminal 25.

In practical application; The above-mentioned first input logic element 260, the second input logic element 262 and output logic element 264 can be and (AND) lock element, anti-and (NAND) lock element or (OR) lock element, anti-or (NOR) lock element, mutual exclusion (XOR) lock element or anti-mutual exclusion (XNOR) lock element, but not as limit.

Get back to Fig. 1; It should be noted that; Because arrangement for testing integrated circuit 1 only comprises single output terminal 14; And this output terminal 14 also can't be exported the first high-frequency signal HF1 and the second high-frequency signal HF2 simultaneously, and therefore, output terminal 14 will the sequence ground output first high-frequency signal HF1 and the second high-frequency signal HF2.

Particular order as for the output terminal 14 sequences ground output first high-frequency signal HF1 and the second high-frequency signal HF2 is not limited to them, and particular order can be to produce at random or relevant with putting in order of the first input end 11 and second input end 12.That is to say, be example with this embodiment, after output terminal 14 can be exported the first high-frequency signal HF1 earlier; Export the second high-frequency signal HF2 again; Perhaps output terminal 14 behind the output second high-frequency signal HF2, is exported the first high-frequency signal HF1 earlier again, the demand when looking actual test and deciding.

It should be noted that the hypothesis input end that arrangement for testing integrated circuit of the present invention comprised number be n, n is a positive integer, and low frequency signal abreast the incoming frequency of input ic proving installation be f _In, the output frequency of these high-frequency signals of arrangement for testing integrated circuit sequence ground output is f _Out, output frequency f then _Out=f _In* n.

Therefore, because the arrangement for testing integrated circuit 1 among Fig. 1 comprises two

input ends

11 and 12, so F _Out=2*F _In, that is the output frequency of arrangement for testing integrated circuit 1 will be the twice of incoming frequency; Because the arrangement for testing integrated circuit 2 among Fig. 3 comprises four input ends 21～24, so F _Out=4*F _In, that is the output frequency of arrangement for testing integrated circuit 2 will be four times of incoming frequency.When arrangement for testing integrated circuit comprises the input end of different numbers, also can the rest may be inferred, so do not give unnecessary details separately in this.

Through the detailed description of above preferred embodiment, be to hope to know more to describe characteristic of the present invention and spirit, and be not to come category of the present invention is limited with the above-mentioned preferred embodiment that is disclosed.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention desire application.

Claims

1. An integrated circuit testing device, comprising:

A plurality of input terminals are used to respectively input a plurality of low-frequency signals in parallel;

a conversion module, coupled to the input terminals, for converting the low-frequency signals into a plurality of high-frequency signals; and

an output terminal, coupled to the conversion module, for sequentially outputting the high-frequency signals;

Wherein, the ratio of the output frequency of the high frequency signals to the input frequency of the low frequency signals is related to the number of the input terminals.

2. The integrated circuit testing device as claimed in claim 1, wherein if the input frequency of the low-frequency signals input to the input terminals is F, and the number of the input terminals is n, the output serial output of the output terminal is of equal height The input frequency of the frequency signal is (F*n), and n is a positive integer.

3. The integrated circuit testing device as claimed in claim 1, wherein the conversion module is composed of an element programmable logic gate array (Field Programmable Gate Array, FPGA).

4. The integrated circuit testing device as claimed in claim 1, wherein the conversion module is composed of an Application Specific Integrated Circuit (ASIC).

5. The integrated circuit testing device as claimed in claim 1, wherein the conversion module comprises at least one logic element, and the at least one logic element corresponds to and is coupled to the input terminals and the output terminal respectively.

6. The integrated circuit testing device as claimed in claim 5, wherein the at least one logic element is selected from an AND (AND) gate element, a reverse AND (NAND) gate element, an OR (OR) gate element, an inverse A group consisting of an OR (NOR) gate element, a mutual exclusion (XOR) gate element and a non-exclusive (XNOR) gate element.

7. The integrated circuit testing device as claimed in claim 5, wherein the at least one logic element comprises a plurality of input logic elements and an output logic element, the input logic elements respectively correspond to and are coupled to the input terminals, the output The logic element corresponds to and is coupled to the output terminal.

8. The integrated circuit testing device as claimed in claim 1, wherein the output terminal sequentially outputs the high-frequency signals according to a specific order.

9. The integrated circuit testing device as claimed in claim 8, wherein the specific order is related to an arrangement order of the input terminals.

10. The integrated circuit testing device as claimed in claim 8, wherein the specific order is randomly generated.