CN102466777A - Integrated circuit testing device - Google Patents
Integrated circuit testing device Download PDFInfo
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- CN102466777A CN102466777A CN2010105628377A CN201010562837A CN102466777A CN 102466777 A CN102466777 A CN 102466777A CN 2010105628377 A CN2010105628377 A CN 2010105628377A CN 201010562837 A CN201010562837 A CN 201010562837A CN 102466777 A CN102466777 A CN 102466777A
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- 230000007717 exclusion Effects 0.000 claims description 8
- 230000008676 import Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 5
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Abstract
The invention discloses an integrated circuit testing device. The integrated circuit testing device comprises a plurality of input ends, a conversion module and an output end. The input terminals are used to input plural low frequency signals in parallel respectively. The conversion module is used for converting the low-frequency signals into a plurality of high-frequency signals. The output terminal is used to output the high frequency signals in sequence. The ratio of the output frequency of the high frequency signals to the input frequency of the low frequency signals is related to the number of the input terminals.
Description
Technical field
The present invention is relevant with integrated circuit testing (integrated circuit test); Particularly about a kind of arrangement for testing integrated circuit; The mode that converts the high frequency logic signal of sequence output through the low frequency logical signal with a plurality of parallel inputs into significantly increases its output frequency, so can the higher integrated circuit of test job frequency.
Background technology
In recent years, along with electronics technology is constantly progressive, the integrated circuit related industry also develops vigorously, and wherein the integrated circuit testing industry is an example.Generally speaking, its restriction of high output frequency is all arranged in order to the arrangement for testing integrated circuit that integrated circuit is tested, thereby the inconvenience when causing practical application.
For example; Suppose that the highest output frequency that a certain arrangement for testing integrated circuit has is 500Mbps; Representing this arrangement for testing integrated circuit the highest can be the work that the integrated circuit of 500Mbps is tested to frequency of operation only; Therefore, if the frequency of operation of integrated circuit is 1Gbps or 2Gbps, this arrangement for testing integrated circuit promptly can't be tested it.
Especially in today that the frequency of operation of integrated circuit improves constantly; Need constantly to upgrade the upgrading arrangement for testing integrated circuit for the integrated circuit that can test high frequency; Will make the testing cost of integrated circuit significantly increase; Do not meet productivity effect, also cause the market competitiveness of integrated circuit to reduce.
Summary of the invention
Therefore, the present invention proposes a kind of arrangement for testing integrated circuit, to address the above problem.
First specific embodiment according to the present invention is a kind of arrangement for testing integrated circuit.In this embodiment, arrangement for testing integrated circuit comprises a plurality of input ends, modular converter and output terminal.Modular converter couples these input ends.Output terminal couples modular converter.Input end is in order to import a plurality of low frequency signals respectively abreast.Modular converter is in order to convert these low frequency signals into a plurality of high-frequency signals.Output terminal is in order to these high-frequency signals of sequence ground output.The output frequency of these high-frequency signals is relevant with the number of these input ends with the ratio of the incoming frequency of these low frequency signals.
In practical application, if the incoming frequency of these low frequency signals of these input ends of input is F, and the number of these input ends is n, and then the incoming frequency of these high-frequency signals of this output terminal sequence output is (F*n), and n is a positive integer.
Modular converter can include a plurality of input logic elements and output logic element, and each the input logic element in these input logic elements is corresponding respectively and is coupled to these input ends that the output logic element is corresponding and is coupled to output terminal.Each input logic element in these input logic elements and the output logic element can be and (AND) lock element, anti-and (NAND) lock element or (OR) lock element, anti-or (NOR) lock element, mutual exclusion (XOR) lock element or anti-mutual exclusion (XNOR) lock element.
Modular converter can by element programmable logic gate array (Field Programmable Gate Array, FPGA) or ASIC (Application Specific Integrated Circuit ASIC) constitutes.Output terminal can be according to these high-frequency signals of particular order sequence ground output, and wherein, particular order can be to produce at random or relevant with putting in order of these input ends.
Compared to prior art; Arrangement for testing integrated circuit according to the present invention is the framework that adopts a plurality of input ends and single output terminal; Convert the mode of the high frequency logic signal of sequence output into through low frequency logical signal, make the output frequency of arrangement for testing integrated circuit to double, so can test integrated circuit with higher operational frequency with a plurality of parallel inputs; So can save the testing cost of integrated circuit effectively, promote the market competitiveness of integrated circuit thus.
In addition; Because the increase multiple of the output frequency of arrangement for testing integrated circuit is proportional with the number of its input end; Therefore; The number of the input end of the demand adjustment arrangement for testing integrated circuit when the integrated circuit testing personnel can test according to reality, as long as make the output frequency of arrangement for testing integrated circuit can be higher than the frequency of operation of integrated circuit, the elasticity in the time of also can increasing integrated circuit testing.
Can graphicly further be understood through following detailed Description Of The Invention and appended about advantage of the present invention and spirit.
Description of drawings
Fig. 1 is the functional block diagram that illustrates according to the arrangement for testing integrated circuit of a specific embodiment of the present invention.
Fig. 2 illustrates the synoptic diagram that modular converter among Fig. 1 comprises logic element.
Fig. 3 is the functional block diagram that illustrates according to the arrangement for testing integrated circuit of another specific embodiment of the present invention.
Fig. 4 illustrates the synoptic diagram that modular converter among Fig. 3 comprises the first input logic element, the second input logic element and output logic element.
The main element symbol description
1,2: arrangement for testing integrated circuit
11: 12: the second input ends of first input end
13,26: modular converter 14,25: output terminal
LF1: the first low frequency signal LF2: second low frequency signal
HF1: the first high-frequency signal HF2: second high-frequency signal
130: logic element P
In1: the first input pin
P
In2: the second input end P
Out: output connecting pin
21～24: input end 264: the output logic element
262: the second input logic elements of 260: the first input logic elements
Embodiment
A specific embodiment according to the present invention is a kind of arrangement for testing integrated circuit.As its name suggests, arrangement for testing integrated circuit is in order to carry out various test job to integrated circuit.
In fact; The kind of the integrated circuit of tested person and form do not have specific restriction, can be simulation (analog) integrated circuit, numeral (digital) integrated circuit, wireless telecommunications (wireless communication) integrated circuit, ASIC (ASIC) or other integrated circuit arbitrarily.
Also not having specific restriction as for arrangement for testing integrated circuit for the test event that integrated circuit carried out, can be proof voltage test, anti-testing current or the relevant testing electrical property project of other integrated circuit.
Please with reference to Fig. 1, Fig. 1 is the functional block diagram that illustrates the arrangement for testing integrated circuit of this embodiment.As shown in Figure 1, arrangement for testing integrated circuit 1 comprises first input end 11, second input end 12, modular converter 13 and output terminal 14.Wherein, the first input end 11 and second input end 12 are coupled to modular converter 13, and modular converter 13 is coupled to output terminal 14.
Only comprise two input ends though it should be noted that the arrangement for testing integrated circuit 1 among this embodiment, in fact the number of input end can also be three, four even more a plurality of, and the demand when looking integrated circuit testing and deciding does not have specific restriction.
The first input end 11 and second input end 12 are in order to import the first low frequency signal LF1 and the second low frequency signal LF2 respectively abreast.That is to say that the first low frequency signal LF1 inputs to modular converter 13, the second low frequency signal LF2 through first input end 11 to input to modular converter 13 through second input end 12.
Then, modular converter 13 promptly can convert the first low frequency signal LF1 and the second low frequency signal LF2 into the first high-frequency signal HF1 and the second high-frequency signal HF2, and the first high-frequency signal HF1 after will changing and the second high-frequency signal HF2 are sent to output terminal 14.
In practical application; Modular converter 13 can be by element programmable logic gate array (Field Programmable Gate Array; FPGA) or ASIC (Application Specific Integrated Circuit ASIC) constitutes, but not as limit.
In this embodiment; Because arrangement for testing integrated circuit 1 comprises two input ends (first input end 11 and second input end 12) and an output terminal 14; Therefore; As shown in Figure 2, modular converter 13 comprises logic element 130 accordingly, and logic element 130 has two input pins (first input pin P
In1And the second input end P
In2) and an output connecting pin P
OutWherein, the first input pin P
In1Correspondence also is coupled to first input end 11; The second input end P
In2Correspondence also is coupled to second input end 12; Output connecting pin P
OutCorrespondence also is coupled to output terminal 14.
In practical application, above-mentioned logic element 130 can be and (AND) lock element, anti-and (NAND) lock element or (OR) lock element, anti-or (NOR) lock element, mutual exclusion (XOR) lock element or anti-mutual exclusion (XNOR) lock element, but not as limit.
Like Fig. 3 and shown in Figure 4; In another embodiment; Suppose that arrangement for testing integrated circuit 2 comprises four input ends 21～24 and an output terminal 25, then its modular converter 26 will comprise the first input logic element 260, the second input logic element 262 and output logic element 264 accordingly.Wherein, input end 21 and 22 corresponding and be coupled to the first input logic element 260; Input end 23 and 24 correspondences also are coupled to the second input logic element 262; The first input logic element 260 and the second input logic element 262 are coupled to output logic element 264; Output logic element 264 correspondences also are coupled to output terminal 25.
In practical application; The above-mentioned first input logic element 260, the second input logic element 262 and output logic element 264 can be and (AND) lock element, anti-and (NAND) lock element or (OR) lock element, anti-or (NOR) lock element, mutual exclusion (XOR) lock element or anti-mutual exclusion (XNOR) lock element, but not as limit.
Get back to Fig. 1; It should be noted that; Because arrangement for testing integrated circuit 1 only comprises single output terminal 14; And this output terminal 14 also can't be exported the first high-frequency signal HF1 and the second high-frequency signal HF2 simultaneously, and therefore, output terminal 14 will the sequence ground output first high-frequency signal HF1 and the second high-frequency signal HF2.
Particular order as for the output terminal 14 sequences ground output first high-frequency signal HF1 and the second high-frequency signal HF2 is not limited to them, and particular order can be to produce at random or relevant with putting in order of the first input end 11 and second input end 12.That is to say, be example with this embodiment, after output terminal 14 can be exported the first high-frequency signal HF1 earlier; Export the second high-frequency signal HF2 again; Perhaps output terminal 14 behind the output second high-frequency signal HF2, is exported the first high-frequency signal HF1 earlier again, the demand when looking actual test and deciding.
It should be noted that the hypothesis input end that arrangement for testing integrated circuit of the present invention comprised number be n, n is a positive integer, and low frequency signal abreast the incoming frequency of input ic proving installation be f
In, the output frequency of these high-frequency signals of arrangement for testing integrated circuit sequence ground output is f
Out, output frequency f then
Out=f
In* n.
Therefore, because the arrangement for testing integrated circuit 1 among Fig. 1 comprises two input ends 11 and 12, so F
Out=2*F
In, that is the output frequency of arrangement for testing integrated circuit 1 will be the twice of incoming frequency; Because the arrangement for testing integrated circuit 2 among Fig. 3 comprises four input ends 21～24, so F
Out=4*F
In, that is the output frequency of arrangement for testing integrated circuit 2 will be four times of incoming frequency.When arrangement for testing integrated circuit comprises the input end of different numbers, also can the rest may be inferred, so do not give unnecessary details separately in this.
Compared to prior art; Arrangement for testing integrated circuit according to the present invention is the framework that adopts a plurality of input ends and single output terminal; Convert the mode of the high frequency logic signal of sequence output into through low frequency logical signal, make the output frequency of arrangement for testing integrated circuit to double, so can test integrated circuit with higher operational frequency with a plurality of parallel inputs; So can save the testing cost of integrated circuit effectively, promote the market competitiveness of integrated circuit thus.
In addition; Because the increase multiple of the output frequency of arrangement for testing integrated circuit is proportional with the number of its input end; Therefore; The number of the input end of the demand adjustment arrangement for testing integrated circuit when the integrated circuit testing personnel can test according to reality, as long as make the output frequency of arrangement for testing integrated circuit can be higher than the frequency of operation of integrated circuit, the elasticity in the time of also can increasing integrated circuit testing.
Through the detailed description of above preferred embodiment, be to hope to know more to describe characteristic of the present invention and spirit, and be not to come category of the present invention is limited with the above-mentioned preferred embodiment that is disclosed.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention desire application.
Claims (10)
1. arrangement for testing integrated circuit comprises:
A plurality of input ends are in order to import a plurality of low frequency signals respectively abreast;
One modular converter couples these input ends, in order to convert these low frequency signals into a plurality of high-frequency signals; And
One output terminal couples this modular converter, in order to these high-frequency signals of sequence ground output;
Wherein, the output frequency of these high-frequency signals is relevant with the number of these input ends with the ratio of the incoming frequency of these low frequency signals.
2. arrangement for testing integrated circuit as claimed in claim 1; Wherein if the incoming frequency of these low frequency signals of these input ends of input is F; And the number of these input ends is n, and then the incoming frequency of these high-frequency signals of this output terminal sequence output is (F*n), and n is a positive integer.
3. arrangement for testing integrated circuit as claimed in claim 1, wherein this modular converter is that (Field Programmable Gate Array FPGA) constitutes by element programmable logic gate array.
4. arrangement for testing integrated circuit as claimed in claim 1, wherein this modular converter is that (Application Specific Integrated Circuit ASIC) constitutes by ASIC.
5. arrangement for testing integrated circuit as claimed in claim 1, wherein this modular converter comprises at least one logic element, and this at least one logic element is corresponding respectively and be coupled to these input ends and this output terminal.
6. arrangement for testing integrated circuit as claimed in claim 5, wherein this at least one logic element is to be selected from by one and (AND) lock element, counter reaching (NAND) lock element, one or (OR) lock element, anti-or (NOR) group that formed of lock element, a mutual exclusion (XOR) lock element and anti-mutual exclusion (XNOR) lock element.
7. arrangement for testing integrated circuit as claimed in claim 5; Wherein this at least one logic element comprises a plurality of input logic elements and an output logic element; These input logic elements are corresponding respectively and be coupled to these input ends, and this output logic element correspondence also is coupled to this output terminal.
8. arrangement for testing integrated circuit as claimed in claim 1, wherein this output terminal is according to these high-frequency signals of particular order sequence ground output.
9. arrangement for testing integrated circuit as claimed in claim 8, wherein this particular order is relevant with putting in order of these input ends.
10. arrangement for testing integrated circuit as claimed in claim 8, wherein this particular order is for produce at random.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99139083A TW201219806A (en) | 2010-11-12 | 2010-11-12 | Integrated circuit testing apparatus |
| TW099139083 | 2010-11-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102466777A true CN102466777A (en) | 2012-05-23 |
Family
ID=46070675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105628377A Pending CN102466777A (en) | 2010-11-12 | 2010-11-23 | Integrated circuit testing device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102466777A (en) |
| TW (1) | TW201219806A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106959411A (en) * | 2017-03-29 | 2017-07-18 | 安徽云塔电子科技有限公司 | A kind of method of testing of integrated circuit and integrated circuit |
| CN108957300A (en) * | 2018-09-03 | 2018-12-07 | 长鑫存储技术有限公司 | Wafer test apparatus and test method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089819A (en) * | 1988-10-05 | 1992-02-18 | Hitachi, Ltd. | Parallel-to-serial signal converting apparatus and image displaying system using the same |
| CN1591694A (en) * | 2003-08-25 | 2005-03-09 | 三星电子株式会社 | Apparatus and method for testing semiconductor memory devices |
| CN1928753A (en) * | 2005-07-20 | 2007-03-14 | 阿尔特拉公司 | Clock circuitry for programmable logic devices |
| CN101369000A (en) * | 2008-09-12 | 2009-02-18 | 北京中星微电子有限公司 | Digital chip testing method and testing system |
| CN101446843A (en) * | 2008-12-30 | 2009-06-03 | 北京中星微电子有限公司 | High-frequency clock generator, clock frequency conversion method, and chip |
| US20100127721A1 (en) * | 2008-11-26 | 2010-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test probe structure |
-
2010
- 2010-11-12 TW TW99139083A patent/TW201219806A/en unknown
- 2010-11-23 CN CN2010105628377A patent/CN102466777A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089819A (en) * | 1988-10-05 | 1992-02-18 | Hitachi, Ltd. | Parallel-to-serial signal converting apparatus and image displaying system using the same |
| CN1591694A (en) * | 2003-08-25 | 2005-03-09 | 三星电子株式会社 | Apparatus and method for testing semiconductor memory devices |
| CN1928753A (en) * | 2005-07-20 | 2007-03-14 | 阿尔特拉公司 | Clock circuitry for programmable logic devices |
| CN101369000A (en) * | 2008-09-12 | 2009-02-18 | 北京中星微电子有限公司 | Digital chip testing method and testing system |
| US20100127721A1 (en) * | 2008-11-26 | 2010-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test probe structure |
| CN101446843A (en) * | 2008-12-30 | 2009-06-03 | 北京中星微电子有限公司 | High-frequency clock generator, clock frequency conversion method, and chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106959411A (en) * | 2017-03-29 | 2017-07-18 | 安徽云塔电子科技有限公司 | A kind of method of testing of integrated circuit and integrated circuit |
| CN108957300A (en) * | 2018-09-03 | 2018-12-07 | 长鑫存储技术有限公司 | Wafer test apparatus and test method |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201219806A (en) | 2012-05-16 |
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Application publication date: 20120523 |