201219806 六、發明說明： 【發明所屬之技術領域】 本發明係與積體電路測試(integrate(j circuit test)有關， 特別是關於一種積體電路測試裝置，透過將多個平行輸入的 低頻邏輯訊號轉換為序列輸出的高頻邏輯訊號之方式大幅 增加其輸㈣率’故㈣虹賴率較高職體電路。 【先前技術】201219806 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an integrated circuit test (integrate (j circuit test), in particular to an integrated circuit test device through a plurality of parallel input low frequency logic signals The way of converting high-frequency logic signals into serial output greatly increases the rate of its input (four), so the (four) rainbow rate is higher in the higher-level circuit. [Prior Art]
近年來’隨著電子科技不斷地進步，親電路相關 二蓬勃地發展’其中積體電路測試產業即為—例。一般而 二认用以對频電料_朗健電路職裝置均有其 兩輸出頻率之限制，因而造成實際應用時之不便。、 出頻設ΐ:積體電路測試裝置所具有的最高輪 工作頻Γρ該麵電關财置最高僅能針對 若積體電路的路進行測試的工作，因此， 裝置即無法對其進行二，或· ’該積體電路剛試 夠測試高頻的積體I路而^頻率不的今日，為了能 j =嘯電路的測試成本大幅增加，不符合生: 皿亦導致積體電路之市場競爭力降低-生產 【發明内容】 問題因此树明提出—種積體電路測試裝置，以解決上述 3 201219806 根據本發明之第一具體實施例為一種積體電路測試裝 置。於此實施例中’積體電路測試裝置包含複數個輸入端、 轉換模組及輸出端。轉換模組麵接該等輸入端。輸出端麵接 轉換模組。輸入端係用以分別平行地輸入複數個低頻訊號。 轉換模組係用以將該等低頻訊號轉換為複數個高頻訊號。輸 出端係用以序列地輸出該等高頻訊號。該等高頻訊號的輸出 頻率與該等低頻訊號的輸入頻率之比值係和該等輸入端之 數目有關。 於實際應用中，若輸入該等輸入端之該等低頻訊號的輸 入頻率為F ’且該等輸入端之數目為n，則該輸出端序列輸 出之該等南頻訊號的輸入頻率為(F*n)，η為正整數。 轉換模組可包含有複數個輸入邏輯元件及輸出邏輯元 件’該等輸入邏輯元件中之每一輸入邏輯元件係分別對應並 耦接至該等輸入端，輸出邏輯元件係對應並耦接至輸出端。 該等輸入邏輯元件中之每一輸入邏輯元件及輸出邏輯元件 可以是及(AND)閘元件、反及(NAND)閘元件、或(〇R)閘元 件、反或(NOR)閘元件、互斥(x〇R)閘元件或反互斥(：?〇^〇幻 閘元件。 轉換模組可以由元件可编程邏輯閘陣列（朽别 Programmable Gate Array，FPGA)或特定應用積體電路 (Application Specific Integrated Circuit，ASIC)構成。輸出端可 依照特定順序序列地輸出該等高頻訊號，其中，特定順序可 以疋機產生或與该荨輸入端之排列順序有關。，、— 相較於先前技術，根據本發明之積體電路測試裝置係採 用多個輸入端與單一輸出端之架構，透過將多個平行輪 201219806 訊號轉換為序列輸出的高頻邏輯訊號之方式’使得 ==裝置的輸出頻率能夠倍增，故能夠測上it :，_以=::路，故可有效地節省積體電路的測試成 不稭以挺升積體電路之市場競爭力。 人 盥盆ΐ外^於龍電路職裝置之輸出鮮的增加倍數係 入端的數目成正比關係，因此，積體電路測試人員可 =實 =試時之需求調整㈣電路測試裝置之輪入= ❿ 赫電輯職置的獅鮮㈣高於積體 的作頻率即可，亦可增加積體電路測試時的彈性。 本發明之優點與精神可以藉由以下的發明詳述及 所附圖式得到進一步的瞭解。 【實施方式】 根據本發明之一具體實施例為一種積體電路測試褒 置。顧名思義’積體電㈣試裝置仙崎對韻電路進行 各種不同的測試工作。 ，際亡’受測試的積體電路之種類及形式並無特定之限 ^ ’可以疋類比(analog)積體電路、數位(dig㈣積體電路、 無’線通-戒(wlreless c〇mmunicati〇n)積體電路、特殊應用積體 電路(ASIC)或其餘意的積體電路。 至於積體電路測試裝置對於積體電路所進行的測試項 目亦無特定之限制’可以是耐電壓測試、耐電流測試或其它 積體電路相關的電性測試項目。 5月參照圖1，圖1係繪示此實施例之積體電路測試裝置 201219806 的功能方塊圖。如圖1所示，積體電路測試裝置1包含第一 輸入端11、第二輸入端12、轉換模組13及輸出端14。其 中’第一輸入端11及第二輸入端12耦接至轉換模組13， 並且轉換模組13耦接至輸出端14。 值得注意的是，雖然此實施例中之積體電路測試裝置1 僅包含兩個輸入端，但實際上輸入端的數目亦可以是三個、 四個甚至更多個，端視積體電路測試時之需求而定，並無特 定之限制。 第一輸入端11及第二輸入端12係用以分別平行地輸入 第一低頻訊號LF1及第二低頻訊號LF2。也就是說，第一低 頻訊號LF1係透過第一輸入端11輸入至轉換模組13，而第 二低頻訊號LF2則係透過第二輸入端12輸入至轉換模組 13。 接著’轉換模組13即會將第一低頻訊號LF1及第二低 頻訊號LF2轉換為第一高頻訊號HF1及第二高頻訊號 HF2’並將轉換後的第一高頻訊號HF1及第二高頻訊號HF2 傳送至輸出端14。 於實際應用中’轉換模組13可以由元件可編程邏輯閘 陣列(Field Programmable Gate Array, FPGA)或特定應用積體 電路(Application Specific Integrated Circuit，ASIC)構成，但不 以此為限。 於此實施例中’由於積體電路測試裝置1包含兩個輸入 端（第一輸入端11及第二輸入端12)及一個輸出端14,因此， 如圖2所示，轉換模組13相對應地包含邏輯元件13〇，並 且邏輯元件130具有兩個輸入接腳(第一輸入接腳Pini及第 201219806 二輸入端Pm)及一個輸出接腳P〇ut。其中，第一輸入接腳Pini 係對應並耦接至第一輸入端11;第二輸入端Pin2係對應並耦 接至第二輸入端12 ;輸出接腳對應並耦接至輸出端 14。 於實際應用中，上述的邏輯元件13〇可以是及(AND)閘 元件、反及(NAND)閘元件、或(0R)閘元件、反或(N〇R)閘 元件、互斥(XOR)閘元件或反互斥(XN〇R)閘元件，但不以 此為限。 如圖3及圖4所示，於另一實施例中，假設積體電路測 試裝置2包含四個輸入端21〜24及一個輸出端25，則其轉 換模組26將會相對應地包含第一輸入邏輯元件260、第二 輸入邏輯元件262及輸出邏輯元件264。其中，輸入端21 及22係對應並耦接至第一輸入邏輯元件26〇 ;輸入端23及 24係對應並耦接至第二輸入邏輯元件262 ;第一輸入邏輯元 件260及第二輸入邏輯元件262係耦接至輸出邏輯元件 264 ;輸出邏輯元件264係對應並耦接至輸出端25。 於實際應用中’上述的第一輸入邏輯元件260、第二輸 入邏輯元件262及輸出邏輯元件264可以是及(AND)閘元 件、反及(NAND)閘元件、或(OR)閘元件、反或(NOR)閘元 件、互斥(XOR)閘元件或反互斥(XN0R)閘元件，但不以此 為限。 回到圖1 ’值得注意的是，由於積體電路測試裝置1僅 包含單一個輸出端14，而此一輸出端14並無法同時輸出第 面頻號HF1及第二南頻訊號HF2，因此，輸出端14將 會序列地輸出第一高頻訊號HF1及第二高頻訊號HF2。 201219806 至於輸出端14序列地輸出第一高頻訊號HF1及第二高 頻號HF2的特定順序並無任何限制，特定順序可以是隨 機產生或與第一輸入端11及第二輸入端12之排列順序有 關。也就是說，以此實施例為例，輸出端14可以先輸出第 -高頻訊號HF1後，再輸出第二高頻訊號肥，抑或輸出 端14先輸出第二高頻訊號HF2後，再輸出第—高頻訊號 HF1 ’端視實際測試時之需求而定。 值得注意的是，假設本發明之積體電路測試裝置所包含 之輸入端的數目為η ’ n為正紐，並絲頻峨平行地輸 入積體電路測試裝置的輸人頻率為&，積體電路測試裝置序 列地輸出該等高頻訊號的輸出頻率為f⑽，則輸出頻率 fin * η。 :頻率將會是故輸 裝置2包含四個輸入端212=Γ— 路測試裝置2的輸出頻率匕-亦即積體電 路測試裝置包含不同數目的頻率的四倍。當積體電 此不另行贅述。 哺从時’亦可依此類推，故於 用多賴置係採 低頻邏輯訊雜換為相輪多個平行輸入的 積體電路測試裝置的輸出輯，號之方式，使得 高工作鮮的賴麵3二触5緣_試具有較 本，藉以提升積體電路之市場競積體電路的測試成 201219806 =實之體需電__路測試裝置::= 鄉:頻:=二==體 藉由以上較佳具體實施例之詳 發明之特徵與精神，而並非以上二 ==發明之梅以限制。相反地，其目的是 之專及具相等性的安排於本發明所欲申請 201219806 【圖式簡單說明】 圖1係繪示根據本發明之一具體實施例之積體電路測 試裝置的功能方塊圖。 圖2係繪示圖1中之轉換模組包含邏輯元件之示意圖。 圖3係繪示根據本發明之另一具體實施例之積體電路測 試裝置的功能方塊圖。 圖4係繪示圖3中之轉換模組包含第一輸入邏輯元件、 第二輸入邏輯元件及輸出邏輯元件之示意圖。 201219806 【主要元件符號說明】 1、2:積體電路測試裝置 11 :第一輸入端 ' 13、26 :轉換模組 • LF1 :第一低頻訊號 HF1 :第一高頻訊號 130 :邏輯元件 • Pin2 :第二輸入端 21〜24 :輸入端 260 :第一輸入邏輯元件 12 :第二輸入端 14、25 :輸出端 LF2 :第二低頻訊號 HF2 :第二高頻訊號 Pini :第一輸入接腳 P〇Ut ·輸出接腳 264 :輸出邏輯元件 262 :第二輸入邏輯元件In recent years, with the continuous advancement of electronic technology, the development of pro-circuits has been vigorously developed. In general, the two are used to limit the frequency of the frequency _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The frequency setting is: the highest wheel operating frequency of the integrated circuit test device. The maximum power of the surface can only be tested for the circuit of the integrated circuit. Therefore, the device cannot perform the second. Or · 'The integrated circuit has just tried to test the high-frequency integrated I path and the frequency is not today. In order to increase the test cost of the j = whistle circuit, it does not meet the raw: the dish also leads to the market competition of the integrated circuit. REDUCTION - PRODUCTION [Disclosure] The problem is therefore to provide an integrated circuit test apparatus to solve the above-mentioned 3 201219806. According to a first embodiment of the present invention, an integrated circuit test apparatus is provided. In this embodiment, the integrated circuit test device includes a plurality of input terminals, a conversion module, and an output terminal. The conversion module is connected to the inputs. The output end is connected to the conversion module. The input terminal is used to input a plurality of low frequency signals in parallel respectively. The conversion module is configured to convert the low frequency signals into a plurality of high frequency signals. The output is used to serially output the high frequency signals. The ratio of the output frequency of the high frequency signals to the input frequency of the low frequency signals is related to the number of such inputs. In an actual application, if the input frequency of the low frequency signals input to the input terminals is F′ and the number of the input terminals is n, the input frequency of the south frequency signals output by the output terminal sequence is (F *n), η is a positive integer. The conversion module can include a plurality of input logic elements and an output logic element. Each of the input logic elements is respectively corresponding to and coupled to the input ends, and the output logic elements are correspondingly coupled to the output. end. Each of the input logic elements and the output logic elements may be an AND gate element, a NAND gate element, or a (〇R) gate element, a reverse (NOR) gate element, and each other. Reject (x〇R) gate elements or reverse mutex (:?〇^〇 闸 元件. The conversion module can be programmed by a programmable logic gate array (FPGA) or a specific application integrated circuit (Application) Specific Integrated Circuit (ASIC). The output terminal can sequentially output the high frequency signals in a specific order, wherein the specific order can be generated or related to the order of the input terminals. , - Compared with the prior art The integrated circuit test device according to the present invention adopts a structure of a plurality of input terminals and a single output terminal, and converts a plurality of parallel wheels 201219806 signals into a sequence output high frequency logic signal to make == the output frequency of the device It can be multiplied, so it can measure it :, _ with =:: road, so it can effectively save the test of the integrated circuit to become the market competitiveness of the integrated circuit. Job The output increase is slightly proportional to the number of input terminals. Therefore, the tester of the integrated circuit can = the actual demand adjustment of the test (4) the turn of the circuit test device = 狮 the lion fresh (four) high The frequency of the integrated body can be increased, and the elasticity of the integrated circuit test can also be increased. The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings. One embodiment of the invention is an integrated circuit test device. As the name suggests, the integrated body (four) test device, the Xianqi circuit, performs various test tests. The type and form of the integrated circuit under test are not The specific limit ^ 'can be analog analog circuit, digital (dig) circuit, no 'wire-to-wire (wlreless c〇mmunicati〇n) integrated circuit, special application integrated circuit (ASIC) or the rest The integrated circuit of the integrated circuit has no specific limitation on the test items of the integrated circuit test device. It can be a voltage withstand test, a current withstand test or other integrated circuits. 1. The functional block diagram of the integrated circuit test device 201219806 of this embodiment is shown in Fig. 1. As shown in Fig. 1, the integrated circuit test device 1 includes a first input terminal 11, The input terminal 12, the conversion module 13 and the output terminal 14 are coupled to the conversion module 13 and the conversion module 13 is coupled to the output terminal 14. Yes, although the integrated circuit testing device 1 in this embodiment only includes two inputs, the number of input terminals may actually be three, four or even more, which is required for the test of the integrated circuit. There are no specific restrictions. The first input terminal 11 and the second input terminal 12 are configured to input the first low frequency signal LF1 and the second low frequency signal LF2 in parallel, respectively. That is, the first low frequency signal LF1 is input to the conversion module 13 through the first input terminal 11, and the second low frequency signal LF2 is input to the conversion module 13 through the second input terminal 12. Then, the conversion module 13 converts the first low frequency signal LF1 and the second low frequency signal LF2 into the first high frequency signal HF1 and the second high frequency signal HF2' and converts the converted first high frequency signal HF1 and the second The high frequency signal HF2 is transmitted to the output terminal 14. In the actual application, the conversion module 13 may be composed of a component programmable gate array (FPGA) or an application specific integrated circuit (ASIC), but is not limited thereto. In this embodiment, the integrated circuit test device 1 includes two input terminals (the first input terminal 11 and the second input terminal 12) and an output terminal 14. Therefore, as shown in FIG. 2, the conversion module 13 phase Correspondingly, the logic element 13A is included, and the logic element 130 has two input pins (the first input pin Pini and the 201219806 two-input Pm) and one output pin P〇ut. The first input pin Pini is correspondingly coupled to the first input end 11; the second input end Pin2 is correspondingly coupled to the second input end 12; the output pin is correspondingly coupled to the output end 14. In practical applications, the above logic element 13A may be an AND gate element, a NAND gate element, or a (0R) gate element, an inverse (N〇R) gate element, and a mutual exclusion (XOR). Gate element or anti-mutual (XN〇R) gate element, but not limited to this. As shown in FIG. 3 and FIG. 4, in another embodiment, if the integrated circuit testing device 2 includes four input terminals 21 to 24 and one output terminal 25, the conversion module 26 will correspondingly include An input logic element 260, a second input logic element 262, and an output logic element 264. The input terminals 21 and 22 are correspondingly coupled to the first input logic element 26; the input terminals 23 and 24 are correspondingly coupled to the second input logic element 262; the first input logic element 260 and the second input logic The component 262 is coupled to the output logic component 264; the output logic component 264 is corresponding to and coupled to the output terminal 25. In practical applications, the first input logic element 260, the second input logic element 262, and the output logic element 264 may be an AND gate element, a (NAND) gate element, or an (OR) gate element, Or (NOR) gate element, mutual exclusion (XOR) gate element or anti-mutation (XN0R) gate element, but not limited to this. Returning to FIG. 1 ' It is worth noting that since the integrated circuit test device 1 only includes a single output terminal 14, the output terminal 14 cannot simultaneously output the first surface frequency number HF1 and the second south frequency signal HF2. The output terminal 14 will sequentially output the first high frequency signal HF1 and the second high frequency signal HF2. 201219806 There is no limitation on the specific order in which the output terminal 14 sequentially outputs the first high frequency signal HF1 and the second high frequency number HF2, and the specific order may be randomly generated or arranged with the first input terminal 11 and the second input terminal 12. The order is related. That is to say, in this embodiment, the output terminal 14 may output the first high frequency signal HF1 first, and then output the second high frequency signal fertilizer, or the output terminal 14 outputs the second high frequency signal HF2 first, and then output. The first - high frequency signal HF1 ' depends on the actual test requirements. It is to be noted that it is assumed that the number of input terminals included in the integrated circuit test apparatus of the present invention is η ' n is a positive button, and the input frequency of the integrated circuit test device is input in parallel with the wire frequency 峨 parallel, & The circuit test device sequentially outputs the output frequency of the high frequency signals as f(10), and outputs the frequency fin* η. The frequency will be the output device 2 containing four inputs 212 = Γ - the output frequency of the test device 2 - that is, the integrated circuit test device contains four times the different number of frequencies. When the body is charged, this will not be repeated. When feeding, it can be used in the same way. Therefore, the output of the integrated circuit test device of the parallel input of the phase wheel is replaced by the low frequency logic signal, which makes the high work fresh surface. 3 two touch 5 edge _ test has a more than this, in order to improve the market competing circuit of the integrated circuit test into 201219806 = real body power __ road test device:: = township: frequency: = two = = body loan The features and spirit of the detailed invention of the above preferred embodiments are not limited by the above two == invention. On the contrary, the purpose of the present invention is to apply for the equivalent of the present invention. The application of the present invention is in the form of a functional block diagram of the integrated circuit testing device according to an embodiment of the present invention. . FIG. 2 is a schematic diagram showing the conversion module of FIG. 1 including logic elements. Fig. 3 is a functional block diagram showing an integrated circuit test apparatus according to another embodiment of the present invention. 4 is a schematic diagram of the conversion module of FIG. 3 including a first input logic element, a second input logic element, and an output logic element. 201219806 [Explanation of main component symbols] 1, 2: Integrated circuit test device 11: First input terminal '13, 26: Conversion module ・ LF1: First low frequency signal HF1: First high frequency signal 130: Logic element • Pin2 : second input terminals 21 to 24: input terminal 260: first input logic element 12: second input terminal 14, 25: output terminal LF2: second low frequency signal HF2: second high frequency signal Pini: first input pin P〇Ut · Output pin 264: Output logic element 262: Second input logic element