CN108957300A - Wafer test apparatus and test method - Google Patents
Wafer test apparatus and test method Download PDFInfo
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- CN108957300A CN108957300A CN201811019070.6A CN201811019070A CN108957300A CN 108957300 A CN108957300 A CN 108957300A CN 201811019070 A CN201811019070 A CN 201811019070A CN 108957300 A CN108957300 A CN 108957300A
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- 238000012360 testing method Methods 0.000 title claims abstract description 49
- 238000010998 test method Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000872 buffer Substances 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000003786 synthesis reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The disclosure is directed to a kind of wafer test apparatus and method, which includes: interface card, and the interface card includes: signal synthetic apparatus, multiple first interfaces and second interface；The first signal that signal synthetic apparatus is used to issue multiple detectors synthesizes second signal, and the second signal is sent to wafer socket；The input terminal of the signal synthetic apparatus is arranged in multiple first interfaces, for connecting the multiple detector；The output end of the signal synthetic apparatus is arranged in second interface, for connecting wafer socket.High-frequency second signal is synthesized by low-frequency first signal that signal synthetic apparatus exports multiple detectors, multiple low frequency detectors, which are utilized, realizes the high-frequency test of chip.
Description
Technical field
This disclosure relates to chip detection technique field, in particular to a kind of apparatus for testing chip and wafer sort side
Method.
Background technique
It is widely used in each adhesive integrated circuit, usually needs before the use with progress, chip with the development of technology
Chip is tested.In built-in storage, the requirement of the speed of service of built-in storage chip is higher and higher, its is right accordingly
The service speed requirement of chip is also higher and higher, also higher and higher to the frequency requirement of test device in test.
Currently, tester used in production, frequency have been unable to satisfy the high-frequency test demand of chip.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The disclosure is designed to provide a kind of apparatus for testing chip and chip detecting method, and then at least to a certain degree
On overcome since tester frequency is low in the related technology, can not to chip carry out high-frequency test the problem of.
According to one aspect of the disclosure, a kind of wafer test apparatus is provided, the wafer test apparatus includes:
Interface card, the interface card include:
Signal synthetic apparatus, the first signal for issuing multiple detectors synthesize second signal, and by described second
Signal is sent to wafer socket；
The input terminal of the signal synthetic apparatus is arranged in multiple first interfaces, for connecting the multiple detector；
The output end of the signal synthetic apparatus is arranged in, for connecting wafer socket in second interface.
According to an embodiment of the disclosure, the frequency of the second signal is higher than the frequency of first signal.
According to an embodiment of the disclosure, there is preset phase difference between multiple first signals.
According to an embodiment of the disclosure, the wafer test apparatus further include:
Multiple detectors are correspondingly connected with multiple first interfaces respectively, for exporting first signal.
According to an embodiment of the disclosure, the wafer test apparatus further include:
Controller is connected with multiple detectors, for controlling the first signal of the detector output, so that multiple
There is preset phase difference between first signal.
According to an embodiment of the disclosure, the signal synthetic apparatus includes:
Multiple buffers, wherein the corresponding first interface of the input terminal of each buffer, the output end of multiple buffers
Connection, for the first signal described in multichannel to be synthesized the second signal.
According to an embodiment of the disclosure, the signal synthetic apparatus includes:
Or door, the first signal issued for receiving multiple detectors, and multiple first signals are synthesized the
The second signal is sent to the wafer socket by binary signal.
According to an embodiment of the disclosure, the signal synthetic apparatus includes:
Adder, first signal issued for receiving multiple detectors, and by multiple first signals
The second signal is synthesized, the second signal is sent to the wafer socket.
According to an embodiment of the disclosure, the wafer test apparatus further include:
Wafer socket is connected with the second interface, for installing chip.
According to another aspect of the disclosure, a kind of chip detecting method is provided, comprising:
Receive multiple first signals of multiple detector outputs；
Multiple first signals are synthesized into second signal；
The second signal is transmitted to wafer socket and carries out wafer sort.
According to an embodiment of the disclosure, the frequency of the second signal is higher than the frequency of first signal.
According to an embodiment of the disclosure, have between multiple first signals of the multiple detector output pre-
If phase difference.
According to an embodiment of the disclosure, the multiple detectors of reception are exported before multiple first signals, further includes:
The multiple detector exports the first signal respectively；
According to an embodiment of the disclosure, the multiple detector exports the first signal respectively, comprising:
Multiple detectors are controlled by controller and export the first signal respectively, so that having between multiple first signals
Preset phase difference.
The wafer test apparatus that the disclosure provides, the first interface on interface card connect multiple detectors, are closed by signal
Second signal is synthesized at the first signal that device exports multiple detectors, that is, passes through multiple low-frequency first signal synthesis one
A high-frequency second signal, meets frequency needs when chip testing；Multiple detectors are connected by signal synthetic apparatus
It connects, the high-frequency test that multiple low frequency detectors complete chip is utilized, has saved testing cost.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is a kind of schematic diagram for wafer test apparatus that disclosure illustrative examples provide.
Fig. 2 is the signal waveform schematic diagram that disclosure illustrative examples provide.
Fig. 3 is a kind of schematic diagram for signal synthetic apparatus that disclosure illustrative examples provide.
Fig. 4 is a kind of flow chart for chip detecting method that disclosure illustrative examples provide.
Fig. 5 is the flow chart for another chip detecting method that disclosure illustrative examples provide.
In figure:
100, detector；200, interface card；210, signal synthetic apparatus；211, buffer；220, first interface；230,
Two interfaces；300, wafer socket.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the present invention will
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Identical attached drawing in figure
Label indicates same or similar structure, thus the detailed description that will omit them.
Although the term of relativity, such as "upper" "lower" is used to describe a component of icon for another in this specification
The relativeness of one component, but these terms are in this manual merely for convenient, for example, with reference to the accompanying drawings described in show
The direction of example.It is appreciated that, if making it turn upside down the device overturning of icon, the component described in "upper" will
As the component in "lower".When certain structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structures
On, or refer to that certain structure is " direct " and be arranged in other structures, or refer to that certain structure is arranged by the way that another structure is " indirect " in other knots
On structure.
Term "one", " one ", "the", " described " and "at least one" be to indicate that there are one or more elements/groups
At part/etc.；Term " comprising " and " having " is to indicate the open meaning being included and refer in addition to listing
Element/component part/also may be present except waiting other element/component part/etc.；Term " first ", " second " and " third "
It is used as to mark Deng only and use, be not the quantity limitation to its object.
When wafer sort, due to the speed of service of chip require it is higher and higher, accordingly in order to meet the test need of chip
It asks, it is also higher and higher to the frequency requirement of wafer test apparatus.Low frequency detector has been unable to satisfy the high-frequency test demand of chip.
A kind of wafer test apparatus is provided firstly in this example embodiment, as shown in Figure 1, the wafer test apparatus packet
Include: interface card 200, the interface card 200 include: multiple first interfaces 220, signal synthetic apparatus 210 and second interface 230；
The first signal that signal synthetic apparatus 210 is used to issue multiple detectors 100 synthesizes second signal, and will be described
Second signal is sent to wafer socket 300；The input terminal of the signal synthetic apparatus 210 is arranged in multiple first interfaces 220, uses
In the multiple detectors 100 of connection；The output end of the signal synthetic apparatus 210 is arranged in, for connecting in second interface 230
Connect wafer socket 300；Wherein, the frequency of the second signal is higher than the frequency of first signal.
The wafer test apparatus that the embodiment of the present disclosure provides, the first interface 220 on interface card 200 connect multiple detectors
100, second signal is synthesized by the first signal that signal synthetic apparatus 210 exports multiple detectors 100, i.e., by multiple low
First signal of frequency synthesizes a high-frequency second signal, to meet frequency needs when chip testing；It is closed by signal
Multiple detectors 100 are connected at device 210, multiple completions of low frequency detectors 100 are utilized to the high-frequency test of chip, save
Testing cost.
It, can be multiple the in order to guarantee that the first signal that multiple detectors 100 export high-frequency signal in synthesis is avoided the peak hour
When one signal exports, so that having preset phase difference between multiple first signals.Multiple first signals can be peak value and week
Phase identical pulse signal, at this time by different signal forming times being controlled, so that multiple when multiple first signals occur
There is preset phase difference between first signal.
It is exemplary, the waveform of two first signals S1 and S2 as shown in Fig. 2, S2 and S1 phase phase difference half period T1,
By S1 and S2 input signal synthesizer 210, synthesis second signal S3 is obtained.It can be obtained by Fig. 2, the frequency of second signal S3 is
Twice of first signal S1 and S2.
Further, the wafer test apparatus that the embodiment of the present disclosure provides further includes multiple detectors 100, multiple detectors
100 are correspondingly connected with multiple first interfaces 220 respectively, for exporting the first signal.
Wherein, detector 100 can be ready-made low-frequency detector 100, in actual production, previous used
Detector 100 is eliminated often due to the frequency of its output signal is unable to satisfy the growing frequency needs of chip, in turn results in
The waste of resource.The interface card 200 provided by the embodiment of the present disclosure, multiple low-frequency detectors 100 is connected, and will be more
A low-frequency first signal synthesizes high-frequency second signal.
Multiple first interfaces 220 are provided on interface card 200, detector 100 can pass through wired connection and first interface
220 connections, and the first signal is sent to signal synthetic apparatus 210 by first interface 220.Certainly in practical applications, inspection
Surveying instrument 100 can also be connected by way of wireless connection with first interface 220, and the embodiment of the present disclosure does not do specific limit to this
It is fixed.It should be noted that first interface 220 can be entity connection jaws or other modes for detector 100 and signal
The device of set composite connection.
Further, the wafer test apparatus that the embodiment of the present disclosure provides, further includes controller, controller and multiple described
Detector 100 connects, for controlling the first signal of the output of detector 100, so that having between multiple first signals preset
Phase difference.
Wherein, multiple delayers can be set in controller, detector 100 is controlled by delayer and exports the first signal.
For example, the first signal and the second signal as shown in Figure 2, the first signal S1 and S2 passes through a detector 100 respectively and exports, control
Device and two detectors 100 connect.Wherein, the detector 100 of the delayer control output S2 signal in controller is delayed half
Period, so that the first signal S1 and S2 has the phase difference of half period.
In the first feasible embodiment that the disclosure provides, as shown in figure 3, signal synthetic apparatus 210 can wrap
It includes: multiple buffers 211, wherein the corresponding first interface 220 of the input terminal of each buffer 211, multiple buffers 211
Output end connection, for the first signal of multichannel to be synthesized second signal.Detector 100 and first interface 220 connect, output
First signal.Multiple detectors 100 export the first signal all the way respectively, and the first signal inputs in a buffer 211 all the way, more
The output end of a buffer 211 links together, and is overlapped to input voltage signal, the voltage that multiple buffers 211 export
Signal synthesizes second signal.The input terminal of multiple buffers 211 can connect to second interface 230, synthesize in second interface 230
Second signal, and second signal is sent to wafer socket 300.Due to having preset phase difference between multiple first signals,
High level is alternately present, therefore the second signal frequency synthesized is higher than the first signal.It has the advantages of simple structure and easy realization.
Exemplary, the high level of the first signal S1 and S2 is Vih, low level Vil, by adjusting in buffer 211
Resistance can make the high level of second signal SThe low level of second signal S is Vil.Pass through multiple buffers
The first signal that the 211 multiple detectors 100 of synthesis export, structure is simple, easy to implement, and the high frequency that can be effectively reduced chip is surveyed
Try cost.
In second of feasible embodiment that the disclosure provides, signal synthetic apparatus 210 may include: or door, should
Or door is used to receive the first signal that multiple detectors 100 issue by multiple first interfaces 220, and multiple first signals are closed
At second signal, second signal is sent to by wafer socket 300 by second interface 230.
Wherein, the input terminal of OR circuit can be connected with first interface 220, and first interface 220 is connected with detector
100, multiple 100 the first signals of output multi-channel of detector, the first signal of multichannel has scheduled phase difference, the table on waveform
Will not now occur simultaneously for high level, by or multiple first signals of goalkeeper synthesize second signals, multiple first signals are low
When level, second signal exports low level, remaining exports high level.Pass through the phase between OR circuit and multiple first signals
Potential difference, so that the second signal frequency of synthesis improves.The output end of OR circuit can be connected with second interface 230, and second connects
Mouth 230 is connected with wafer socket 300, and second signal is transferred to wafer socket 300 by second interface 230.
In the third achievable embodiment that the disclosure provides, signal synthetic apparatus 210 includes: adder；It should
Adder is used to receive the first signal that multiple detectors 100 issue by multiple first interfaces 220, and by multiple first signals
The second signal is synthesized, the second signal is sent to by wafer socket 300 by second interface 230.
Wherein, the input terminal of adder can be connected with first interface 220, and first interface 220 and detector 100 connect,
Detector 100 exports the first signal, and multiple first signals synthesize a second signal by adder.The output end of adder and
Second interface 230 connects, and second interface 230 is connected with wafer socket 300, is transferred to second signal by second interface 230
Wafer socket 300.Multiple first signals have predetermined phase poor, and the high level which obtains multiple first signals exists
The same time uniquely occurs, i.e., at most only one is in output high level in multiple first signals of same time.In addition electricity
It, can be by adjusting the resistance in circuit, so that operation result is appropriate for wafer sort during road transport is calculated.
Further, the wafer test apparatus that the embodiment of the present disclosure provides further include: wafer socket 300, wafer socket 300
It is connected with second interface 230, the socket for installing chip is provided on wafer socket 300.It, can be with when carrying out wafer sort
Chip to be tested is mounted in the socket, is detected.Wafer socket 300 may be mounted on tester table.
A kind of chip detecting method is additionally provided in this example embodiment, as shown in figure 4, the chip detecting method, packet
Include following steps:
Step S410 receives multiple first signals of multiple detector outputs；
Multiple first signals are synthesized second signal, wherein the frequency of the second signal is higher than institute by step S420
State the frequency of the first signal；
The second signal is transmitted to wafer socket and carries out wafer sort by step S430.
The chip detecting method that the embodiment of the present disclosure provides, is exported multiple detectors 100 by signal synthetic apparatus 210
Low-frequency first signal synthesizes a high-frequency second signal, to meet frequency needs when chip testing；Simultaneously because
Multiple low frequency detectors 100 are utilized to complete to have saved testing cost to the high-frequency test of chip.
Further, as shown in figure 5, the chip detecting method that the embodiment of the present disclosure provides also wraps before step S410
Include: step S440, multiple detectors 100 export the first signal respectively.
The chip detecting method provided below the embodiment of the present disclosure is described in detail:
In step S440, multiple detectors 100 export the first signal respectively.
Multiple detectors 100 can be ready-made low-frequency detector 100, in actual production, previous used
Detector 100 is eliminated often due to the frequency of its output signal is unable to satisfy the growing frequency needs of chip, in turn results in
The waste of resource.The first signal that multiple detectors 100 export can be period and identical pulse voltage signal, and multiple
There is preset phase difference, which obtains the high level of multiple first signals in same a period of time between pulse voltage signal
Between uniquely occur, i.e., in multiple first signals of same time at most only one in output high level.Controller can be passed through
In delayer control detector 100 export the first signal time so that between multiple first signals have preset phase
Difference.
In step S410, it can receive multiple detectors 100 and export multiple first signals.Detector 100 passes through first
Interface 220 and signal synthetic apparatus 210 connect, and signal synthetic apparatus 210 receives the first signal by first interface 220.
In the step s 420, multiple first signals are synthesized into second signal, wherein the frequency of the second signal is high
In the frequency of first signal.
Synthesizing multiple first signals can be by any one in multiple buffers 211 or door or adder.Due to
Between multiple first signals have preset phase difference, by signal synthetic apparatus 210 synthesis after, the second signal of output
Frequency is higher than the frequency of the first signal.
In step S430, the second signal can be transmitted to wafer socket and carry out wafer sort.
The output end of signal synthetic apparatus 210 can be connected with second interface 230, second interface 230 and wafer socket 300
Second signal can be sent to wafer socket 300 by second interface 230 by connection, signal synthetic apparatus 210.Wafer socket
Chip to be detected is installed, high frequency second signal can satisfy requirement of the chip to be detected to detection frequency on 300.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by appended
Claim is pointed out.
Claims (14)
1. a kind of wafer test apparatus, which is characterized in that the wafer test apparatus includes:
Interface card, the interface card include:
Signal synthetic apparatus, the first signal for issuing multiple detectors synthesize second signal, and by the second signal
It is sent to wafer socket；
The input terminal of the signal synthetic apparatus is arranged in multiple first interfaces, for connecting the multiple detector；
The output end of the signal synthetic apparatus is arranged in, for connecting wafer socket in second interface.
2. wafer test apparatus as described in claim 1, which is characterized in that the frequency of the second signal is higher than described first
The frequency of signal.
3. wafer test apparatus as described in claim 1, which is characterized in that have between multiple first signals preset
Phase difference.
4. wafer test apparatus as claimed in claim 3, which is characterized in that the wafer test apparatus further include:
Multiple detectors are correspondingly connected with multiple first interfaces respectively, for exporting first signal.
5. wafer test apparatus as claimed in claim 4, which is characterized in that the wafer test apparatus further include:
Controller is connected with multiple detectors, for controlling the first signal of the detector output, so that multiple described
There is preset phase difference between first signal.
6. wafer test apparatus as described in claim 1, which is characterized in that the signal synthetic apparatus includes:
Multiple buffers, wherein the corresponding first interface of the input terminal of each buffer, the output end of multiple buffers connect
It connects, for the first signal described in multichannel to be synthesized the second signal.
7. wafer test apparatus as described in claim 1, which is characterized in that the signal synthetic apparatus includes:
Or multiple first signals are synthesized second signal by door, the first signal issued for receiving multiple detectors,
And the second signal is sent to the wafer socket.
8. wafer test apparatus as described in claim 1, which is characterized in that the signal synthetic apparatus includes:
Multiple first signals are synthesized institute by adder, first signal issued for receiving multiple detectors
Second signal is stated, and the second signal is sent to the wafer socket.
9. wafer test apparatus as described in claim 1, which is characterized in that the wafer test apparatus further include:
Wafer socket is connected with the second interface, for installing chip.
10. a kind of chip detecting method of wafer test apparatus characterized by comprising
Receive multiple first signals of multiple detector outputs；
Multiple first signals are synthesized into second signal；
The second signal is transmitted to wafer socket and carries out wafer sort.
11. chip detecting method as claimed in claim 10, which is characterized in that the frequency of the second signal is higher than described the
The frequency of one signal.
12. chip detecting method as claimed in claim 10, which is characterized in that the multiple detector exports multiple described
There is preset phase difference between first signal.
13. chip detecting method as claimed in claim 10, which is characterized in that described to receive multiple detectors output multiple the
Before one signal, further includes:
The multiple detector exports the first signal respectively.
14. chip detecting method as claimed in claim 13, which is characterized in that the multiple detector exports the first letter respectively
Number, comprising:
Multiple detectors are controlled by controller and export the first signal respectively, so that having between multiple first signals default
Phase difference.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811019070.6A CN108957300A (en) | 2018-09-03 | 2018-09-03 | Wafer test apparatus and test method |
| PCT/CN2019/103359 WO2020048381A1 (en) | 2018-09-03 | 2019-08-29 | Chip test device and method |
| US17/124,088 US11385279B2 (en) | 2018-09-03 | 2020-12-16 | Chip test device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811019070.6A CN108957300A (en) | 2018-09-03 | 2018-09-03 | Wafer test apparatus and test method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108957300A true CN108957300A (en) | 2018-12-07 |
Family
ID=64475588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811019070.6A Pending CN108957300A (en) | 2018-09-03 | 2018-09-03 | Wafer test apparatus and test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108957300A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020048381A1 (en) * | 2018-09-03 | 2020-03-12 | Changxin Memory Technologies, Inc. | Chip test device and method |
| CN114152864A (en) * | 2021-11-29 | 2022-03-08 | 江苏捷策创电子科技有限公司 | Method and device for multi-chip parallel test |
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| CN101446843A (en) * | 2008-12-30 | 2009-06-03 | 北京中星微电子有限公司 | High-frequency clock generator, clock frequency conversion method, and chip |
| CN102466777A (en) * | 2010-11-12 | 2012-05-23 | 瑞鼎科技股份有限公司 | Integrated circuit testing device |
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| CN1627629A (en) * | 2000-09-26 | 2005-06-15 | 三星电子株式会社 | Detection control device to improve frequency multiplication |
| CN1478204A (en) * | 2000-11-30 | 2004-02-25 | ���ء����߸� | Method and device for carrying out frequency synthesis in distance measuring device and distance measuring device thereof |
| CN101446843A (en) * | 2008-12-30 | 2009-06-03 | 北京中星微电子有限公司 | High-frequency clock generator, clock frequency conversion method, and chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020048381A1 (en) * | 2018-09-03 | 2020-03-12 | Changxin Memory Technologies, Inc. | Chip test device and method |
| US11385279B2 (en) | 2018-09-03 | 2022-07-12 | Changxin Memory Technologies, Inc. | Chip test device and method |
| CN114152864A (en) * | 2021-11-29 | 2022-03-08 | 江苏捷策创电子科技有限公司 | Method and device for multi-chip parallel test |
| CN114152864B (en) * | 2021-11-29 | 2024-05-03 | 江苏捷策创电子科技有限公司 | Multi-chip parallel test method and device |
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