CN102456667B - 接合焊盘结构以及具有该接合焊盘结构的晶片 - Google Patents

接合焊盘结构以及具有该接合焊盘结构的晶片 Download PDF

Info

Publication number
CN102456667B
CN102456667B CN201110166558.3A CN201110166558A CN102456667B CN 102456667 B CN102456667 B CN 102456667B CN 201110166558 A CN201110166558 A CN 201110166558A CN 102456667 B CN102456667 B CN 102456667B
Authority
CN
China
Prior art keywords
technology controlling
pad
bond pad
process monitoring
bow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110166558.3A
Other languages
English (en)
Other versions
CN102456667A (zh
Inventor
陈英儒
陈宪伟
蔡豪益
李明机
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102456667A publication Critical patent/CN102456667A/zh
Application granted granted Critical
Publication of CN102456667B publication Critical patent/CN102456667B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Automation & Control Theory (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种在半导体晶片中用来进行晶片测试的接合焊盘结构以及具有该接合焊盘结构的晶片。上述接合焊盘结构包括至少两个金属接合焊盘，彼此之间借由在一个或多个绝缘层中的多个导电通孔互相连接。与最底端的金属接合焊盘相接触的多个接触条，其实质上自最底端的金属接合焊盘垂直延伸进入基板。绝缘结构实质上围绕着多个接触条，以便将接合焊盘结构隔离。本发明的工艺控制监测焊盘结构具有的优点如下：借由在裸片单分工艺中降低破裂形成及破裂延伸至裸片的可能性，以及将晶片中的工艺控制监测焊盘结构与其他装置隔绝，避免漏电流，来增加在测试期间的集成电路的可靠度。

Description

接合焊盘结构以及具有该接合焊盘结构的晶片
技术领域
本发明涉及一种半导体装置及制造技术，特别涉及一种内连线结构及测试方法。
背景技术
为了实现半导体集成电路的高集成度以及高速的目标，缩减了半导体集成电路的尺寸，并且于制造过程中运用各种不同的材料及技术。例如，运用双镶嵌技术(dual damascene technology)以及铜导体以减少在集成电路(integrated circuits，ICs)中内连线结构的电阻及电阻电容(resistance-capacitance，RC)延迟。当集成电路的体积制作的越小，而介于相邻导线之间的距离也随之缩短时，可在铜质内连线技术(copperinterconnect technology)上利用低介电常数(low dielectric constant，low-k)的介电材料，以减少这些延迟。
半导体集成电路的内连线结构，将集成电路各种不同的有源元件及电路，连结至在裸片表面上的多个导电接合焊盘。为了更有效地在有源元件及裸片表面之间布线，目前已发展出多层内连线结构(multi-level interconnectstructures)，以配合有源元件密度的进展。在典型的集成电路设计中，可利用五个甚至更多个独立的导电路径的内连线层，来配合有源元件的密度。多层内连线结构包括排列在多重膜层中的金属导线。各个独立的膜层的金属导线形成于层间介电(interlevel dielectric，ILD)材料中，层间介电材料电性隔绝金属导线和内连线结构的各个膜层中的其他金属导线，并且电性隔绝在邻近膜层中的金属导线。
镶嵌工艺(damascene processes)通常用于制造多层内连线结构(multi-level interconnect structures)的后段工艺(back-end-of-line，BEOL)中。在镶嵌工艺中，在层间介电层中蚀刻沟槽及导通孔，并且使用如铜或以铜为基础的合金的导电材料来填充沟槽及导通孔，来制造介于不同膜层中的内连线之间的导线及垂直导电路径。
多层内连线结构的导电路径终止于集成电路(Integrated Circuit，IC)表面的接合焊盘(bond pads)。接合焊盘为至少分布遍及裸片的顶面的相对较大的金属面积。利用接合焊盘，让介于集成电路和集成电路封装的封装基板或探针(用于晶片验收测试，wafer acceptance testing，WAT)之间得以电性接触。用于晶片验收测试的接合焊盘也称为工艺控制监测器接合焊盘(process control monitor pad，PCM pad)。每一次的探测，探针和接合焊盘之间电性即会有一次接触，如此一来可供应电压或电流给集成电路，以测试装置的功能及性能。用于晶片验收测试的接合焊盘可分布于裸片之间的切割线中。这些切割线在裸片单分工艺(die singulation process)期间会被切断，其切割线会贯穿接合焊盘。
在内连线结构上配置晶片验收测试接合焊盘的传统方法，是在各个内连线层上的切割线中设置接合焊盘，其排列对齐于顶金属层的切割线中的接合焊盘之下，并且在各个内连线层中设置连接于接合焊盘的金属填充导通孔(metal-filled vias)，其排列对齐于各个在顶金属层中的接合焊盘或探针焊盘(probe pad)之下。在第二内连线层M2至顶金属层(top metal，MT)形成之前，第一内连线层M1中的接合焊盘可用于原位测试(in situ testing)。
裸片切割(dicing)(或单分，singulation)工艺会产生很大的机械应力，此机械应力取决于多项条件，包括：切割宽度、裸片锯速率(die saw speed)、裸片锯切温度(die saw temperature)、裸片锯切压力(die saw pressure)等。
由于当工艺控制监测焊盘(process control monitor pad，PCM pad)被裸片锯切割时会产生破裂(cracking)，因此传统的多层内连线结构(multi-levelinterconnect structures)容易发生故障。根据经验显示，在裸片单分工艺期间，在切割线中的介电质会于邻近接合焊盘处破裂(cracking)，且上述破裂可能会延伸至裸片。当低介电常数的介电质材料(low-k dielectric materials)(包括极低介电常数(extreme low-k，ELK)、及超低介电常数(ultra low-k，ULK))被用来作为层间介电(ILD)材料时，这个问题将会变得更加严重。
发明内容
为了克服现有技术的缺陷，本发明提供一种晶片，包括：一基板，具有多个集成电路形成于该基板上，且在两个该集成电路之间至少有一切割线；多个介电层形成于至少一切割线中，该介电层具有一工艺控制监测焊盘结构形成于该多个介电层中，该工艺控制监测焊盘结构具有：多个金属接合焊盘，借由多个导电通孔互相连接；多个接触条，与最底端的金属接合焊盘相接触，该接触条自最底端金属接合焊盘实质上垂直延伸进入该基板；以及一绝缘结构，实质上围绕着该多个接触条以隔离该工艺控制监测焊盘结构。
本发明另提供一种晶片，包括：一基板，具有多个集成电路形成于该基板上，且在两个该集成电路之间至少有一切割线：以及多个介电层形成于至少一切割线中，该介电层具有一工艺控制监测焊盘结构形成于该多个介电层中，该工艺控制监测焊盘具有：多个金属接合焊盘，借由多个导电通孔彼此之间互相连接；一个或多个绝缘结构；以及多个接触条，与最底端的金属接合焊盘相接触，该接触条自最底端金属接合焊盘实质上垂直延伸以接触该绝缘结构。
本发明尚提供一种工艺控制监测焊盘结构，用来进行集成电路测试及故障分析，包括：至少两个金属接合焊盘彼此之间借由多个导电通孔互相连接；多个接触条，与最底端的金属接合焊盘相接触，该些接触条自最底端金属接合焊盘实质上垂直延伸进入该基板；以及一绝缘结构实质上围绕着多个接触条，以隔离该工艺控制监测焊盘结构。
本发明还提供一种工艺控制监测焊盘结构，用来进行集成电路测试及故障分析，包括：至少两个金属接合焊盘彼此之间借由多个导电通孔互相连接；一个或多个绝缘结构；以及多个接触条，与最底端的金属接合焊盘相接触，该接触条自最底端金属接合焊盘实质上垂直延伸以接触该绝缘结构。
本发明的工艺控制监测焊盘结构具有的优点如下：借由在裸片单分工艺中降低破裂形成及破裂延伸至裸片的可能性，以及将晶片中的工艺控制监测焊盘结构与其他装置隔绝，避免漏电流，来增加在测试期间的集成电路的可靠度。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附附图，作详细说明如下：
附图说明
图1a为第一实施例中，在半导体晶片的切割线中的工艺控制监测焊盘结构的部分剖面图。
图1b为图1a中的工艺控制监测焊盘结构的透视图。
图2a为第二实施例中，在半导体晶片的切割线中的工艺控制监测焊盘结构的部分剖面图。
图2b为图2a中的工艺控制监测焊盘结构的透视图。
图3a为第三实施例中，在半导体晶片的切割线中的工艺控制监测焊盘结构的部分剖面图。
图3b为图3a中的工艺控制监测焊盘结构的透视图。
并且，上述附图中的附图标记说明如下：
Figure BSA00000522470100041
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。值得注意的是，这些实施例提供许多可行的发明概念并可实施于各种特定情况。然而，本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰。在一些实施例中，已经被大家广为所知的结构和工艺将不再赘述，以避免模糊本发明的实施例。
在整份说明书中，出现“一个实施例”或“一实施例”表示，在至少一个本发明的实施例中，包括一个与此实施例相关的特定的特征、结构、或性质。因此，在整份说明书中的各种不同地方有“一个实施例”或“一实施例”一辞的出现，并非皆是描述同一个实施例。此外，在一个或多个实施例中，特定的特征、结构、或性质可以任何适当的形式彼此结合。应可理解的是，下述的各种特征并未按照比例绘制，相反地，这些特征仅作为说明之用。
在运用低介电常数的介电质材料(low-K dielectric materials)的半导体产品中，当切割工艺控制监测焊盘(PCM pad)时，常可观察到有破裂(cracking)的情形出现。上述破裂的机制十分复杂，但从经验上来说，在裸片单分工艺期间，当裸片锯片(die saw blade)移动穿过晶片的切割线中的工艺控制监测焊盘时，破裂很有可能与使用易碎的层间介电(ILD)层材料有关。当裸片切割刀片接触到控制监测器接合焊盘的金属结构时，破裂形成的可能性将会增加。
为了增加集成电路的可靠度，以及当借由裸片锯切割工艺控制监测焊盘时，降低裸片破裂的可能性，必须强化工艺控制监测焊盘的结构。在一些实施例中，借由形成多个接触条来强化工艺控制监测焊盘的结构。接触条与工艺控制监测焊盘结构的第一金属层M1相接触，并且镶嵌进入基板中，用来作为支柱，以降低在裸片切割工艺期间，工艺控制监测焊盘结构剥落(peelingoff)的可能性。
图1a为第一实施例中，工艺控制监测焊盘结构10的部分剖面图，此工艺控制监测焊盘结构10具有接触条40以及一形成于基板5中的绝缘结构50。图1b为第1a图中的工艺控制监测焊盘结构的透视图。此工艺控制监测焊盘结构10可形成于部分的工艺晶片上，其中多层集成电路半导体装置(multi-level integrated circuit semiconductor device)形成于上述的部分的工艺晶片上，或者，工艺控制监测焊盘结构10可形成于附近没有电子装置形成的部分。例如，工艺控制监测焊盘结构10首先形成一较低(第一)金属层M1(例如铜或铜合金)，此金属层M1形成于介电质绝缘层15中。形成金属层M1的传统工艺的进行，包括图案化、在绝缘层15中蚀刻沟槽开口、形成阻挡层以排列开口、利用金属来填充开口、以及进行平坦化工艺(planarization process)，例如：化学机械研磨(CMP)以将填充的金属平坦化。
在平坦化工艺步骤之后，形成一重叠的金属层M2，包括与金属层M1电性连通的导电通孔(conductive vias)30。应可了解，金属层M2及导电通孔30可分开个别形成，或借由一双镶嵌工艺(dual damascene process)形成。
图1a的工艺控制监测焊盘结构10也包括与金属层M1电性接触的多个接触条40，多个接触条40自金属层M1实质上垂直延伸进入基板5。接触条40可当作工艺控制监测焊盘结构10的支柱，且可降低在裸片单分工艺期间工艺控制监测焊盘结构10剥落(peeling off)，进而造成破裂形成及破裂延伸至裸片的可能性。接触条40可形成于第一金属层M1形成之前，并借由单或双镶嵌工艺(single or dual damascene process)形成。接触条40可由如钨、铜、铜合金、或铝所形成。其他的导电材料也在考虑范围内。应可了解，接触条40的数量、形状、宽度、及/或长度可个别或全部变更。然而，接触条40的数量、形状、宽度、及/或长度取决于：需要用于强化工艺控制监测焊盘结构的数量；以及防止在裸片单分工艺期间，工艺控制监测焊盘结构10剥落，进而造成破裂形成及破断延伸至裸片。
介于任两个邻近的工艺控制监测焊盘结构10之间皆具有接触条40，可能有漏电流(current leakage)的情形发生，其会影响测试模式(test pattern)的电性测试准确性(electrical test accuracy)，或导致其他负面的电性效应。为了防止在晶片中工艺控制监测焊盘结构之间或与其他装置之间发生漏电流，在接触条40的周围形成一绝缘结构50，借此隔绝工艺控制监测焊盘结构。图1a显示大体上为正方形或矩形的绝缘结构50。应可了解，绝缘结构50的形状并不限于图1a及图1b所示的范例，相反地，绝缘结构50的宽度、长度、及/或厚度等形状皆可个别或全部变更。例如，绝缘结构50可为环形。
在至少一实施例中，绝缘结构50包括氧化物，且其厚度D约500埃
Figure BSA00000522470100061
至2500埃
Figure BSA00000522470100062
更佳的情况的是，绝缘结构50的厚度足以在晶片中的装置之间产生电性隔绝。在至少一实施例中，绝缘结构50的厚度约500埃
Figure BSA00000522470100063
至1000埃
Figure BSA00000522470100064
在一些实施例中，绝缘结构50可为一浅沟槽绝缘(shallow trench isolation，STI)区域，并且包括氧化物。其他绝缘材料也可纳入考虑。可借由沟槽蚀刻、氧化物填充、以及氧化物抛光等的步骤，来形成浅沟槽绝缘区域。在一些实施例中，绝缘结构可为一场效氧化物(field oxide，FOX)层，其包括氧化物，且绝缘结构的厚度介于2500埃
Figure BSA00000522470100065
至15000埃以防止电荷的迁移。
在图2a及图2b所示的另一实施例中，绝缘结构50与多个接触条40电性接触，因此将在晶片中的工艺控制监测焊盘结构10与其他装置隔绝。在一些实施例中，多个接触条40实质上延伸进入绝缘结构50。
在图3a及图3b所示的另一实施例中，绝缘结构50连结至一个接触条40，以将工艺控制监测焊盘结构与其他装置隔绝。在其他实施例中，各个绝缘结构50实质上围绕着其相对应的一个接触条40的一端。
目前已描述了多个工艺控制监测焊盘结构的实施例。工艺控制监测焊盘结构具有的优点如下：借由在裸片单分工艺中降低破裂形成及破裂延伸至裸片的可能性，以及将晶片中的工艺控制监测焊盘结构与其他装置隔绝，避免漏电流，来增加在测试期间的集成电路的可靠度。
虽然本发明已以多个较佳实施例公开如上，然其并非用以限定本发明，本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。同样地，本发明说明书的描述与附图也仅仅作为说明之用而非用来限定本发明。应可了解，本发明的实施例可利用各种其他组合和环境，并且在不脱离本发明的精神和范围内，也可作任意的更动与润饰。

Claims (8)

1.一种晶片，包括：
一基板，具有多个集成电路形成于该基板上，且在两个该集成电路之间至少有一切割线；
多个介电层形成于至少一切割线中，该介电层具有一工艺控制监测焊盘结构形成于所述多个介电层中，该工艺控制监测焊盘结构具有：
多个金属接合焊盘，借由多个导电通孔互相连接；
多个接触条，与最底端的金属接合焊盘相接触，该接触条自最底端金属接合焊盘实质上垂直延伸进入该基板；以及
一绝缘结构，实质上围绕着所述多个接触条以隔离该工艺控制监测焊盘结构。
2.如权利要求1所述的晶片，其中该绝缘结构为一浅沟槽绝缘区域，或一场效氧化层。
3.如权利要求1所述的晶片，其中该接触条包括钨、铜、铜合金、铝、或上述的组合。
4.一种晶片，包括：
一基板，具有多个集成电路形成于该基板上，且在两个该集成电路之间至少有一切割线：以及
多个介电层形成于至少一切割线中，该介电层具有一工艺控制监测焊盘结构形成于所述多个介电层中，该工艺控制监测焊盘具有：
多个金属接合焊盘，借由多个导电通孔彼此之间互相连接；
一个或多个绝缘结构，设于该基板中；以及
多个接触条，与最底端的金属接合焊盘相接触，该接触条自最底端金属接合焊盘实质上垂直延伸以接触该绝缘结构，其中所述多个接触条实质上延伸进入该绝缘结构。
5.如权利要求4所述的晶片，其中每一个绝缘结构实质上围绕着一个接触条，以隔离该工艺控制监测焊盘。
6.一种工艺控制监测焊盘结构，用来进行集成电路测试及故障分析，包括：
至少两个金属接合焊盘彼此之间借由多个导电通孔互相连接；
多个接触条，与最底端的金属接合焊盘相接触，所述多个接触条自最底端金属接合焊盘实质上垂直延伸进入一基板；以及
一绝缘结构实质上围绕着多个接触条，以隔离该工艺控制监测焊盘结构。
7.一种工艺控制监测焊盘结构，用来进行集成电路测试及故障分析，包括：
至少两个金属接合焊盘彼此之间借由多个导电通孔互相连接；
一个或多个绝缘结构，设于一基板中；以及
多个接触条，与最底端的金属接合焊盘相接触，该接触条自最底端金属接合焊盘实质上垂直延伸以接触该绝缘结构，其中所述多个接触条实质上延伸进入该绝缘结构。
8.如权利要求7所述的工艺控制监测焊盘结构，其中每一个绝缘结构实质上围绕着一个接触条，以隔离该工艺控制监测焊盘。
CN201110166558.3A 2010-10-19 2011-06-14 接合焊盘结构以及具有该接合焊盘结构的晶片 Active CN102456667B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US39447710P 2010-10-19 2010-10-19
US61/394,477 2010-10-19
US12/984,669 2011-01-05
US12/984,669 US9093411B2 (en) 2010-10-19 2011-01-05 Pad structure having contact bars extending into substrate and wafer having the pad structure

Publications (2)

Publication Number Publication Date
CN102456667A CN102456667A (zh) 2012-05-16
CN102456667B true CN102456667B (zh) 2014-04-02

Family

ID=45933362

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110166558.3A Active CN102456667B (zh) 2010-10-19 2011-06-14 接合焊盘结构以及具有该接合焊盘结构的晶片

Country Status (2)

Country Link
US (2) US9093411B2 (zh)
CN (1) CN102456667B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5953974B2 (ja) 2011-09-15 2016-07-20 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
US10090214B2 (en) * 2012-10-15 2018-10-02 Infineon Technologies Ag Wafer and method for processing a wafer
CN104752405B (zh) * 2013-12-27 2017-12-29 中芯国际集成电路制造(上海)有限公司 半导体器件的测试结构及其形成方法
US9831193B1 (en) * 2016-05-31 2017-11-28 Texas Instruments Incorporated Methods and apparatus for scribe street probe pads with reduced die chipping during wafer dicing
CN106158798A (zh) * 2016-07-11 2016-11-23 中航（重庆）微电子有限公司 一种芯片结构及其封装方法
CN106252313B (zh) * 2016-10-12 2018-12-11 上海华虹宏力半导体制造有限公司 一种接合焊盘结构
US10438902B2 (en) * 2017-09-07 2019-10-08 Globalfoundries Inc. Arc-resistant crackstop
US20200035641A1 (en) * 2018-07-26 2020-01-30 Invensas Bonding Technologies, Inc. Post cmp processing for hybrid bonding
TWI731431B (zh) * 2019-10-04 2021-06-21 旺宏電子股份有限公司 接墊結構
CN117059590B (zh) * 2023-10-11 2024-03-12 荣耀终端有限公司 晶圆结构及芯片

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495918B1 (en) * 2000-09-05 2002-12-17 Infineon Technologies Ag Chip crack stop design for semiconductor chips
CN100499108C (zh) * 2006-06-20 2009-06-10 台湾积体电路制造股份有限公司 内连线结构与晶片

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2776457B2 (ja) * 1992-12-29 1998-07-16 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスのクラックストップ形成方法及び半導体デバイス
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
US6174775B1 (en) * 1999-06-25 2001-01-16 Taiwan Semiconductor Manufacturing Company Method for making a dual gate structure for CMOS device
JP3538170B2 (ja) * 2001-09-11 2004-06-14 松下電器産業株式会社 半導体装置及びその製造方法
JP2003209134A (ja) * 2002-01-11 2003-07-25 Hitachi Ltd 半導体装置及びその製造方法
JP3811473B2 (ja) * 2003-02-25 2006-08-23 富士通株式会社 半導体装置
US20050026397A1 (en) * 2003-07-28 2005-02-03 International Business Machines Corporation Crack stop for low k dielectrics
US7223673B2 (en) * 2004-07-15 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device with crack prevention ring
US20060022195A1 (en) * 2004-08-01 2006-02-02 Kun-Chih Wang Scribe line structure
US7679195B2 (en) * 2006-06-20 2010-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. PAD structure and method of testing
US7622364B2 (en) * 2006-08-18 2009-11-24 International Business Machines Corporation Bond pad for wafer and package for CMOS imager
US7777339B2 (en) * 2007-07-30 2010-08-17 International Business Machines Corporation Semiconductor chips with reduced stress from underfill at edge of chip
US8680653B2 (en) * 2007-11-12 2014-03-25 Infineon Technologies Ag Wafer and a method of dicing a wafer
US8013333B2 (en) * 2008-11-07 2011-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor test pad structures
US7906836B2 (en) * 2008-11-14 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreader structures in scribe lines
US8748295B2 (en) * 2009-06-15 2014-06-10 Infineon Technologies Ag Pads with different width in a scribe line region and method for manufacturing these pads
US8314476B2 (en) * 2010-05-07 2012-11-20 Hynix Semiconductor, Inc. Semiconductor chip and semiconductor wafer
US8810001B2 (en) * 2011-06-13 2014-08-19 Mediatek Inc. Seal ring structure with capacitor
US8742594B2 (en) * 2012-09-14 2014-06-03 International Business Machines Corporation Structure and method of making an offset-trench crackstop that forms an air gap adjacent to a passivated metal crackstop

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495918B1 (en) * 2000-09-05 2002-12-17 Infineon Technologies Ag Chip crack stop design for semiconductor chips
CN100499108C (zh) * 2006-06-20 2009-06-10 台湾积体电路制造股份有限公司 内连线结构与晶片

Also Published As

Publication number Publication date
CN102456667A (zh) 2012-05-16
US20150318225A1 (en) 2015-11-05
US9831140B2 (en) 2017-11-28
US20120091455A1 (en) 2012-04-19
US9093411B2 (en) 2015-07-28

Similar Documents

Publication Publication Date Title
CN102456667B (zh) 接合焊盘结构以及具有该接合焊盘结构的晶片
CN102024781B (zh) 三维集成电路结构
CN103378033B (zh) 衬底通孔及其形成方法
CN1284226C (zh) 有机夹层介电材料中的铜通路的剪切应力的减小
JP2009147218A (ja) 半導体装置とその製造方法
US8692245B2 (en) Crack stop structure and method for forming the same
US6373136B2 (en) Damascene wiring structure and semiconductor device with damascene wirings
US9524933B2 (en) Semiconductor structures and fabrication methods thereof
US9875964B2 (en) Semiconductor device components and methods
US7196423B2 (en) Interconnect structure with dielectric barrier and fabrication method thereof
KR100739975B1 (ko) 반도체 소자의 제조 방법
KR100563817B1 (ko) 반도체 소자의 구리 배선 형성 방법
CN103094197B (zh) 互连结构制造方法
CN104752405A (zh) 半导体器件的测试结构及其形成方法
KR100871551B1 (ko) 반도체 소자 및 그 제조방법
CN109309019B (zh) 测试结构和测试方法
KR20080001905A (ko) 반도체 소자의 금속 배선 형성방법
US20150145055A1 (en) High voltage devices and method of manufacturing the same
KR101150605B1 (ko) 반도체 소자 및 그 제조 방법
US6835605B2 (en) Method for providing and utilizing rerouting resources
KR20100036008A (ko) 반도체 소자의 금속배선 형성방법
US20240222268A1 (en) Semiconductor device having contact plug
KR20080002027A (ko) 반도체 소자의 제조방법
KR101029107B1 (ko) 반도체 소자의 금속배선 및 그 형성방법
KR100645225B1 (ko) 반도체 소자의 금속 배선 형성방법 및 그 반도체 소자

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant