CN102456659A - 半导体芯片及用于制造半导体芯片的布局制备方法 - Google Patents

半导体芯片及用于制造半导体芯片的布局制备方法 Download PDF

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CN102456659A
CN102456659A CN201110309282XA CN201110309282A CN102456659A CN 102456659 A CN102456659 A CN 102456659A CN 201110309282X A CN201110309282X A CN 201110309282XA CN 201110309282 A CN201110309282 A CN 201110309282A CN 102456659 A CN102456659 A CN 102456659A
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connection pads
conductive connection
projection
semiconductor chip
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CN102456659B (zh
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陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种半导体芯片，其具有一半导体基底；一第一导电接垫，形成于基底上方；一第二导电接垫，形成于基底上，且比第一导电接垫更远离半导体芯片的几何中心；一第一凸块下方金属结构，形成于第一导电接垫上方；以及一第二凸块下方金属结构，形成于第二导电接垫上方。第一导电接垫及第一凸块下方金属结构具有一第一接垫对凸块下方金属宽度比，且第二导电接垫及第二凸块下方金属结构具有一第二接垫对凸块下方金属宽度比，其大于第一接垫对凸块下方金属宽度比。本发明通过增加导电接垫的接垫宽度或是增加接垫宽度对凸块下方金属宽度比，可降低基底的介电层内凸块破裂和/或断裂及剥离。因此，可改善半导体芯片封装的寿命。

Description

半导体芯片及用于制造半导体芯片的布局制备方法
技术领域
本发明涉及一种半导体封装，尤其涉及一种半导体芯片及用于制造半导体芯片的布局制备方法。
背景技术
当电路形成于半导体芯片上之后接着进行封装时，芯片上的电路与封装基底上输入/输出连接引脚(pin)之间的内连接可通过倒装芯片(Filp-Chip)封装技术来完成。倒装芯片组件包括面朝下(即，翻转)的半导体芯片位于封装基底(例如，陶瓷基底或电路板)上所构成的一直接电性连接。倒装芯片技术取代旧式打线接合(wire bonding)技术(采用面朝上的半导体芯片，其具有连接半导体芯片上每一接垫的导线)。
为了采用倒装芯片封装技术来进行半导体芯片封装，将半导体芯片翻转并放置于一封装基底上方。对导电凸块(bump)进行回流(reflow)，以在其间形成电性连接，并提供半导体芯片与封装基底有限的机械性固定。接着，采用底胶(underfilling)粘着剂，例如环氧化物，填充半导体芯片与封装基底之间的空间，以提供半导体芯片与封装基底之间更佳的机械性内连接。
发明内容
为了克服现有技术的缺陷，在本发明一实施例中，一种半导体芯片，包括：一基底；一电路，形成于基底上；多个导电接垫，形成于基底上，至少有一部分的导电接垫电性耦接于电路；以及多个凸块结构，对应形成于导电接垫上。其中，导电接垫包括：一第一导电接垫，具有一第一接垫宽度；以及一第二导电接垫，具有大于第一接垫宽度的一第二接垫宽度，且第一导电接垫比第二导电接垫接近导体芯片的一几何中心。
在本发明另一实施例中，一种用于制造半导体芯片的布局制备方法，包括：决定多个凸块位置；选择一第一组凸块位置，其占据半导体芯片的一第一区；选择一第二组凸块位置，其占据半导体芯片的一第二区，其中第二区比第一区更远离半导体芯片的一几何中心；在第一组凸块位置形成一个或多个导电接垫图案及对应的凸块下方金属图案，其具有一第一接垫对凸块下方金属宽度比；以及在第二组凸块位置形成一个或多个导电接垫图案及对应的凸块下方金属图案，其具有大于第一接垫对凸块下方金属宽度比的一第二接垫对凸块下方金属宽度比。
在本发明又一实施例中，一种半导体芯片，包括：一基底；一第一导电接垫，形成于基底上；一第一凸块下方金属(under bump metallurgy，UBM)结构，形成于第一导电接垫上，第一导电接垫及第一凸块下方金属结构具有一第一接垫对凸块下方金属宽度比；一第二导电接垫，形成于基底上，且其比第一导电接垫更远离半导体芯片的一几何中心；以及一第二凸块下方金属结构，形成于第二导电接垫上，第二导电接垫及第二凸块下方金属结构具有大于第一接垫对凸块下方金属宽度比的一第二接垫对凸块下方金属宽度比。
本发明通过增加导电接垫的接垫宽度或是增加接垫宽度对凸块下方金属宽度比，可降低基底的介电层内凸块破裂和/或断裂及剥离。因此，可改善半导体芯片封装的寿命。
附图说明
图1A是示出根据一实施例的具有凸块结构位于基底上的半导体芯片局部剖面示意图。
图1B是示出图1A中半导体芯片内导电接垫上方的凸块下方金属结构平面示意图。
图2A是示出根据一实施例的用于半导体芯片的凸块布局平面示意图。
图2B至图2D是示出根据各个实施例的用于半导体芯片的凸块布局的局部放大平面示意图。
图3是示出根据模拟数据的导电接垫尺寸与施加于介电层的应力的关系图。
图4是示出根据一些实施例的用于制造半导体芯片的布局制备方法流程图。
图5是示出根据一实施例的可用于一方法的电脑系统高阶功能方框图。
其中，附图标记说明如下：
100～半导体芯片；
110～凸块结构；
112～凸块下方金属结构；
114～焊料凸块；
120～基底；
130～导电接垫；
140～钝化保护层；
200～凸块布局；
202～凸块位置；
204～凸块位置；
210～几何中心；
220、222、224、226～中心区；
230、232、234、236～角落区；
232a～第一角落区；
232b～第二角落区；
240、242、244、246～周围区；
242a、246a～第一周围区；
242b、246b～第二周围区；
250～方形凸块接合边缘；
250a～第一凸块下方金属接合边缘；
250b～第二凸块下方金属接合边缘；
260a～第一弧线；
260b～第二弧线；
270a、270b、270c、270d～矩形区；
410、420、430、440、450～操作步骤；
500～电脑系统；
510～电脑可读式存储媒体；
520～微处理器；
530～输入/输出接口；
540～显示器；
C1～既定侧边长度；
C2～侧边长度；
D1、D2、D3、D4～距离；
E～侧向边对边距离；
p～间距；
P1、R1～第一距离；
P2、R2～第二距离；
X～凸块下方金属宽度。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可容易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所公开的特定实施例仅仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。再者，为了内文清晰的目的，附图中的特征及尺寸并未依照比例绘示。
在以下说明中，提出了许多特定细节部分，以充分了解本发明。然而，任何本领域普通技术人员将会了解本发明能够在没有这些特定细节情形下实行。在一些范例中，并未详述公知结构及工艺，以避免使本发明产生不必要的混淆。
实质上的应力量存在于焊料锡球以及使用倒装芯片封装技术连接半导体芯片与封装基底的填充材料中。应力的增加部分来自于半导体芯片与封装基底之间热膨胀系数(coefficient of thermal expansion，CTE)差异。如以上所述，倒装芯片封装技术是将半导体芯片翻转置放于封装基底上，并对翻转的半导体芯片加热。这些操作施加大量的应力及应变于半导体基底。随着低机械强度材料(例如，低介电常数(low-k)材料)的使用增加，比起使用非低介电常数(low-k)材料的半导体芯片而言，更容易受到应力及应变的损伤。再者，当半导体芯片的尺寸增加，伴随封装工艺而来的应力及应变也会增加。
位于远离半导体芯片的中心区的凸块，例如位于半导体芯片的周围或四个角落，其所受应力及应变特别显著。随着时间的过去，应力会因为凸块龟裂和/或破裂以及半导体芯片封装的介电层剥离而导致机械性和/或电性失效。
图1A是示出根据一实施例的具有凸块结构110形成于基底120上的半导体芯片100。基底120具有一电路形成于其上。再者，基底120也具有多个导电层及介电层，其构成基底上电路的内连结构。
对应于凸块结构110的区域的一导电接垫130形成于基底120与凸块结构110之间。在一些实施例中，导电接垫130包括铝(Al)、铜(Cu)或铝/铜合金。虽然图1A仅示出一凸块结构110及一对应的导电接垫130，然而任何本领域普通技术人员可以了解的是半导体芯片100内的基底120上形成了多个凸块结构110及对应的多个导电接垫130。在至少一实施例中，至少有一部分的导电接垫130电性耦接至电路，且至少有另一部分的导电接垫130未电性耦接至电路。
一钝化保护层140形成于基底120上，且局部位于导电接垫130上。亦即，钝化保护层140本身定义出一开口，露出一部分的导电接垫130。在一些实施例中，利用光致抗蚀剂及蚀刻工艺来去除一部分的钝化保护层140而形成开口。在一些实施例中，钝化保护层140包括：氮化硅(SiN)、二氧化硅(SiO2)、氮氧化硅(SiON)、聚酰亚胺(polyimide)、氧化铅(lead oxide，PBO)或其他绝缘材料。虽然图1A仅示出单一钝化保护层140，然而在一些实施例中，二层或多层的钝化保护层可形成于基底120上。
凸块结构具有一凸块下方金属(UBM)结构112形成于导电接垫130上以及一焊料凸块114形成于凸块下方金属结构112上。凸块下方金属结构112为一中介导电层，电性连接导电接垫130及焊料凸块114。在一些实施例中，凸块下方金属结构112可通过无电电镀(electroless plating)、溅镀或电镀而形成。在至少一实施例中，凸块下方金属结构112包括一多层结构，例如粘着层、阻挡层和/或润湿层。在一些实施例中，粘着层由铬(Cr)、钛钨(TiW)、钛(Ti)或铝(Al)所构成。在一些实施例中，阻挡层为非必需的，且由镍(Ni)、镍钒(NiV)、铬铜(CrCu)、氮化钛(TiN)或钛钨(TiW)所构成。在一些实施例中，润湿层由铜(Cu)、金(Au)或银(Ag)所构成。
在一些实施例中，焊料凸块114可通过蒸镀、电解电镀(electrolyticplating)、无电电镀、和/或网版印刷一个或多个导电材料而形成于凸块下方金属结构112上。用于焊料凸块114的导电材料包括金属，例如锡(Sn)、铅(Pb)、镍、金、银、铜、铋(Bi)或其合金或与其他导电材料的混合物。在至少一实施例中，焊料凸块114包括63wt％(重量百分比)的锡与37wt％的铅。在一些实施例中，焊料凸块114为球型，且可通过临时加热导电材料至其熔点以上的温度而形成。虽然图1A中焊料凸块114直接形成于凸块下方金属结构112上，然而在一些实施例中，一个或多个额外的特征部件可形成于焊料凸块114与凸块下方金属结构112之间，凸块柱体(bump post)或一层或多层导电材料层。
图1B是示出图1A中半导体芯片100内的导电接垫130上方的凸块下方金属结构112的平面示意图，为了使内文更为清晰，图1B中省略了半导体芯片其他特征部件。导电接垫130的外型相似于凸块下方金属结构112的外型。虽然图1B中凸块下方金属结构112与导电接垫130为八边形，然而在其他实施例中，凸块下方金属结构112与导电接垫130可为圆形、其他规则的多边形或具有任何其他外型。再者，在图1A及图1B的实施例中，凸块下方金属结构112具有一凸块下方金属宽度X。凸块下方金属结构112水平地放置于导电接垫130的中心处，且凸块下方金属结构112与导电接垫130定义出一侧向边对边距离E。因此，导电接垫130具有一接垫宽度为X+2E。在一些实施例中，对于凸块下方金属宽度为85微米(μm)的工艺来说，侧向边对边距离E在1微米至12微米的范围。
图2A是示出根据一实施例的用于半导体芯片的凸块布局200平面示意图。一布局包括用以制造半导体芯片的图案层，例如用以在基底上形成半导体部件的各个图案层以及用以形成导电接垫和/或凸块结构的各个图案层。由布局工程师根据半导体芯片的电路设计而产生的上述图案通常经过布局编辑工具或是电子设计自动化(electronic design automation，EDA)工具的操作。每一图案对应一可使用于形成至少一特征部件(例如：阱区、漏极区、源极区、栅电极、导线或其他半导体基底上的特征部件)的光掩模图案。
在图2A中，‘X’符号表是半导体芯片的几何中心210，而每一圆形表示用以形成导电接垫及位于其上的凸块结构的凸块位置。虽然图2A中凸块位置排列成栅型图案，然而在一些实施例中，凸块位置可任意排列。再者，用于半导体芯片的凸块布局200具有一方形凸块接合边缘250。然而，在一些实施例中，凸块布局200具有不同外型的凸块接合边缘，例如具有矩形的外型轮廓或是八边形的外型轮廓。
根据凸块布局200所形成的半导体芯片具有多个导电接垫形成于凸块位置处的基底上以及多个凸块结构形成于对应的一个导电接垫上。在本实施例中，至少一第一导电接垫位于一凸块位置202，其比位于凸块位置204的一第二导电接垫更靠近几何中心210，且第二导电接垫具有一第二接垫宽度，其大于第一导电接垫的一第一接垫宽度。
在一些实施例中，上述导电接垫的接垫宽度随着导电接垫的位置离几何中心210越远而逐渐增加。在一些实施例中，上述导电接垫排列成多个组群，且位于其中一组群内的导电接垫具有实质上相同的接垫宽度。
导电接垫排列成对应半导体芯片的一中心区220的一组群、对应半导体芯片的一角落区230的一组群以及对应半导体芯片的一周围区240的一组群。在一些实施例中，离半导体芯片的几何中心越远的区域内的导电接垫具有较大的接垫宽度。举例来说，在至少一实施例中，位于周围区240内导电接垫的组群的接垫宽度大于位于中心区220的组群的接垫宽度，而位于角落区230内导电接垫的组群的接垫宽度大于位于周围区240的组群的接垫宽度。虽然图2A中仅示出三组导电接垫的组群，然而任何本领域普通技术人员可以了解的是在一些实施例中，导电接垫可排列成多于或少于三组导电接垫的组群。
图2B是示出根据一些实施例的用于半导体芯片的凸块布局的局部平面示意图，凸块位置根据中心区222、角落区232及周围区242进行分组。在一些实施例中，角落区232进一步划分为第一角落区232a及一第二角落区232b，而周围区242进一步划分为第一周围区242a及一第二周围区242b。
第一角落区232a由一直角三角形区定义而成，其具有一侧边沿一第一凸块下方金属接合边缘250a延伸以及另一侧边沿一第二凸块下方金属接合边缘250b延伸。上述侧边具有一既定侧边长度C1。第二角落区232b由上述直角三角形区与另一直角三角形区(其具有一侧边沿一第一凸块下方金属接合边缘250a延伸以及另一侧边沿一第二凸块下方金属接合边缘250b延伸，且侧边长度为C2)的差异定义而成。C1为零或正数值，而C2为大于C1的数值。
在凸块下方金属宽度为X且凸块下方金属结构之间间距为P的至少一实施例中，侧边长度C1等于1.707×X，而侧边长度C2等于1.707×(X+P)。
再者，一周围区242由一矩形区定义而成，其具有从第二凸块下方金属接合边缘250b偏移一第一距离(例如，零或P1)的一侧以及从第二凸块下方金属接合边缘250b偏移一第二距离(例如，P1或P2)的一侧，并除去角落区232a和/或232b。举例来说，第一周围区242a由第一距离为零且第二距离为P1的矩形区定义而成，而第二周围区242b由第一距离为P1且第二距离为P2的矩形区定义而成。P1及P2的数值大于零。虽然图2B仅示出局部的凸块布局200，然而其他部分的凸块布局也有相似的定义。
将位于几何中心210所处位置且未定义成角落区232a/232b以及周围区242a/242b的区域定义为中心区222。
图2C是示出根据一些实施例的用于半导体芯片的凸块布局的局部放大平面示意图。根据中心区224、角落区234及周围区244进行凸块位置的分组。
各个区域是由凸块下方金属接合边缘250a/250b或是弧线260a/260b所定义而成。举例来说，角落区234是由沿凸块下方金属接合边缘250a及250b延伸的侧边以及与几何中心210相距一第一距离R1的弧线260a所包围的区域定义而成。周围区244是由与几何中心210相距一第一距离R1的第一弧线260a以及与几何中心210相距一第二距离R2的第二弧线260b之间的区域定义而成。将位于几何中心210所处位置且未定义成角落区234以及周围区244的区域定义为中心区224。在至少一实施例中，第一距离R1及第二距离R2取决于几何中心210至不同既定角落区的最大距离。
图2D是示出根据一些实施例的用于半导体芯片的凸块布局的局部放大平面示意图。根据中心区226、角落区236及周围区246进行凸块位置的分组。周围区246又划分为一第一周围区246a及一第二周围区264b。
各个区域是由凸块下方金属接合边缘250a/250b或是矩形区270a/270b/270c/270d所定义而成。举例来说，角落区236是由矩形区270a与矩形区270b的重叠区域定义而成。矩形区270a是由凸块下方金属接合边缘250a以及与几何中心210相距一距离D1的一侧之间的区域定义而成，而矩形区270b是由凸块下方金属接合边缘250b以及与几何中心210相距一距离D2的一侧之间的区域定义而成。
第一周围区246a是由结合矩形区270a及270b并去除角落区236定义而成。第二周围区246b是由矩形区270c与矩形区270d之间的差异定义而成。矩形区270c是由在垂直方向与几何中心210相距一距离D1的一侧以及在水平方向与几何中心210相距一距离D2的一侧所定义而成，而矩形区270d是由在垂直方向与几何中心210相距一距离D3的一侧以及在水平方向与几何中心210相距一距离D4的一侧所定义而成。
将位于几何中心210所处位置且未定义成角落区236以及周围区246的区域定义为中心区226。虽然图2C至图2D仅示出局部的凸块布局200，然而其他部分的凸块布局也有相似的定义。另外，在一些实施例中，用于对凸块位置进行分组的各个区域也可使用根据图2B至图2D实施例所结合的方法定义而成。
在图2B至图2D实施例中，靠近几何中心210的区域内所形成的导电接垫与凸块结构具有较大的接垫宽度或是较高的接垫对凸块下方金属宽度比。举例来说，在一些实施例中，半导体芯片内的凸块下方金属结构具有相同的凸块下方金属宽度且为85微米；位于中心区220/222/224/226的导电接垫的侧向边对边距离为2微米；位于周围区240/242/244/246的导电接垫的侧向边对边距离为3.5微米；位于角落区230/232/234/236的导电接垫的侧向边对边距离为5微米。
图3是示出根据模拟数据的导电接垫尺寸与施加于介电层的应力的关系图。当导电接垫的尺寸增加，介电层所受的应力则降低。举例来说，假定凸块下方金属结构的宽度X为固定，而导电接垫的侧向边对边距离E为2.0微米，则介电层所受的应力定义为1.0(绝对单位)。当侧向边对边距离E为3.5微米，介电层所受的应力从1.0降至0.8，其表示应力降低20％。当侧向边对边距离E为5.0微米，介电层所受的应力从1.0降至0.7，其表示应力降低30％。
根据本实施例，任何本领域普通技术人员可以了解，凸块下方金属宽度与接垫宽度是取决于不同的制造和/或封装工艺的需求。在一些实施例中，进一步增加接垫尺寸或是增加接垫宽度对凸块下方金属宽度比并无法保证介电层所受的应力会降低相同的百分比。用于形成导电接垫的导电层也可使用于信号路径布线。因此，任何本领域普通技术人员可以了解用于半导体芯片中各种接垫宽度或是凸块下方金属宽度是取决于半导体芯片的应力等级或良率与导电接垫所占区域之间的平衡。
图4是示出根据一些实施例的用于制造半导体芯片的布局制备方法流程图。任何本领域普通技术人员可以理解的是在一些实施例中，可在进行图4的方法之前、期间和/或之后进行额外的操作。再者，在不脱离本发明的精神和范围内，所公开的操作也可在适当的时候增加、取代、改变次序和/或去除。
在操作步骤410中，根据一电路设计及特定制造和/或封装工艺的需求，以布局编辑工具或是电子设计自动化(EDA)工具进行操作来决定多个凸块位置。接着，在操作步骤420中，选择占据半导体芯片的一第一区的一第一组凸块位置。接着，在操作步骤430中，选择占据半导体芯片的一第二区的一第二组凸块位置。
每一凸块位置表示用于制造半导体芯片的导电接垫及凸块下方金属结构的一导电接垫图案以及一对应凸块下方金属图案的形成位置。在一些实施例中，对应于同一组凸块位置的导电接垫具有大体相同的接垫宽度，而对应于同一组凸块位置的凸块下方金属结构具有大体相同的凸块下方金属宽度。在本实施例中，第二区比第一区远离半导体芯片的几何中心。在一些实施例中，位于较远区域的凸块位置组，其具有较大的接垫宽度或是较大的接垫宽度对凸块下方金属宽度比。
在一非必要的操作步骤440中，选择一额外的次组凸块位置。举例来说，在图2B的实施例中，角落区230再细分为第一角落区230a及第二角落区230b，而次组凸块位置的选则取决于凸块位置所在的区域。在一些实施例中，往复地进行操作步骤440直至凸块布局根据一既定计划而划分成多个区域，且凸块位置根据凸块位置的所在进行分组。
之后，在操作步骤450中，具有一第一接垫宽度对凸块下方金属宽度比的一个或多个导电接垫图案及对应的凸块下方金属图案形成于第一组凸块位置，而具有一第二接垫宽度对凸块下方金属宽度比(其大于第一接垫宽度对凸块下方金属宽度比的)的一个或多个导电接垫图案及对应的凸块下方金属图案形成于第二组凸块位置。
每一凸块下方金属图案的外型相似于对应的导电接垫图案，并于凸块下方金属图案与导电接垫图案之间定义出一侧向边对边距离。在一些实施例中，侧向边对边距离在1微米至12微米的范围。在至少一实施例中，位于第一组凸块位置的凸块下方金属与导电接垫的一第一侧向边对边距离为2微米，而位于第二组凸块位置的凸块下方金属与导电接垫的一第二侧向边对边距离不小于4微米。
可应用不同的方式来决定区域以及选择凸块位置。在一些实施例中，如图2B所示，第二组凸块位置的选择是先通过定义一直角三角形区，接着在直角三角形区内选择凸块位置以作为第二组凸块位置。
在一些实施例中，如图2C所示，先通过沿一第一凸块下方金属接合边缘延伸的一第一侧边、沿一第二凸块下方金属接合边缘延伸的一第二侧边以及与几何中心相距一距离的一弧线围绕而定义出区域来进行第二组凸块位置的选择。在其他实施例中，如图2D所示，先通过定义出沿凸块下方金属接合边缘延伸的二个矩形区的重叠区来进行第二组凸块位置的选择。
在一些实施例中，操作步骤440包括选择占据半导体芯片的第三区的第三组凸块位置，第三区比第一区远离几何中心，且比第二区接近几何中心。同样地，对应于第三组凸块位置的导电接垫图案及凸块结构图案具有一第三接垫宽度对凸块下方金属宽度比，其大于第一接垫宽度对凸块下方金属宽度比，且小于第二接垫宽度对凸块下方金属宽度比。
可应用不同的方式来决定区域以及选择凸块位置。在一些实施例中，如图2B所示，第三组凸块位置的选择是先通过定义一第一直角三角形区及一第二直角三角形区来进行，接着基于第一及第二直角三角形区的差异定义出一梯形区。
在一些实施例中，如图2B所示，第三组凸块位置的选择是先通过定义一第一直角三角形区及一第二直角三角形区来进行，接着定义一矩形区，其具有从第一凸块下方金属接合边缘偏移一第一距离的一第一侧以及从第一凸块下方金属接合边缘偏移一第二距离的一第二侧。最后，选择位于矩形区内但未位于第一及第二直角三角形区的凸块位置作为第三组凸块位置。
在一些实施例中，如图2C所示，第三组凸块位置的选择是通过定义位于与几何中心相距一第一距离的一第一弧线与与几何中心相距一第二距离的一第二弧线之间的一区域来进行。又在一些实施例中，如图2D所示，第三组凸块位置的选择是通过定义位于围绕几何中心的一第一直角三角形区与围绕第一直角三角形区的一第二正方形区之间的一区域来进行。
图5是示出根据一实施例的用于布局制备方法的电脑系统500的高阶功能方框图。电脑系统500包括一电脑可读式存储媒体510，用以进行一电脑程序码(即，一组执行指令)的编码(即，存储)。电脑系统500包括电性耦接至电脑可读式存储媒体510的一微处理器520。微处理器520用以执行电脑可读式存储媒体510内的电脑程序码，使电脑系统500作为布局编辑工具或是电子设计自动化(EDA)工具，以进行图4所示的方法。
在一些实施例中，微处理器520为一中央处理单元(central processing unit，CPU)、多重处理器(multi-processor)、分布式处理系统(distributed processingsystem)和/或任何适当的处理单元。
在一些实施例中，电脑可读式存储媒体510为电子式、磁式、光学式、电磁式、红外线式和/或半导体系统(或装置)。举例来说，电脑可读式存储媒体510包括：半导体或固态存储器、磁带、可移除式电脑光盘、随机存取存储器(random access memory，RAM)、只读存储器(read-only memory，ROM)、硬盘和/或光盘。在一些使用光盘的实施例中，电脑可读式存储媒体510包括光盘只读存储器(compact disk-read only memory，CD-ROM)、可读写光盘(compact disk-read/write，CD-R/W)和/或数码影音光盘(digitalvideo disc，DVD)。
再者，电脑系统500包括：一输入/输出接口530及一显示器540。输入/输出接口530耦接至微处理器520，且容许布局工程师或电路工程师操作电脑系统500，以进行图4所示的方法。显示器540即时显示出图4所示的方法的操作状态，并可提供图形使用者接口(graphical user interface，GUI)。输入/输出接口530及显示器540容许操作者以人机操作方式进行电脑系统500的操作。
如以上所述，在一些实施例中，通过增加导电接垫的接垫宽度或是增加接垫宽度对凸块下方金属宽度比，可降低基底的介电层内凸块破裂和/或断裂及剥离。因此，可改善半导体芯片封装的寿命。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动、替代与润饰。再者，本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何本领域普通技术人员可从本发明公开内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。

Claims (10)

1.一种半导体芯片，包括：
一基底；
一电路，形成于该基底上；
多个导电接垫，形成于该基底上，至少有一部分的所述多个导电接垫电性耦接于该电路，且所述多个导电接垫包括：
一第一导电接垫，具有一第一接垫宽度；以及
一第二导电接垫，具有大于该第一接垫宽度的一第二接垫宽度，其中该第一导电接垫比该第二导电接垫接近该半导体芯片的一几何中心；以及
多个凸块结构，对应形成于所述多个导电接垫上。
2.如权利要求1所述的半导体芯片，其中所述多个导电接垫排列成多个组群，且位于所述多个组群的其中一个内的所述多个导电接垫具有相同的接垫宽度，所述多个组群包括：
一第一组群，包括具有该第一接垫宽度的导电接垫，且位于该半导体芯片的一中心区内；
一第二组群，包括具有该第二接垫宽度的导电接垫，且位于该半导体芯片的一角落区内；以及
一第三组群，包括具有一第三接垫宽度的导电接垫，且位于该半导体芯片的一周围区内，该第三接垫宽度大于该第一接垫宽度且小于该第二接垫宽度。
3.如权利要求1所述的半导体芯片，其中所述多个凸块结构包括：
一第一凸块结构，具有一第一凸块下方金属结构形成于该第一导电接垫上，且该第一凸块下方金属结构与该第一导电接垫的排置定义出一第一侧向边对边距离；以及
一第二凸块结构，具有一第二凸块下方金属结构形成于该第二导电接垫上，且该第二凸块下方金属结构与该第二导电接垫的排置定义出大于该第一侧向边对边距离的一第二侧向边对边距离。
4.一种用于制造半导体芯片的布局制备方法，包括：
决定多个凸块位置；
选择一第一组凸块位置，其占据该半导体芯片的一第一区；
选择一第二组凸块位置，其占据该半导体芯片的一第二区，其中该第二区比该第一区更远离该半导体芯片的一几何中心；
在该第一组凸块位置形成一个或多个导电接垫图案及对应的凸块下方金属图案，其具有一第一接垫对凸块下方金属宽度比；以及
在该第二组凸块位置形成一个或多个导电接垫图案及对应的凸块下方金属图案，其具有大于该第一接垫对凸块下方金属宽度比的一第二接垫对凸块下方金属宽度比。
5.如权利要求4所述的用于制造半导体芯片的布局制备方法，其中选择该第二组凸块位置包括：
定义一直角三角形区，其具有一第一侧边沿一第一凸块下方金属接合边缘延伸以及一第二侧边沿一第二凸块下方金属接合边缘延伸，该第一侧边及该第二侧边具有一既定侧边长度；以及
选择位于该直角三角形区内的凸块位置作为该第二组凸块位置。
6.如权利要求4所述的用于制造半导体芯片的布局制备方法，其中选择该第二组凸块位置包括：
定义一区域，其被沿一第一凸块下方金属接合边缘延伸的一第一侧边、沿一第二凸块下方金属接合边缘延伸的一第二侧边以及与该几何中心相距一距离的一弧线所围住；以及
选择位于该区域内的凸块位置作为该第二组凸块位置。
7.如权利要求4所述的用于制造半导体芯片的布局制备方法，还包括：
选择一第三组凸块位置，其占据该半导体芯片的一第三区，其中该第三区比该第一区更远离该几何中心且比该第二区更接近该几何中心；以及
在该第三组凸块位置形成一个或多个导电接垫图案及对应的凸块下方金属图案，其具有大于该第一接垫对凸块下方金属宽度比且小于该第二接垫对凸块下方金属宽度比的一第三接垫对凸块下方金属宽度比。
8.如权利要求7所述的用于制造半导体芯片的布局制备方法，其中选择该第三组凸块位置包括：
定义一第一直角三角形区，其具有一第一侧边沿一第一凸块下方金属接合边缘延伸以及一第二侧边沿一第二凸块下方金属接合边缘延伸，该第一侧边及该第二侧边具有一第一既定侧边长度；
定义一第二直角三角形区，其具有一第三侧边沿该第一凸块下方金属接合边缘延伸以及一第四侧边沿该第二凸块下方金属接合边缘延伸，该第三侧边及该第四侧边具有大于该第一既定侧边长度的一第二既定侧边长度；
基于该第一直角三角形区与该第二直角三角形区的差异定义一梯形区；以及
选择位于该梯形区内的凸块位置作为该第二组凸块位置。
9.如权利要求7所述的用于制造半导体芯片的布局制备方法，其中选择该第三组凸块位置包括：
定义一第一直角三角形区，其具有一第一侧边沿一第一凸块下方金属接合边缘延伸以及一第二侧边沿一第二凸块下方金属接合边缘延伸，该第一侧边及该第二侧边具有一第一既定侧边长度；
定义一第二直角三角形区，其具有一第三侧边沿该第一凸块下方金属接合边缘延伸以及一第四侧边沿一第三凸块下方金属接合边缘延伸，该第三侧边及该第四侧边具有该第一既定侧边长度；
定义一矩形区，具有从该第一凸块下方金属接合边缘偏移一第一距离的一第一侧以及从该第一凸块下方金属接合边缘偏移一第二距离的一第二侧；以及
选择位于该矩形区内且未位于该第一直角三角形区与该第二直角三角形区的凸块位置作为该第三组凸块位置。
10.一种半导体芯片，包括：
一基底；
一第一导电接垫，形成于该基底上；
一第一凸块下方金属结构，形成于该第一导电接垫上，该第一导电接垫及该第一凸块下方金属结构具有一第一接垫对凸块下方金属宽度比；
一第二导电接垫，形成于该基底上，且其比该第一导电接垫更远离该半导体芯片的一几何中心；以及
一第二凸块下方金属结构，形成于该第二导电接垫上，该第二导电接垫及该第二凸块下方金属结构具有大于该第一接垫对凸块下方金属宽度比的一第二接垫对凸块下方金属宽度比。
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