CN102427026A - Optimized removing method of hard mask of polycrystalline grid silicon oxide - Google Patents
Optimized removing method of hard mask of polycrystalline grid silicon oxide Download PDFInfo
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- CN102427026A CN102427026A CN2011101941530A CN201110194153A CN102427026A CN 102427026 A CN102427026 A CN 102427026A CN 2011101941530 A CN2011101941530 A CN 2011101941530A CN 201110194153 A CN201110194153 A CN 201110194153A CN 102427026 A CN102427026 A CN 102427026A
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Abstract
The invention relates to an optimized removing method of a hard mask of polycrystalline grid silicon oxide, so that a problem that there are lots of losses on silica of a shallow trench and an oxidized grid sidewall during a hard mask removing process in the prior art is solved. According to the invention, an optimized scheme is provided and removing of a hard mask is distributed into a side wall and self-aligning process flow design; therefore, an application amount of wet-method removing is substantially reduced, so that losses on silica of a shallow trench and an oxidized grid are minimized.
Description
Technical field
The present invention relates to a kind of semiconductor technology, relate in particular to a kind of polycrystalline gate oxidation silicon hard mask removal method of optimization.
Background technology
The use of hard mask is a kind of method more common in the following polysilicon gate manufacture craft of 130 nanometer technologies.Use hard mask to have more advantage; Such as can better controlling critical size; Can reduce defective generation in the etching process etc., but the removal technology of hard mask also can be brought some counter productives simultaneously, especially be embodied in the loss of silicon dioxide of shallow trench and oxidation grid.
So far; It all is after the polycrystalline grid etch is accomplished, to use all hard masks of the disposable removal of wet etching that the hard mask of traditional polycrystalline grid is removed, though this method can settle at one go, corresponding; The loss of the silicon dioxide of shallow trench and oxidation grid sidewall is also more relatively; On 65 nanometers and following technology, this is just becoming a technical bottleneck, demands urgently breaking through.
Hard mask removal technology conventional in the prior art is:
Fig. 1 is the structural representation after etching polysilicon gate is accomplished in the prior art, sees also Fig. 1, and generally in the following technology of 90 nanometers, the hard mask of polycrystalline grid uses silica-based material, and thickness generally is controlled at 100 ~ 500A; In the etching process of polycrystalline grid, hard mask generally has the loss of 50 ~ 300A, can be left 50 ~ 300A; It is the various silicon dioxide wet etching liquid on basis that the removal hard mask can use with hydrofluoric acid.
Fig. 2 is the structural representation after hard mask is removed through wet etching in the prior art; See also Fig. 2; Because the isotropic characteristic of wet etching; When hard mask was removed, the intersection of the sidewall of grid oxygen and shallow trench, active area all can have silicon dioxide loss to a certain degree, and serious will influence device property.
Summary of the invention
The invention discloses a kind of polycrystalline gate oxidation silicon hard mask removal method of optimization, in order to solve in the prior art hard mask removal process the more problem of silicon dioxide loss for shallow trench and oxidation grid sidewall.
Above-mentioned purpose of the present invention realizes through following technical scheme:
A kind of polycrystalline gate oxidation silicon hard mask removal method of optimization; In a substrate, be formed with a plurality of active areas of preparation field-effect transistor; And adjacent active area is isolated through the fleet plough groove isolation structure that is formed in the substrate, wherein, may further comprise the steps:
Step a: on the active area of this substrate, form a polycrystalline grid, and form a gate oxide layers that is positioned at polycrystalline grid below and a hard mask that covers polycrystalline grid top;
Step b: approach side wall preparation technology, form the thin side wall of one deck on the sidewall that covers the polycrystalline grid, thin side wall also covers on the sidewall of gate oxide layers simultaneously, and in the process that approaches side wall preparation technology, causes the loss of a spot of hard mask;
Step c: carry out thick side wall preparation technology, form the bed thickness side wall on the sidewall that covers thin side wall, and in the process of carrying out thick side wall preparation technology, cause the loss of a spot of hard mask;
Steps d: carry out metal silicide autoregistration shielding layer process; Deposition layer of silicon dioxide layer covers on substrate and the fleet plough groove isolation structure; Silicon dioxide layer covers hard mask, thin side wall, thick side wall simultaneously, deposits one deck silicon nitride afterwards and covers and also constitute the autoregistration layer on the oxide skin(coating) with it;
Step e: etching is removed the autoregistration layer, adopts dry etching to fall silicon nitride and a small amount of silicon dioxide in the autoregistration layer, utilizes wet method to remove in the autoregistration layer remaining silica again and removes remaining hard mask fully.
The polycrystalline gate oxidation silicon hard mask removal method of aforesaid optimization; Wherein, Thin side wall technology among the step b is specially: reach deposit one thin side wall layer on the hard mask on the polycrystalline grid at substrate; And thin side wall layer carried out etching, only keep on the sidewall that covers grid simultaneously thin side wall layer on the sidewall with gate oxide layers as thin side wall.
The polycrystalline gate oxidation silicon hard mask removal method of aforesaid optimization, wherein, deposition thickness less than the silicon dioxide of 250A or silicon nitride to form thin side wall layer.
The polycrystalline gate oxidation silicon hard mask removal method of aforesaid optimization, wherein, formation approaches side wall and thin side wall layer is carried out in the step of etching, the thin side wall layer at hard mask top is removed, and a spot of hard mask also is etched away.
The polycrystalline gate oxidation silicon hard mask removal method of aforesaid optimization; Wherein, Thick side wall technology among the step c is specially: deposit one thick side wall layer on substrate and hard mask; Thick side wall layer also covers on the said thin side wall simultaneously, and thick side wall layer is carried out etching thereupon, only keeps the thick side wall layer cover on the thin side wall sidewall as thick side wall.
The polycrystalline gate oxidation silicon hard mask removal method of aforesaid optimization, wherein, silicon dioxide or the silicon nitride of deposition thickness between 300A ~ 600A is to form thick side wall layer.
The polycrystalline gate oxidation silicon hard mask removal method of aforesaid optimization wherein, is carried out thick side wall layer in the process of etching, the thick side wall layer at hard mask top is removed, and etching is removed the hard mask of part polycrystalline top portions of gates.
The polycrystalline gate oxidation silicon hard mask removal method of aforesaid optimization, wherein, the thickness of the autoregistration layer of deposit in the steps d is between 200A ~ 600A.
In sum; Owing to adopted technique scheme; The polycrystalline gate oxidation silicon hard mask removal method of optimization of the present invention has solved in the prior art hard mask removal process for the more problem of silicon dioxide loss of shallow trench and oxidation grid sidewall, and the present invention proposes a kind of prioritization scheme, and the removal of hard mask is distributed in side wall, the self-registered technology flow scheme design; Significantly reduced the use amount that wet method is removed, thereby dropped to the loss of the silicon dioxide of shallow trench and oxidation grid minimum.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the structural representation after etching polysilicon gate is accomplished in the prior art;
Fig. 2 is the structural representation after hard mask is removed through wet etching in the prior art;
Fig. 3 is the structural representation after the thin side wall technology of the completion of the polycrystalline gate oxidation silicon hard mask removal method optimized of the present invention;
Fig. 4 is the structural representation after the thick side wall technology of completion of the polycrystalline gate oxidation silicon hard mask removal method optimized of the present invention;
Fig. 5 is the structural representation behind the deposit autoregistration layer of the polycrystalline gate oxidation silicon hard mask removal method optimized of the present invention;
Fig. 6 is the structural representation after the etching of the polycrystalline gate oxidation silicon hard mask removal method optimized of the present invention is removed autoregistration layer and hard mask layer.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
A kind of polycrystalline gate oxidation silicon hard mask removal method of optimization; In a substrate, be formed with a plurality of active areas of preparation field-effect transistor; And adjacent active area is isolated through the fleet plough groove isolation structure that is formed in the substrate, wherein, may further comprise the steps:
Fig. 1 is the structural representation after etching polysilicon gate is accomplished in the prior art; See also Fig. 1; Step a: on the active area 101 of this substrate 10, form a polycrystalline grid 202, and form the gate oxide layers 201 that is positioned at polycrystalline grid 202 belows and a hard mask 203 of polycrystalline grid 202 tops, above polycrystalline grid 202, have a hard mask 203; To between the 100A, hard mask 203 adopts silica-based material to the thickness of hard mask 203 at 50A;
Fig. 3 is the structural representation after the thin side wall technology of the completion of the polycrystalline gate oxidation silicon hard mask removal method optimized of the present invention; See also Fig. 3; Step b: approach side wall preparation technology, form the thin side wall 301 of one deck on the sidewall that covers polycrystalline grid 202, at the thin side wall 301 of sidewall covering of polycrystalline grid; Thin side wall also covers on the sidewall of gate oxide layers 201 simultaneously; In the process that approaches side wall preparation technology, cause the loss of a spot of hard mask 203, wherein, thin side wall 301 technologies are specially: reach deposit thin side wall layer 301 on the hard mask on the polycrystalline grid 202 at substrate 10; And thin side wall layer 301 carried out etching; Only keep on the sidewall cover grid simultaneously the thin side wall 301 of 301 layers of conduct of thin side wall on the sidewall with gate oxide layers, thin side wall 301 technologies have effectively been protected the sidewall of gate oxide layers 201, have effectively avoided in subsequent technique etching to remove in the process of hard mask 203 damage to gate oxide layers 201 sidewalls;
Wherein, deposition thickness approaches 301 layers of side walls less than silicon dioxide or the silicon nitride of 250A to form.
Further; Etching is removed in the process of 301 layers of the thin side walls of part the 301 layers of removal of thin side wall with the polycrystalline top portions of gates, and etching removes the hard mask 203 of part polycrystalline top portions of gates, that is to say in etching and removes in the process of 301 layers of the thin side walls of part; Etching is removed 301 layers of thin side walls covering hard mask 203 tops; And remove part hard mask 203 simultaneously, in the technology below 90 nanometers, hard mask 203 will have the consumption about 50A.
Fig. 4 is the structural representation after the thick side wall technology of completion of the polycrystalline gate oxidation silicon hard mask removal method optimized of the present invention; See also Fig. 4; Step c: carry out thick side wall preparation technology; Formation covers the bed thickness side wall 401 on the sidewall that approaches side wall 301, in the process of carrying out thick side wall preparation technology, causes the loss of a spot of hard mask 203, wherein; Thick side wall 401 technologies are specially: deposit one thick side wall is 401 layers on substrate 10 and hard mask; Thick side wall layer 401 also covers on the said thin side wall 301 simultaneously, and thick side wall layer 401 is carried out etching thereupon, only keeps the 401 layers of thick side wall 401 as polycrystalline grid 202 of thick side wall that cover on thin side wall 301 sidewalls.
Wherein, silicon dioxide or the silicon nitride of deposition thickness between 300A ~ 600A is to form 401 layers of thick side walls.
Further, etching is removed in the process of 401 layers of the thick side walls of part the 401 layers of removal of thick side wall with the polycrystalline top portions of gates, and etching is removed the hard mask 203 of part polycrystalline top portions of gates; That is to say, remove in the process of 401 layers of the thick side walls of part, 401 layers of removal of thick side wall of hard mask 203 tops in etching; Remove part hard mask 203 simultaneously; In the technology below 90 nanometers, hard mask will have the consumption about 100 ~ 200A, and hard mask 203 is residual less after the etching.
Fig. 5 is the structural representation behind the deposit autoregistration layer of the polycrystalline gate oxidation silicon hard mask removal method optimized of the present invention; See also Fig. 5; Steps d: carry out metal silicide autoregistration shielding layer process; Deposition layer of silicon dioxide 502 covers on substrate 10 and shallow trench 102 isolation structures, and silicon dioxide 502 covers hard mask 203, thin side wall 301, thick side wall 401 simultaneously, deposits one deck silicon nitride 501 afterwards and covers and also constitute autoregistration layer 50 on the silicon dioxide 502 with it;
Wherein, the autoregistration layer 50 of deposition thickness between 200A ~ 600A.
In the steps d on the polycrystalline grid 202 on substrate 10 and the substrate 10 from down to up successively deposit one silicon dioxide 502 and a silicon nitride layer 501 to form autoregistration layer 50; Wherein, Carry out in the prior art in the process of step a, etching forms the polycrystalline grid will form groove at the active area 101 of substrate 10 and the intersection in shallow trench zone 102, carries out after the silicon dioxide 502 of steps d deposit; Will this groove be filled, thus the groove of elimination active area 101 and shallow trench zone 102 intersections.
Fig. 6 is the structural representation after the etching of the polycrystalline gate oxidation silicon hard mask removal method optimized of the present invention is removed autoregistration layer and hard mask layer; See also Fig. 6; Step e: adopt dry etching to fall silicon nitride and a small amount of silicon dioxide in the autoregistration layer 50; Utilize wet method to remove in the autoregistration layer 50 remaining silica and remove fully after the remaining hard mask completing steps d again; Hard mask also has small amount of residual for 203 layers; In the following technology of 90 nanometers, residual quantity can be between 50A ~ 200A, and the autoregistration layer 50 that etching is removed hard mask 203 tops in the process of etching removal autoregistration layer 50 is also simultaneously with remaining hard mask 203 removals.
Carry out dry etching among the step e and remove said silicon nitride layer 501 and certain thickness silicon dioxide 502; Carry out wet etching afterwards and remove remaining silica 502; And in the process of carrying out wet etching, the hard mask on the polycrystalline grid 2 203 is removed; In the process of removing silicon dioxide 502; Because what adopt is wet etching, can cause damage to active area 101 and shallow trench zone 102 intersections, produce groove; But fill and lead up owing in the process of steps d deposition of silica, etching is formed the groove that the polycrystalline grid forms; And the thickness of the residue hard mask 203 that final step wet etching of the present invention institute etching is removed is less than the direct thickness of the hard mask 203 removed of etching in the prior art, so than prior art, the loss of adopting technical scheme of the present invention to remove hard mask shallow trenchs zone 102,203 back and active area 101 intersections reduces to some extent.
In sum; The polycrystalline gate oxidation silicon hard mask removal method of optimization of the present invention has solved in the prior art hard mask removal process the more problem of silicon dioxide loss for shallow trench and oxidation grid sidewall; The present invention proposes a kind of prioritization scheme; The removal of hard mask is distributed in side wall, the self-registered technology flow scheme design, significantly reduced the use amount that wet method is removed, thereby drop to the loss of the silicon dioxide of shallow trench and oxidation grid minimum.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and the foregoing description can realize said variant, do not repeat them here.Such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (8)
1. the polycrystalline gate oxidation silicon hard mask removal method of an optimization; In a substrate, be formed with a plurality of active areas of preparation field-effect transistor; And adjacent active area is isolated through the fleet plough groove isolation structure that is formed in the substrate, it is characterized in that, may further comprise the steps:
Step a: on the active area of this substrate, form a polycrystalline grid, and form a gate oxide layers that is positioned at polycrystalline grid below and a hard mask that covers polycrystalline grid top;
Step b: approach side wall preparation technology, form the thin side wall of one deck on the sidewall that covers the polycrystalline grid, thin side wall also covers on the sidewall of gate oxide layers simultaneously, and in the process that approaches side wall preparation technology, causes the loss of a spot of hard mask;
Step c: carry out thick side wall preparation technology, form the bed thickness side wall on the sidewall that covers thin side wall, and in the process of carrying out thick side wall preparation technology, cause the loss of a spot of hard mask;
Steps d: carry out metal silicide autoregistration shielding layer process; The deposition layer of silicon dioxide covers on substrate and the fleet plough groove isolation structure; Silicon dioxide covers hard mask, thin side wall, thick side wall simultaneously, deposits one deck silicon nitride afterwards and covers and also constitute the autoregistration layer on the silicon dioxide with it;
Step e: etching is removed the autoregistration layer, adopts dry etching to fall silicon nitride and small amounts thing in the autoregistration layer, utilizes wet method to remove in the autoregistration layer remaining oxide again and removes remaining hard mask fully.
2. the polycrystalline gate oxidation silicon hard mask removal method of optimization according to claim 1; It is characterized in that; Thin side wall technology among the step b is specially: reach deposit one thin side wall layer on the hard mask on the polycrystalline grid at substrate; And thin side wall layer carried out etching, only keep on the sidewall that covers grid simultaneously thin side wall layer on the sidewall with gate oxide layers as thin side wall.
3. the polycrystalline gate oxidation silicon hard mask removal method of optimization according to claim 2 is characterized in that, deposition thickness less than the oxide of 250A or silicon nitride to form thin side wall layer.
4. the polycrystalline gate oxidation silicon hard mask removal method of optimization according to claim 2; It is characterized in that; Formation approaches side wall and thin side wall layer is carried out in the step of etching, the thin side wall layer at hard mask top is removed, and a spot of hard mask also is etched away.
5. the polycrystalline gate oxidation silicon hard mask removal method of optimization according to claim 1; It is characterized in that; Thick side wall technology among the step c is specially: deposit one thick side wall layer on substrate and hard mask; Thick side wall layer also covers on the said thin side wall simultaneously, and thick side wall layer is carried out etching thereupon, only keeps the thick side wall layer cover on the thin side wall sidewall as thick side wall.
6. the polycrystalline gate oxidation silicon hard mask removal method of optimization according to claim 5 is characterized in that, oxide or the silicon nitride of deposition thickness between 300A ~ 600A is to form thick side wall layer.
7. the polycrystalline gate oxidation silicon hard mask removal method of optimization according to claim 5; It is characterized in that; Thick side wall layer is carried out in the process of etching, the thick side wall layer at hard mask top is removed, and etching is removed the hard mask of part polycrystalline top portions of gates.
8. the polycrystalline gate oxidation silicon hard mask removal method of optimization according to claim 1 is characterized in that the thickness of the autoregistration layer of deposit in the steps d is between 200A ~ 600A.
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| CN201110194153.0A CN102427026B (en) | 2011-07-12 | 2011-07-12 | Optimized removing method of hard mask of polycrystalline grid silicon oxide |
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| CN201110194153.0A CN102427026B (en) | 2011-07-12 | 2011-07-12 | Optimized removing method of hard mask of polycrystalline grid silicon oxide |
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Citations (7)
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| US6348389B1 (en) * | 1999-03-11 | 2002-02-19 | Taiwan Semiconductor Manufacturing Company | Method of forming and etching a resist protect oxide layer including end-point etch |
| TW530342B (en) * | 1999-08-10 | 2003-05-01 | Taiwan Semiconductor Mfg | Formation method of self-aligned silicide using dual spacer |
| US20060121708A1 (en) * | 2004-12-07 | 2006-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming self-aligned silicides |
| US20080153241A1 (en) * | 2006-12-26 | 2008-06-26 | Chia-Jung Hsu | Method for forming fully silicided gates |
| US20080305601A1 (en) * | 2007-06-06 | 2008-12-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor device using multi-functional sacrificial dielectric layer |
| CN101330006A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Gate structure and manufacturing method thereof |
| US20090174002A1 (en) * | 2008-01-09 | 2009-07-09 | International Business Machines Corporation | Mosfet having a high stress in the channel region |
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2011
- 2011-07-12 CN CN201110194153.0A patent/CN102427026B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348389B1 (en) * | 1999-03-11 | 2002-02-19 | Taiwan Semiconductor Manufacturing Company | Method of forming and etching a resist protect oxide layer including end-point etch |
| TW530342B (en) * | 1999-08-10 | 2003-05-01 | Taiwan Semiconductor Mfg | Formation method of self-aligned silicide using dual spacer |
| US20060121708A1 (en) * | 2004-12-07 | 2006-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming self-aligned silicides |
| US20080153241A1 (en) * | 2006-12-26 | 2008-06-26 | Chia-Jung Hsu | Method for forming fully silicided gates |
| US20080305601A1 (en) * | 2007-06-06 | 2008-12-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor device using multi-functional sacrificial dielectric layer |
| CN101330006A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Gate structure and manufacturing method thereof |
| US20090174002A1 (en) * | 2008-01-09 | 2009-07-09 | International Business Machines Corporation | Mosfet having a high stress in the channel region |
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