CN101330006A - Gate structure and manufacturing method thereof - Google Patents
Gate structure and manufacturing method thereof Download PDFInfo
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- CN101330006A CN101330006A CNA2007100421481A CN200710042148A CN101330006A CN 101330006 A CN101330006 A CN 101330006A CN A2007100421481 A CNA2007100421481 A CN A2007100421481A CN 200710042148 A CN200710042148 A CN 200710042148A CN 101330006 A CN101330006 A CN 101330006A
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Abstract
The invention discloses a method for manufacturing a gate structure, which includes the steps that a first medium layer is formed on a semiconductor substrate; a gate layer which covers the first medium layer is deposited; a second medium layer which covers the gate layer is deposited; the second medium layer and the gate layer are etched; a third medium layer which covers the second medium layer and the gate layer is deposited and the third medium layer is etched. By adding the second medium layer on the gate surface, a side wall which is obtained from the etching of the third medium layer is formed to the whole structure composed of the gate and the second medium layer so as to further form the gate structure, which can prevent reactants from being contacted with the gate surface when in the formation of silicon-germanium source-drain.
Description
Technical field
The present invention relates to the ic manufacturing technology field, particularly a provenance is leaked grid structure and the manufacture method thereof before forming.
Background technology
Fig. 1 is the grid structure schematic diagram before the source leak to form in the prior art, as shown in Figure 1, existing source leak grid structure before forming comprise the gate oxide 11 that is positioned at at semiconductor-based the end 10, be positioned on this gate oxide grid 13 and around the side wall 12 of this grid.This side wall leaks break-through near raceway groove down to contingent source in order to prevent that more heavy dose of source from leaking to inject too.For convenience of description, in the presents " grid structure before forming is leaked in the source " is abbreviated as " grid structure ".
Application number is for also providing the method for multiple this type of formation grid structure in the Chinese patent application such as " 200510009531.8 ".
Usually, the method for making this grid structure comprises:
At first, on the semiconductor-based end, form first dielectric layer;
This semiconductor-based end for defined device active region and finished shallow trench isolation from Semiconductor substrate.This first dielectric layer is a gate oxide, and described gate oxide material comprises silicon dioxide (SiO
2) or the silicon dioxide of doping hafnium (Hf).
Secondly, deposition grid layer, this grid layer covers first dielectric layer;
Described grid layer preferably is made of polysilicon, or is formed by combinations of materials such as polysilicon and metal silicides.
Subsequently, etching grid layer is to form grid;
Then, deposit second dielectric layer, this second dielectric layer cover gate and first dielectric layer;
This second dielectric layer is in order to form the side wall of all around gate.Described second dielectric layer comprises silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride, or a kind of in the stepped construction that constitutes of silicon dioxide, silicon oxynitride and/or silicon nitride and silicon dioxide and silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide.
At last, etching second dielectric layer with the formation side wall, and forms this grid structure.
Fig. 2 is a gate surface coronary fault schematic diagram when forming the silicon Germanium source leakage in the prior art, and as shown in Figure 2, actual production is found, leaks 14 o'clock in the formation silicon Germanium source, at the surperficial easily formation of polysilicon gate coronary fault 15.The analysis showed that this coronary fault 15 is SiGe reactant and the gate upper surface polysilicon of exposure and the product that lacks the gate electrode side surface polysilicon reaction back generation that exposes owing to height of side wall of the leakage of formation source.Reactant becomes the direction that suppresses this gate surface coronary fault generation with contacting of gate surface when thus, how to reduce the leakage of formation silicon Germanium source.
Summary of the invention
The invention provides a kind of grid structure manufacture method, the grid structure that reactant does not contact with gate surface when forming the silicon Germanium source leakage in order to be manufactured on; The invention provides a kind of grid structure, can avoid contacting of when forming silicon Germanium source and leak reactant and gate surface.
A kind of grid structure manufacture method provided by the invention comprises:
On the semiconductor-based end, form first dielectric layer;
Deposition grid layer, this grid layer covers described first dielectric layer;
Deposit second dielectric layer, this second dielectric layer covers described grid layer;
Described second dielectric layer of etching and grid layer;
Deposit the 3rd dielectric layer, this 3rd dielectric layer covers described second dielectric layer and grid layer;
Described the 3rd dielectric layer of etching.
The described first dielectric layer material comprises the silicon dioxide of silicon dioxide or doping hafnium; Described grid layer material comprises polysilicon; The described second dielectric layer material comprises a kind of or its combination in silicon dioxide, silicon nitride, the silicon oxynitride; Described the 3rd dielectric layer comprises silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride, or a kind of in the stepped construction that constitutes of silicon dioxide, silicon oxynitride and/or silicon nitride and silicon dioxide and silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide; The thickness of described second dielectric layer is less than or equal to the thickness of a kind of or its combination layer in silicon dioxide, silicon nitride, the silicon oxynitride in described the 3rd dielectric layer stepped construction.
A kind of grid structure provided by the invention, comprise be positioned at suprabasil first dielectric layer of semiconductor, be positioned at the grid on described first dielectric layer and be positioned on the described grid second dielectric layer and around the 3rd dielectric layer of the described grid and second dielectric layer, described the 3rd dielectric layer covers the sidewall of described second dielectric layer to small part.
The described second dielectric layer material comprises a kind of or its combination in silicon dioxide, silicon nitride, the silicon oxynitride; Described the 3rd dielectric layer comprises silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride, or a kind of in the stepped construction that constitutes of silicon dioxide, silicon oxynitride and/or silicon nitride and silicon dioxide and silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide; The thickness of described second dielectric layer is less than or equal to the thickness of a kind of or its combination layer in silicon dioxide, silicon nitride, the silicon oxynitride in described the 3rd dielectric layer stepped construction.
Compared with prior art, the present invention has the following advantages:
1. by increase by second dielectric layer in gate surface, then the overall structure to described grid and second dielectric layer formation forms the side wall that obtains behind described the 3rd dielectric layer of etching, and then the formation grid structure, can avoid contacting of when forming silicon Germanium source and leak reactant and gate surface;
2. by controlling the thickness of second dielectric layer, make side wall to the small part that obtains behind described the 3rd dielectric layer of etching cover the sidewall of described second dielectric layer, can avoid the exposure of gate electrode side surface polysilicon, guarantee that after the grid structure manufacturing is finished reactant does not contact with the gate electrode side surface when forming the silicon Germanium source leakage.
Description of drawings
Fig. 1 is a grid structure schematic diagram in the prior art;
Fig. 2 is a gate surface coronary fault schematic diagram when forming the silicon Germanium source leakage in the prior art;
Fig. 3 A～3F is the manufacturing process schematic diagram of the grid structure of the explanation embodiment of the invention;
Fig. 4 A～4D for etching the 3rd dielectric layer in the grid structure of the explanation embodiment of the invention to obtain the first manufacturing process schematic diagram of side wall;
Fig. 5 A～5D for etching the 3rd dielectric layer in the grid structure of the explanation embodiment of the invention to obtain the second manufacturing process schematic diagram of side wall.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work for those skilled in the art with advantage of the present invention.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
The step of using method manufacturing grid structure provided by the invention comprises: form first dielectric layer on the semiconductor-based end; Deposition grid layer, this grid layer covers described first dielectric layer; Deposit second dielectric layer, this second dielectric layer covers described grid layer; Described second dielectric layer of etching and grid layer; Deposit the 3rd dielectric layer, this 3rd dielectric layer covers described second dielectric layer and grid layer; Described the 3rd dielectric layer of etching.
Fig. 3 A～3F is the manufacturing process schematic diagram of grid structure of the explanation embodiment of the invention, as shown in the figure, uses method provided by the invention and makes the concrete steps of this grid structure and comprise:
At first, as shown in Figure 3A, on the semiconductor-based end 10, form first dielectric layer 20.
The described semiconductor-based end 1 for defined device active region and finished shallow trench isolation from Semiconductor substrate.Described first dielectric layer 20 is a gate oxide, and described gate oxide material comprises silicon dioxide (SiO
2) or the silicon dioxide of doping hafnium (Hf).The method of described formation first dielectric layer is selected thermal oxidation method or CVD method for use.
Secondly, shown in Fig. 3 B, deposition grid layer 30, described grid layer 30 covers described first dielectric layer 20.
Described grid layer 30 preferably is made of polysilicon, or is formed by combinations of materials such as polysilicon and metal silicides.
Subsequently, shown in Fig. 3 C, deposit second dielectric layer 40, described second dielectric layer 40 covers described grid layer 30.
The described second dielectric layer material comprises a kind of or its combination in silicon dioxide, silicon nitride, the silicon oxynitride, is preferably silicon nitride; The thickness of described second dielectric layer need guarantee that after the grid structure manufacturing is finished the reactant when forming the silicon Germanium source leakage does not contact with the gate electrode side surface.The thickness of described second dielectric layer is determined according to process conditions and product requirement.Preferably, the thickness of described second dielectric layer is slightly less than or equals the thickness of a kind of or its combination layer in silicon dioxide, silicon nitride, the silicon oxynitride in the described side wall layer stack structure.
By controlling the thickness of second dielectric layer, make side wall to the small part that obtains behind described the 3rd dielectric layer of etching cover the sidewall of described second dielectric layer, can avoid the exposure of gate electrode side surface polysilicon, guarantee that after the grid structure manufacturing is finished reactant does not contact with the gate electrode side surface when forming the silicon Germanium source leakage.
Then, shown in Fig. 3 D, described second dielectric layer 40 of etching and grid layer 30.
Grid layer after the described etching is in order to form grid.Second dielectric layer after the described etching is avoided the supplemental dielectric that reactant contacts with gate surface when forming the silicon Germanium source leakage in order to provide.
By increase by second dielectric layer in gate surface, then the overall structure to described grid and second dielectric layer formation forms the side wall that obtains behind described the 3rd dielectric layer of etching, and then the formation grid structure, can avoid contacting of when forming silicon Germanium source and leak reactant and gate surface.
Again, shown in Fig. 3 E, deposit the 3rd dielectric layer 50, described the 3rd dielectric layer 50 covers described second dielectric layer 40 and grid layer 30.
Described the 3rd dielectric layer is in order to form the side wall of all around gate.Described the 3rd dielectric layer comprises silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride, or a kind of in the stepped construction that constitutes of silicon dioxide, silicon oxynitride and/or silicon nitride and silicon dioxide and silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide.
At last, shown in Fig. 3 F, described the 3rd dielectric layer 50 of etching with the formation side wall, and then constitutes described grid structure.
Fig. 4 A～4D for etching the 3rd dielectric layer in the grid structure of the explanation embodiment of the invention to obtain the first manufacturing process schematic diagram of side wall, as shown in the figure, described the 3rd dielectric layer of deposition-etching comprises with the step of formation side wall: deposition-etching silicon dioxide (SiO
2) layer or deposition-etching silicon dioxide layer and silicon nitride/silicon oxynitride layer and silicon dioxide, silicon oxynitride and/or silicon nitride layer and silicon dioxide layer and silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide layer in turn.With the technology of deposition-etching silicon dioxide layer and silicon nitride/silicon oxynitride layer in turn is example, the step of deposition-etching silicon dioxide layer and silicon nitride/silicon oxynitride layer is in turn: at first, shown in Fig. 4 A, deposition of silica layer 51 covers second dielectric layer 40 and first dielectric layer 20 after the described etching; Subsequently, shown in Fig. 4 B, the described silicon dioxide layer of etching is to form so as to constituting the lateral wall substrate 52 of side wall layer stack structure; Then, shown in Fig. 4 C, deposited silicon nitride/silicon oxynitride layer 53 is to cover silicon dioxide layer, second dielectric layer and first dielectric layer after the described etching; At last, shown in Fig. 4 D, etch silicon nitride/silicon oxynitride layer constitutes side wall layer stack structure 54.In like manner, the step of deposition-etching silicon dioxide layer, silicon nitride/silicon oxynitride layer and silicon dioxide layer is in turn: deposition of silica layer at first, to cover second dielectric layer and first dielectric layer after the described etching; Etching silicon dioxide layer subsequently is to form so as to constituting first lateral wall substrate of side wall layer stack structure; Deposited silicon nitride/silicon oxynitride layer then is to cover first lateral wall substrate, second dielectric layer and first dielectric layer after the described etching; Etch silicon nitride/silicon oxynitride layer again is to form so as to constituting second lateral wall substrate of side wall layer stack structure; Deposition of silica layer then is to cover second lateral wall substrate, second dielectric layer and first dielectric layer after the described etching; Last etching silicon dioxide constitutes the side wall layer stack structure.
Fig. 5 A～5D for etching the 3rd dielectric layer in the grid structure of the explanation embodiment of the invention to obtain the second manufacturing process schematic diagram of side wall, as shown in the figure, with the technology of deposition-etching silicon dioxide layer and silicon nitride/silicon oxynitride layer in turn is example, described the 3rd dielectric layer of deposition-etching also can comprise with the step that forms side wall: at first, shown in Fig. 5 A, deposition of silica layer 51 and silicon nitride/silicon oxynitride layer 53 in turn; Subsequently, shown in Fig. 5 B～5C, the silicon dioxide layer 51 of the described grid layer of etching upper surface and silicon nitride/silicon oxynitride layer 53 in turn; At last, shown in Fig. 5 D, the silicon dioxide layer and the silicon nitride/silicon oxynitride layer of described second dielectric layer of etching and grid layer side surface.
A kind of grid structure provided by the invention, comprise be positioned at suprabasil first dielectric layer of semiconductor, be positioned at the grid on described first dielectric layer and be positioned on the described grid second dielectric layer and around the 3rd dielectric layer of described grid and described second dielectric layer, described the 3rd dielectric layer covers the sidewall of described second dielectric layer to small part.
The described second dielectric layer material comprises a kind of or its combination in silicon dioxide, silicon nitride, the silicon oxynitride, is preferably silicon nitride; Described the 3rd dielectric layer comprises silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride, or a kind of in the stepped construction that constitutes of silicon dioxide, silicon oxynitride and/or silicon nitride and silicon dioxide and silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide; The thickness of described second dielectric layer is determined according to process conditions and product requirement.Preferably, the thickness of described second dielectric layer is slightly less than or equals the thickness of a kind of or its combination layer in silicon dioxide, silicon nitride, the silicon oxynitride in the described side wall layer stack structure.
By controlling the thickness of second dielectric layer, make side wall to the small part that obtains behind described the 3rd dielectric layer of etching cover the sidewall of described second dielectric layer, can avoid the exposure of gate electrode side surface polysilicon, guarantee that after the grid structure manufacturing is finished reactant does not contact with the gate electrode side surface when forming the silicon Germanium source leakage.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (10)
1. grid structure manufacture method comprises:
On the semiconductor-based end, form first dielectric layer;
Deposition grid layer, this grid layer covers described first dielectric layer;
Deposit second dielectric layer, this second dielectric layer covers described grid layer;
Described second dielectric layer of etching and grid layer;
Deposit the 3rd dielectric layer, this 3rd dielectric layer covers described second dielectric layer and grid layer;
Described the 3rd dielectric layer of etching.
2. grid structure manufacture method according to claim 1 is characterized in that: the described first dielectric layer material comprises the silicon dioxide of silicon dioxide or doping hafnium.
3. grid structure manufacture method according to claim 1 and 2 is characterized in that: described grid layer material comprises polysilicon.
4. grid structure manufacture method according to claim 1 is characterized in that: the described second dielectric layer material comprises a kind of or its combination in silicon dioxide, silicon nitride, the silicon oxynitride.
5. grid structure manufacture method according to claim 1, it is characterized in that: described the 3rd dielectric layer comprises silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride, or a kind of in the stepped construction that constitutes of silicon dioxide, silicon oxynitride and/or silicon nitride and silicon dioxide and silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide.
6. according to claim 4 or 5 described grid structure manufacture methods, it is characterized in that: the thickness of described second dielectric layer is less than or equal to the thickness of a kind of or its combination layer in silicon dioxide, silicon nitride, the silicon oxynitride in described the 3rd dielectric layer stepped construction.
7. grid structure, comprise be positioned at suprabasil first dielectric layer of semiconductor, be positioned at the grid on described first dielectric layer and be positioned on the described grid second dielectric layer and around the 3rd dielectric layer of the described grid and second dielectric layer, described the 3rd dielectric layer covers the sidewall of described second dielectric layer to small part.
8. grid structure according to claim 7 is characterized in that: the described second dielectric layer material comprises a kind of or its combination in silicon dioxide, silicon nitride, the silicon oxynitride.
9. grid structure according to claim 7, it is characterized in that: described the 3rd dielectric layer comprises silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride, or a kind of in the stepped construction that constitutes of silicon dioxide, silicon oxynitride and/or silicon nitride and silicon dioxide and silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide.
10. according to Claim 8 or 9 described grid structures, it is characterized in that: the thickness of described second dielectric layer is less than or equal to the thickness of a kind of or its combination layer in silicon dioxide, silicon nitride, the silicon oxynitride in described the 3rd dielectric layer stepped construction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100421481A CN101330006A (en) | 2007-06-18 | 2007-06-18 | Gate structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100421481A CN101330006A (en) | 2007-06-18 | 2007-06-18 | Gate structure and manufacturing method thereof |
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| CN101330006A true CN101330006A (en) | 2008-12-24 |
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| CNA2007100421481A Pending CN101330006A (en) | 2007-06-18 | 2007-06-18 | Gate structure and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427026A (en) * | 2011-07-12 | 2012-04-25 | 上海华力微电子有限公司 | Optimized removing method of hard mask of polycrystalline grid silicon oxide |
| CN105453264A (en) * | 2013-08-22 | 2016-03-30 | 德州仪器公司 | Improved silicide formation by improved SiGe faceting |
| CN108231812A (en) * | 2018-01-24 | 2018-06-29 | 德淮半导体有限公司 | Transistor and its manufacturing method and cmos image sensor |
-
2007
- 2007-06-18 CN CNA2007100421481A patent/CN101330006A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427026A (en) * | 2011-07-12 | 2012-04-25 | 上海华力微电子有限公司 | Optimized removing method of hard mask of polycrystalline grid silicon oxide |
| CN102427026B (en) * | 2011-07-12 | 2014-10-01 | 上海华力微电子有限公司 | Optimized removing method of hard mask of polycrystalline grid silicon oxide |
| CN105453264A (en) * | 2013-08-22 | 2016-03-30 | 德州仪器公司 | Improved silicide formation by improved SiGe faceting |
| CN105453264B (en) * | 2013-08-22 | 2019-05-03 | 德州仪器公司 | Improve silicide by improved SiGe facet to be formed |
| CN108231812A (en) * | 2018-01-24 | 2018-06-29 | 德淮半导体有限公司 | Transistor and its manufacturing method and cmos image sensor |
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Open date: 20081224 |