CN102414806B - 管芯连接监控系统及方法 - Google Patents

管芯连接监控系统及方法 Download PDF

Info

Publication number
CN102414806B
CN102414806B CN200980159010.7A CN200980159010A CN102414806B CN 102414806 B CN102414806 B CN 102414806B CN 200980159010 A CN200980159010 A CN 200980159010A CN 102414806 B CN102414806 B CN 102414806B
Authority
CN
China
Prior art keywords
pad
bga
monitoring
coupled
tube core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200980159010.7A
Other languages
English (en)
Other versions
CN102414806A (zh
Inventor
J.S.塞尔维斯特
R.H.霍奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of CN102414806A publication Critical patent/CN102414806A/zh
Application granted granted Critical
Publication of CN102414806B publication Critical patent/CN102414806B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/70—Testing of connections between components and printed circuit boards
    • G01R31/71—Testing of solder joints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54—Testing for continuity
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/55—Testing for incorrect line connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种用于监控管芯连接的系统包括接合至基底的管芯和耦合至所述管芯的监控垫的连接指示器电路。所述连接指示器电路被配置成检测所述监控垫的连接故障。监控与所述管芯的监控垫相对应的信号，并且响应于所述被监控的信号的变化提供与所述监控垫相关联的垫连接故障的指示。

Description

管芯连接监控系统及方法
背景技术
集成电路设计一般涉及通过诸如光刻法之类的工艺在单个硅晶片上产生大量的集成电路。晶片被锯成单独的芯片（即，管芯），每个芯片都包括集成电路的副本。每个管芯或芯片都被安装在诸如球栅阵列或“BGA”的基底上。BGA通常充当用于管芯集成电路的基底或封装。当管芯被以“倒装芯片”的方式安装时，管芯被通过丝焊或通过在其接合垫上的焊料块连接至BGA。“倒装芯片”是能够在没有任何丝焊的情况下被以“正面向下”的方式直接附着或接合至BGA的管芯。倒装芯片具有在其上通常形成焊料块的经预处理的接合垫，使倒装芯片的正面向下的附件能够通过例如超声或回流焊接工艺接触在BGA上。
由于加载在BGA、印刷电路板(PCB)、和/或管芯自身上的各种诸如周期的机械和热之类的应力的原因，在倒装芯片和丝焊管芯二者中的焊接点可能破裂。机械装载可以是由例如在运输期间的振动所引起的，并且在正常操作期间发生热应力。破裂的焊接点能够使管芯上的接合垫变得与BGA分离或以其他方式松开，导致了在管芯集成电路与BGA和/或印刷电路板之间的断开或间歇的电连接。为了减少与破裂的焊接点相关联的故障，经常用不被管芯集成电路使用的假接合垫代替功能接合垫。假接合垫通常位于在诸如角之类的较高应力的区域中和/或在较大的温度波动的区域中的管芯上。因此，如果假接合垫与BGA触点之间的焊接点(倒装芯片或丝焊的)变得破裂、松开或以其他方式损坏了，则不会危及管芯上的集成电路的性能。
然而，对焊接点的损坏未必限于在管芯的高应力区域中的假焊接点。与功能接合垫相关联的焊接点也可能变得破裂、松开或以其他方式被损坏。例如，尽管破裂的焊接点可能最初发生在管芯的角处，但是破裂状况趋于朝着管芯的中心向内传播，从而危及功能或非假接合垫，并且导致到管芯集成电路的断开或间歇电连接。
一般地，对管芯焊接点的这些相同类型的应力和损坏也适用于在BGA与印刷电路板之间的焊接点。因此，在BGA与PCB触点之间的破裂和损坏的焊接球接点能够同样地导致到管芯集成电路的断开或间歇电连接。
附图说明
现将参考附图、通过示例的方式对本实施例进行描述，其中：
图1a示出了根据实施例的、在管芯被倒装芯片安装到基底的情况下的管芯连接监控系统的示例；
图1b示出了根据实施例的、在管芯被丝焊至基底的情况下的图1a的管芯连接监控系统的示例；
图2示出了根据实施例的连接指示器电路；
图3示出了根据实施例的、在导电通路中具有示例性中断的连接指示器电路；
图4示出了根据实施例的管芯连接监控系统的另一示例；
图5示出了根据实施例的、与在导电通路中具有示例性中断的图4的管芯监控系统相符的连接指示器电路；
图6示出了根据实施例的管芯连接监控系统的另一示例；
图7示出了根据实施例的管芯连接监控系统的另一示例；
图8示出了根据实施例的监控管芯连接的方法的流程图。
具体实施方式
问题综述和解决方案
如上文所指出的那样，将管芯附着至下面的基底(例如，球栅阵列，或“BGA”)所伴随的一个问题是可由管芯接合垫与BGA连接点之间的破裂的焊接点导致的间歇的和/或断开的电连接。当管芯被以“倒装芯片”的方式安装至BGA时或当其被丝焊至BGA时可能会发生这个问题。这个问题同样地可适用于将BGA附着至下面的印刷电路板(PCB)的焊接点。
本公开的实施例使用管芯监控系统和方法来检测这些问题。例如，在一个实施例中，用于监控管芯连接的系统包括接合至诸如BGA之类的基底的管芯。连接指示器电路被耦合至管芯的监控垫并且被配置成检测监控垫的连接故障。当监控垫变得与基底触点不耦合和/或当基底触点变得与下面的印刷电路板不耦合时这两种情况下，可能发生连接故障。
在另一实施例中，用于监控管芯连接的系统包括接合至球栅阵列(BGA)的管芯，其中BGA被接合至印刷电路板(PCB)。管芯上的监控垫被通过BGA耦合至地，并且被进一步地通过管芯上的上拉电阻器耦合至电压轨（voltage rail）。锁存器存储监控垫的连接故障指示。当将监控垫耦合至BGA触点的焊接点出故障时、和/或当将BGA触点耦合至PCB上的接地连接的焊接点出故障时，可发生连接故障，其中的任一个都引起接地连接中的中断。
在再一实施例中，监控管芯连接的方法包括监控与管芯的监控垫相对应的信号并且响应于信号的变化提供与监控垫的垫连接故障的指示。这种方法还适用于存在通过指示与监控垫中的任何一个或多个监控垫相关联的垫连接故障而串联耦合的多个监控垫的情况。
说明性的实施例
图1a示出了管芯连接监控系统100的实施例的示例。图1a中的管芯被表示为安装至基底(BGA 112)的“倒装芯片”管芯104。然而，管芯也可以是通过丝焊132连接至基底的丝焊管芯130，如图1b中所示出的那样。要注意的是，尽管在本文中主要针对以倒装芯片的方式安装的管芯对实施例进行了描述，但是该描述以类似的方式适用于丝焊管芯。
参考图1a，系统100包括布置在倒装芯片管芯104之上的连接指示器电路102。倒装芯片104是在其上已经由半导体材料制造了一个或多个功能集成电路106的管芯或芯片。除一个或多个集成电路106之外，倒装芯片104还包括在功能上与一个或多个集成电路106隔离或不同的集成连接指示器电路102。安置到管芯垫110(在倒装芯片104的顶面上)上的焊料块108被用来将倒装芯片104直接地附着至或接合至诸如球栅阵列(BGA)112之类的基底。因为管芯垫110和焊料块108是在倒装芯片104的顶面上，所以倒装芯片104被翻转并且被以“正面向下”方式安装至BGA 112。焊料块108例如通过超声或回流焊接工艺将管芯垫110耦合至BGA触点114。
管芯连接监控系统100还可包括通过焊球118耦合至BGA 112的印刷电路板(PCB)116。焊球118被焊接至BGA 112上的PCB触点120并且被焊接至PCB 116。在BGA 112的一侧上的每个BGA触点114通常被通过导电通路122穿过BGA 112耦合至BGA 112的另一侧上的对应的PCB触点114。
管芯垫110通常是提供到倒装芯片管芯104(或丝焊管芯130；图1b)的集成电路106的接入的功能垫。然而，在某些实例下，管芯垫110可以不是与倒装芯片104的集成电路106相关联的功能垫。作为替代，管芯垫110可以是与倒装芯片104的连接指示器电路102相关联的监控垫124。在这样的情况下，监控垫124被耦合至连接指示器电路102并且形成连接指示器电路102的导电通路126的一部分。
图2图示了连接指示器电路102的一个实施例。这个实施例与图1a和1b中所示出的管芯连接监控系统100实施例一致，并且其图示了其中通过连接指示器电路102来监控单个监控垫124的情况。连接指示器电路102包括具有经由导电通路126(图1a和3)、通过监控垫124耦合至地204的输入端202的锁存器200。尽管至监控垫124的接地连接204可以起源在别处，但是在这个实例中，接地连接起源在PCB 116上并且被经由包括PCB 116、焊球118、BGA 112上的PCB触点120、BGA 112上的BGA触点114、以及监控垫124上的焊料块108的导电通路126电耦合至监控垫124和锁存器200。
锁存器200的输入端202也被通过上拉电阻器R 208耦合至电压轨(Vcc) 206。锁存器200表示具有使其能够存储信息的一个位的两个稳定状态的电子电路。一般而言，锁存器200是其输出端210状态取决于当前输入信号和先前输入信号二者的时序逻辑电路。锁存器200被配置成基于在输入端202处从监控垫124所接收的输入信号来改变其在输出端210处的状态。输出系统212被通信地耦合至锁存器200以便生成和/或以其他方式发送指示垫连接故障的信号。在图1至7的实施例中，输出系统212包括在生产/测试期间可用的和/或以其他方式通知客户电子设备的即将发生的故障的计算机设备。输出系统212还可以包括机载系统(例如，布置在PCB 116上和/或以其他方式形成PCB 116的一部分)。表示输出系统212的计算机设备也可以包括其中安装了PCB 116的计算机，从而提供了计算机设备系统故障的可视的或其它类型的指示。输出系统212也可以被配置成在PCB 116的闪速存储器中设置标志以便于记录和跟踪垫连接故障。
现参考图2和3两者，在工作中，导电通路126在204处接地，从而使得在锁存器200的输入端202处的输入信号是低的、或接地。如果在监控垫124的焊料块108处的焊接点出故障(或者如果丝焊132出故障，图1b)，则导致监控垫124与BGA触点114不耦合，或者在间歇故障(例如连接变得间歇)的情况下，电流将被阻止沿着通路126流动(即，电路将断开)。导电通路126中的中断一般由中断300和中断302图示在图3中。当至地204的导电通路126被中断或变得不耦合时，在锁存器200的输入端202处的输入信号被经由上拉电阻器R 208上拉至电压轨Vcc。这使锁存器200改变其在输出端210处的输出状态。锁存器200的输出状态的变化指示已经发生了垫连接故障。来自锁存器200的输出210被发送给输出系统212(计算机设备)以提供垫连接故障的通知。
垫连接故障可以归因于沿着导电通路126的任何地方的中断。在所公开的实施例中，集成到倒装芯片管芯104(或丝焊管芯130，图1b)上的连接指示器电路102允许在倒装芯片104(或丝焊管芯130，图1b)上的监控垫124处、以及在使接地连接与监控垫124（完全和/或间歇）不耦合的沿着电路102的导电通路126的任何其它故障处的垫故障的检测。因此，垫故障可以是在监控垫124与BGA触点114之间的焊接点(即，焊料块)中的中断、在丝焊132中的中断、在穿过BGA 112的导电通路122中的中断、在PCB触点120与PCB 116之间的焊接点(即，焊球118)中的中断、在PCB 116上的导电通路中的中断等等中的任何一个或多个的故障的指示。
图4图示了管芯连接监控系统100的实施例，其中：多个监控垫124可以被串联链接并且被通过集成到倒装芯片104上的连接指示器电路102同时监控。此外，图4中的实施例示出了串联链接的、在基底(BGA 112)与PCB 116之间的多个焊接点能够同样地被连接指示器电路102同时监控。图5示出了根据实施例的、与在导电通路126中具有示例性中断500和502的图4的管芯监控系统相符的连接指示器电路102。如在前面的实施例中那样，倒装芯片104上的连接指示器电路102允许在倒装芯片104上的监控垫124处、以及在使接地连接与监控垫124（完全和/或间歇）不耦合的沿着电路102的导电通路126的任何其它故障处的垫故障的检测。在这里，垫故障可以是在监控垫124a、124b以及124c和它们相应的BGA触点114之间的焊接点(即，焊料块108)中的中断、在丝焊中的中断、在BGA触点114与PCB触点120之间的BGA 112上的导电通路126中的中断、在沿着PCB触点120与PCB 116之间的通路126的焊接点(即，焊球118)中的中断、在PCB 116上的导电通路126中的中断等等中的任何一个或多个的故障的指示。
图6图示了管芯连接监控系统100的实施例，其中：沿着不同的导电通路126a和126b串联链接的多个监控垫124被集成到倒装芯片104上的连接指示器电路102同时监控。图7通过示出能够通过连接指示器电路102在任何配置中沿着任何数量的导电通路126(126a-126d)监控任何数量的监控垫124提供了对这个和其它实施例的更全面的说明。在图7中所图示的实施例中，各种监控垫124被以不同的数量和配置布置在倒装芯片104的角C1、C2、C3以及C4上。然而，如先前所指出的那样，监控垫124可以被正如所愿地定位在机械、热和/或其它应力很可能引起倒装芯片104与诸如BGA 112之类的下面的基底之间的焊接点中的中断的倒装芯片104上的任何地方。沿着每条导电通路126a-126d耦合至监控垫124并且耦合至锁存器200的是各内部上拉电阻器Ra、Rb、Rc以及Rd。如在先前实施例中那样，每个监控垫124或监控垫124的串联串被接地204至PCB 116并且被耦合至相应的内部上拉电阻器Ra、Rb、Rc以及Rd。然而，要注意的是，地可以被定位于除了PCB 116上以外的地方。
在工作中，如果沿着特定导电通路126a-126d的监控垫124出故障，则用于那条通路的电路将断开，并且在到用于那条通路的锁存器200的输入端处的信号将被经由相应的上拉电阻器Ra、Rb、Rc以及Rd上拉，从而改变锁存器200的输出状态以指示在布置有相应的导电通路126和监控垫124的特定角C1、C2、C3或C4(或正被监控的其它位置)处已经发生了故障。因此，在各种实施例中，能够独立地监控在变化的导电通路配置中的任何数量的监控垫124。例如，输出系统212从锁存器200接收信号以指示沿着导电通路126a-126d的(一个或多个)监控垫的故障。
图8示出了根据实施例的监控管芯连接的方法800的流程图。方法800通常与针对图1-7在上文中所讨论的管芯连接监控系统100的实施例相关联。方法800起始于方框802，其中监控与倒装芯片管芯104(或丝焊管芯130)的监控垫相对应的信号。监控包括将监控垫耦合至锁存器。监控垫还被通过监控垫与BGA触点之间的焊接点耦合至地。监控垫还被通过上拉电阻器耦合至电压轨Vcc，从而使得如果焊接点被断开则监控垫的电压电平将从地电位改变为Vcc。监控垫也可以与另外的监控垫串联耦合，其中在串联的一端上的监控垫被耦合至地，而在串联的另一端上的不同的监控垫被耦合至锁存器并且通过上拉电阻器耦合至Vcc。
方法800在方框804处继续，其中响应于信号的变化指示已经发生了与监控垫相关联的垫连接故障。在监控垫与另外的监控垫串联的情况下，响应于信号的变化，垫连接故障的指示与监控垫和另外的监控垫中的至少一个相关联。垫连接故障的指示是基于当到地的连接在沿着监控垫与地之间的导电通路的任何地方被中断时发生的监控垫的电压增加。
方法800进一步包括监控耦合至与监控垫相关联的导电通路的锁存器的输出信号，如在方框806处所示出的那样。在方法800的方框808处，响应于正被监控的、与管芯的监控垫相对应的信号的变化，改变锁存器的输出信号。在方框810处，锁存器的输出信号被发送给输出系统(例如，计算机设备)以提供垫连接故障的通知。

Claims (13)

1.一种用于监控管芯连接的系统，包括：
接合至基底的管芯；和
连接指示器电路，其被耦合至所述管芯的监控垫，并且被配置成检测所述监控垫的连接故障；
其中，所述连接指示器电路包括具有经由导电通路、通过监控垫耦合至地的输入端的锁存器，所述锁存器被配置成基于在所述输入端处从监控垫所接收的输入信号来改变其在输出端处的状态，所述锁存器的输出状态的变化指示已经发生了垫连接故障；
其中所述导电通路包括印刷电路板PCB、焊球、球栅阵列BGA上的PCB触点、BGA上的BGA触点、以及所述监控垫上的焊料块。
2.根据权利要求1所述的系统，其中，所述管芯包括：
集成电路；
将所述集成电路耦合至基底触点的功能接合垫；以及
在功能上与所述集成电路隔离的所述连接指示器电路。
3.根据权利要求1所述的系统，其中，所述连接指示器电路还包括到所述监控垫的地电位连接和在所述监控垫与电轨之间耦合的上拉电阻器，并且其中当所述地电位连接被中断时所述连接指示器电路检测到连接故障。
4.根据权利要求3所述的系统，其中，所述监控垫是串联耦合的所述管芯的n个监控垫中的第一个，并且所述上拉电阻器被耦合在第n个监控垫与所述电轨之间。
5.根据权利要求1所述的系统，其中，所述基底包括球栅阵列(BGA)，并且当所述监控垫变得与BGA触点不耦合时发生连接故障。
6.根据权利要求1所述的系统，其中，所述基底包括球栅阵列(BGA)，其具有在所述BGA的顶面上耦合至所述监控垫的BGA触点和在所述BGA的底面上耦合至PCB的印刷电路板(PCB)触点，其中所述BGA触点被穿过所述BGA耦合至所述PCB触点，并且其中当所述PCB触点变得与所述PCB不耦合时发生连接故障。
7.根据权利要求1所述的系统，其中，所述管芯选自包括倒装芯片管芯和丝焊管芯的组。
8.一种监控管芯连接的方法，包括：
监控与管芯的监控垫相对应的信号；和
响应于与所述监控垫相对应的所述信号的变化来指示与所述监控垫相关联的垫连接故障；
其中所述方法进一步包括：
监控耦合至与所述监控垫相关联的导电通路的锁存器的输出信号；
响应于与所述监控垫相对应的所述信号的所述变化，改变所述锁存器的所述输出信号；以及
将所述锁存器的所述输出信号发送给输出系统以提供所述垫连接故障的通知；
其中将所述导电通路被配置为包括印刷电路板PCB、焊球、球栅阵列BGA上的PCB触点、BGA上的BGA触点、以及监控垫上的焊料块。
9.根据权利要求8所述的方法，其中，所述监控垫被串联地耦合至所述管芯的多个另外的监控垫，所述方法进一步包括响应于所述信号的变化来指示与所述监控垫和所述另外的监控垫中的至少一个相关联的垫连接故障。
10.根据权利要求8所述的方法，进一步包括基于所述监控垫的电压增加来指示垫连接故障。
11.一种用于监控管芯连接的系统，包括：
接合至球栅阵列(BGA)的管芯；
接合至印刷电路板(PCB)的所述BGA；
所述管芯上的监控垫，其通过所述BGA耦合至地并且通过所述管芯上的上拉电阻器耦合至电压轨；以及
用于存储所述监控垫的连接故障指示的锁存器；所述锁存器具有经由导电通路、通过监控垫耦合至地的输入端，所述锁存器被配置成基于在所述输入端处从监控垫所接收的输入信号来改变其在输出端处的状态；所述锁存器的输出状态的变化指示已经发生了垫连接故障；
其中所述导电通路包括印刷电路板PCB、焊球、球栅阵列BGA上的PCB触点、BGA上的BGA触点、以及监控垫上的焊料块。
12.根据权利要求11所述的系统，进一步包括：
将所述监控垫耦合至第一BGA触点的第一焊接点；
将第二BGA触点耦合至所述PCB上的接地连接的第二焊接点，其中当所述第一和第二焊接点中的一个或两个出故障时发生连接故障，引起所述接地连接中的中断。
13.根据权利要求11所述的系统，其中，所述监控垫包括串联耦合的多个监控垫，并且其中所述串联中的第一个监控垫被通过所述上拉电阻器耦合至所述电压轨，并且所述串联中的最后一个监控垫被通过所述BGA耦合至地，并且所述锁存器存储所述多个监控垫中的任何一个的连接故障指示。
CN200980159010.7A 2009-04-30 2009-04-30 管芯连接监控系统及方法 Expired - Fee Related CN102414806B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2009/042230 WO2010126511A1 (en) 2009-04-30 2009-04-30 Die connection monitoring system and method

Publications (2)

Publication Number Publication Date
CN102414806A CN102414806A (zh) 2012-04-11
CN102414806B true CN102414806B (zh) 2014-06-25

Family

ID=43032447

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200980159010.7A Expired - Fee Related CN102414806B (zh) 2009-04-30 2009-04-30 管芯连接监控系统及方法

Country Status (5)

Country Link
US (1) US8829918B2 (zh)
CN (1) CN102414806B (zh)
DE (1) DE112009004562T5 (zh)
GB (1) GB2481738B (zh)
WO (1) WO2010126511A1 (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5152099B2 (ja) * 2009-05-18 2013-02-27 富士通株式会社 基板構造
GB2484211B (en) * 2009-07-24 2014-04-23 Hewlett Packard Development Co Active pin connection monitoring system and method
KR101912843B1 (ko) * 2011-08-02 2018-10-30 삼성디스플레이 주식회사 인쇄 회로 기판
US9412725B2 (en) 2012-04-27 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
JP5894515B2 (ja) * 2012-09-28 2016-03-30 株式会社東芝 半導体装置、寿命推定装置、寿命推定方法
CN103823149A (zh) * 2013-12-03 2014-05-28 华为技术有限公司 芯片检测系统及检测方法
US9867295B2 (en) * 2014-01-07 2018-01-09 Dell Products L.P. Ball grid array system
WO2016015189A1 (en) * 2014-07-28 2016-02-04 GM Global Technology Operations LLC Systems and methods for reinforced adhesive bonding
EP3086132B1 (de) * 2015-04-01 2018-05-02 Siemens Aktiengesellschaft Elektronisches bauelement mit mehreren kontaktstrukturen und verfahren zur überwachung von kontaktstrukturen eines elektronischen bauelements
JP2016223802A (ja) * 2015-05-27 2016-12-28 ファナック株式会社 製造不良や損傷・劣化を検出する機能を備えた電子部品およびプリント基板
US9910085B2 (en) * 2016-01-04 2018-03-06 International Business Machines Corporation Laminate bond strength detection
US10186476B2 (en) * 2016-11-07 2019-01-22 Qorvo Us, Inc. Semiconductor package with grounded fence to inhibit dendrites of die-attach materials
KR20190064098A (ko) * 2017-11-30 2019-06-10 에스케이하이닉스 주식회사 반도체 장치, 및 그의 리페어 동작방법
US10860408B2 (en) * 2018-05-03 2020-12-08 Microchip Technology Incorporated Integrity monitor peripheral for microcontroller and processor input/output pins
CN108957807A (zh) * 2018-08-08 2018-12-07 昆山龙腾光电有限公司 一种绑定检测系统及显示面板
EP3690867A1 (en) * 2019-01-30 2020-08-05 Siemens Aktiengesellschaft Fingerprinting of semiconductor die arrangements
US11815984B2 (en) * 2020-02-07 2023-11-14 Intel Corporation Error handling in an interconnect
CN112088406B (zh) * 2020-08-06 2023-10-03 长江存储科技有限责任公司 用于三维存储器的多管芯峰值功率管理
CN117577152A (zh) 2020-11-26 2024-02-20 长江存储科技有限责任公司 用于多管芯操作的动态峰值功率管理
DE102021209892A1 (de) * 2021-09-08 2023-03-09 Robert Bosch Gesellschaft mit beschränkter Haftung Elektronisches Steuergerät und Verfahren zum Überwachen von Lötverbindungen eines elektronischen Steuergeräts
DE102022212722A1 (de) 2022-11-28 2024-05-29 Robert Bosch Gesellschaft mit beschränkter Haftung Integriertes elektronisches Bauelement mit Montageerkennung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452502B1 (en) * 1998-10-15 2002-09-17 Intel Corporation Method and apparatus for early detection of reliability degradation of electronic devices
US6564986B1 (en) * 2001-03-08 2003-05-20 Xilinx, Inc. Method and assembly for testing solder joint fractures between integrated circuit package and printed circuit board
US20060194353A1 (en) * 2005-02-28 2006-08-31 Ridgetop Group, Inc. Method and circuit for the detection of solder-joint failures in a digital electronic package

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087842A (en) * 1996-04-29 2000-07-11 Agilent Technologies Integrated or intrapackage capability for testing electrical continuity between an integrated circuit and other circuitry
JP4246835B2 (ja) 1999-03-09 2009-04-02 ローム株式会社 半導体集積装置
US6940288B2 (en) * 2003-06-04 2005-09-06 Hewlett-Packard Development Company, L.P. Apparatus and method for monitoring and predicting failures in system interconnect
US6895353B2 (en) * 2003-06-04 2005-05-17 Hewlett-Packard Development Company, L.P. Apparatus and method for monitoring high impedance failures in chip interconnects
US7196294B2 (en) * 2005-02-28 2007-03-27 Ridgetop Group, Inc. Method and resistive bridge circuit for the detection of solder-joint failures in a digital electronic package
US7250784B2 (en) * 2005-06-29 2007-07-31 Marvell International Ltd. Integrated systems testing
US7394273B2 (en) * 2006-01-18 2008-07-01 International Business Machines Corporation On-chip electromigration monitoring system
US7573282B2 (en) * 2006-04-26 2009-08-11 Hewlett-Packard Development Company, L.P. Ball grid array connection monitoring system and method
US7648847B2 (en) * 2006-06-26 2010-01-19 Hamilton Sundstrand Corporation In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit
US20080144243A1 (en) 2006-12-19 2008-06-19 Ridgetop Group, Inc. Method and circuit for low-power detection of solder-joint network failures in digital electronic packages

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452502B1 (en) * 1998-10-15 2002-09-17 Intel Corporation Method and apparatus for early detection of reliability degradation of electronic devices
US6564986B1 (en) * 2001-03-08 2003-05-20 Xilinx, Inc. Method and assembly for testing solder joint fractures between integrated circuit package and printed circuit board
US20060194353A1 (en) * 2005-02-28 2006-08-31 Ridgetop Group, Inc. Method and circuit for the detection of solder-joint failures in a digital electronic package

Also Published As

Publication number Publication date
US8829918B2 (en) 2014-09-09
GB2481738A (en) 2012-01-04
GB2481738B (en) 2013-10-16
GB201115583D0 (en) 2011-10-26
DE112009004562T5 (de) 2012-09-20
CN102414806A (zh) 2012-04-11
US20120001642A1 (en) 2012-01-05
WO2010126511A1 (en) 2010-11-04

Similar Documents

Publication Publication Date Title
CN102414806B (zh) 管芯连接监控系统及方法
US6452502B1 (en) Method and apparatus for early detection of reliability degradation of electronic devices
US7759961B2 (en) Ball grid array connection monitoring system and method
CN102473659B (zh) 有效管脚连接监测系统和方法
US6274390B1 (en) Method and apparatus providing redundancy for fabricating highly reliable memory modules
KR100705634B1 (ko) 대규모 집적회로 패키지, 인터포저, 인터페이스 모듈,신호처리 대규모 집적회로 감시회로 및 인터페이스 모듈
US6288346B1 (en) System and method for easily inspecting a bonded state of a BGA/CSP type electronic part to a board
US7478741B1 (en) Solder interconnect integrity monitor
US20150276854A1 (en) Integrated circuit interconnect crack monitor circuit
KR20070077696A (ko) 반도체 테스트 장비의 고장을 검출하기 위한 테스트 장치및 방법
JP2018160521A (ja) 半導体装置
US20110140730A1 (en) Detection circuitry for detecting bonding conditions on bond pads
CN102290403B (zh) 模块基板、具有该基板的半导体模块及其制造方法
JP2005064355A (ja) 半導体装置およびその製造方法
JP2009239027A (ja) 不具合検出機能を備えた半導体装置
JP2009141082A (ja) 半導体装置
EP3285294B1 (en) Integrated circuit die having a split solder pad
CN103337487B (zh) 用于集成电路的附接的方法和装置
JPH0661428A (ja) 半導体集積回路
KR100214853B1 (ko) 노운 굳 다이 테스트용 패키지 및 그의 제조 방법
CN117712097A (zh) 一种晶圆级系统集成装配的测试电路以及测试方法
KR100234025B1 (ko) 적층형 모듈 테스트 장치
CN101707852A (zh) 布局方法与电路板
JP2006133072A (ja) 半導体装置
KR20060099745A (ko) 비지에이 패키지 검사장치

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140625