CN102388449A - 在半导体装置的金属化系统中提供超电迁移效能且减少敏感低k介电的劣化 - Google Patents

在半导体装置的金属化系统中提供超电迁移效能且减少敏感低k介电的劣化 Download PDF

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Publication number
CN102388449A
CN102388449A CN2010800121646A CN201080012164A CN102388449A CN 102388449 A CN102388449 A CN 102388449A CN 2010800121646 A CN2010800121646 A CN 2010800121646A CN 201080012164 A CN201080012164 A CN 201080012164A CN 102388449 A CN102388449 A CN 102388449A
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CN
China
Prior art keywords
dielectric material
layer
copper
thermochemical
silicon
Prior art date
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Pending
Application number
CN2010800121646A
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English (en)
Chinese (zh)
Inventor
O·奥威尔
J·霍哈格
F·福斯特尔
A·普罗伊塞
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN102388449A publication Critical patent/CN102388449A/zh
Pending legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/093Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/20Cleaning during device manufacture
    • H10P70/23Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/20Cleaning during device manufacture
    • H10P70/27Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
    • H10W20/0526Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by thermal treatment thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/093Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/097Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/906Cleaning of wafer as interim step

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
CN2010800121646A 2009-02-27 2010-02-22 在半导体装置的金属化系统中提供超电迁移效能且减少敏感低k介电的劣化 Pending CN102388449A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102009010844.0A DE102009010844B4 (de) 2009-02-27 2009-02-27 Bereitstellen eines verbesserten Elektromigrationsverhaltens und Verringern der Beeinträchtigung empfindlicher dielektrischer Materialien mit kleinem ε in Metallisierungssystemen von Halbleiterbauelementen
DE102009010844.0 2009-02-27
PCT/EP2010/001091 WO2010097190A1 (en) 2009-02-27 2010-02-22 Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices

Publications (1)

Publication Number Publication Date
CN102388449A true CN102388449A (zh) 2012-03-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010800121646A Pending CN102388449A (zh) 2009-02-27 2010-02-22 在半导体装置的金属化系统中提供超电迁移效能且减少敏感低k介电的劣化

Country Status (6)

Country Link
US (1) US8153524B2 (https=)
JP (1) JP2012519373A (https=)
KR (1) KR20120052190A (https=)
CN (1) CN102388449A (https=)
DE (1) DE102009010844B4 (https=)
WO (1) WO2010097190A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103871959A (zh) * 2012-12-17 2014-06-18 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
CN108231736A (zh) * 2016-12-22 2018-06-29 格芯公司 用于触点和互连金属化集成的腐蚀和/或蚀刻保护层

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* Cited by examiner, † Cited by third party
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DE102008063417B4 (de) * 2008-12-31 2016-08-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Lokale Silizidierung an Kontaktlochunterseiten in Metallisierungssystemen von Halbleiterbauelementen
US8710660B2 (en) * 2012-07-20 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid interconnect scheme including aluminum metal line in low-k dielectric
US9373579B2 (en) * 2012-12-14 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Protecting layer in a semiconductor structure
US20150206798A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure And Method of Forming
US10515896B2 (en) 2017-08-31 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for semiconductor device and methods of fabrication thereof
CN114664656A (zh) 2020-05-22 2022-06-24 北京屹唐半导体科技股份有限公司 使用臭氧气体和氢自由基的工件加工

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US20070037374A1 (en) * 2005-08-15 2007-02-15 Kabushiki Kaisha Toshiba Semiconductor device and its manufacturing method
US20070173073A1 (en) * 2006-01-24 2007-07-26 Frank Weber Porous silicon dielectric
CN101051631A (zh) * 2006-04-04 2007-10-10 台湾积体电路制造股份有限公司 集成电路的内联机结构、镶嵌式结构以及半导体结构
US20080286966A1 (en) * 2007-05-15 2008-11-20 Joerg Hohage Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment

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US6259160B1 (en) * 1999-04-21 2001-07-10 Advanced Micro Devices, Inc. Apparatus and method of encapsulated copper (Cu) Interconnect formation
JP4034227B2 (ja) * 2002-05-08 2008-01-16 Necエレクトロニクス株式会社 半導体装置の製造方法
US6869878B1 (en) * 2003-02-14 2005-03-22 Advanced Micro Devices, Inc. Method of forming a selective barrier layer using a sacrificial layer
US7268074B2 (en) * 2004-06-14 2007-09-11 Enthone, Inc. Capping of metal interconnects in integrated circuit electronic devices
JP4903374B2 (ja) * 2004-09-02 2012-03-28 ローム株式会社 半導体装置の製造方法
US7309658B2 (en) * 2004-11-22 2007-12-18 Intermolecular, Inc. Molecular self-assembly in substrate processing
DE102005035740A1 (de) * 2005-07-29 2007-02-08 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer isolierenden Barrierenschicht für eine Kupfermetallisierungsschicht
DE102005057057B4 (de) * 2005-11-30 2017-01-05 Advanced Micro Devices, Inc. Verfahren zur Herstellung einer isolierenden Deckschicht für eine Kupfermetallisierungsschicht unter Anwendung einer Silanreaktion
US20070287294A1 (en) 2006-06-08 2007-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structures and methods for fabricating the same
JP5204964B2 (ja) * 2006-10-17 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2008172051A (ja) * 2007-01-12 2008-07-24 Nec Electronics Corp 半導体装置およびその製造方法
JP2009016520A (ja) * 2007-07-04 2009-01-22 Tokyo Electron Ltd 半導体装置の製造方法及び半導体装置の製造装置
US7776740B2 (en) * 2008-01-22 2010-08-17 Tokyo Electron Limited Method for integrating selective low-temperature ruthenium deposition into copper metallization of a semiconductor device
US7928003B2 (en) * 2008-10-10 2011-04-19 Applied Materials, Inc. Air gap interconnects using carbon-based films

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Publication number Priority date Publication date Assignee Title
US20070037374A1 (en) * 2005-08-15 2007-02-15 Kabushiki Kaisha Toshiba Semiconductor device and its manufacturing method
US20070173073A1 (en) * 2006-01-24 2007-07-26 Frank Weber Porous silicon dielectric
CN101051631A (zh) * 2006-04-04 2007-10-10 台湾积体电路制造股份有限公司 集成电路的内联机结构、镶嵌式结构以及半导体结构
US20080286966A1 (en) * 2007-05-15 2008-11-20 Joerg Hohage Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103871959A (zh) * 2012-12-17 2014-06-18 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
CN108231736A (zh) * 2016-12-22 2018-06-29 格芯公司 用于触点和互连金属化集成的腐蚀和/或蚀刻保护层
CN108231736B (zh) * 2016-12-22 2021-12-28 格芯美国公司 用于触点和互连金属化集成的腐蚀和/或蚀刻保护层

Also Published As

Publication number Publication date
JP2012519373A (ja) 2012-08-23
DE102009010844B4 (de) 2018-10-11
KR20120052190A (ko) 2012-05-23
DE102009010844A1 (de) 2010-09-02
US20100221911A1 (en) 2010-09-02
US8153524B2 (en) 2012-04-10
WO2010097190A1 (en) 2010-09-02

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Application publication date: 20120321