CN102376692A - 隔离外延调制装置 - Google Patents

隔离外延调制装置 Download PDF

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CN102376692A
CN102376692A CN2011102805815A CN201110280581A CN102376692A CN 102376692 A CN102376692 A CN 102376692A CN 2011102805815 A CN2011102805815 A CN 2011102805815A CN 201110280581 A CN201110280581 A CN 201110280581A CN 102376692 A CN102376692 A CN 102376692A
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isolation
modulating
semiconductor device
extension
substrate
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Y·李
S·H·沃德曼
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Intersil Corp
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Intersil Inc
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Abstract

一种隔离外延调制装置包括：基片；势垒结构，其形成在所述基片上；隔离外延区，其形成在所述基片的上方并且由所述势垒结构与所述基片电隔离；半导体器件，所述半导体器件位于隔离外延区中；以及调制网络，其形成在所述基片上并且与所述半导体器件电耦合。所述装置还包括接合焊盘和接地焊盘。隔离外延区与接合焊盘和接地焊盘中的至少一个电耦合。所述半导体器件和所述外延调制网络配置为调制输入电压。

Description

隔离外延调制装置
相关申请的交叉引用
本申请涉及下面的共同代决的美国专利申请，所有的申请均通过引用并入本文中：
于2010年8月20日提交的标题为“基片泵静电放电装置”且在本文中称为’360申请的美国临时专利申请序列号61/375,360(代理人案件号SE-2841-TD)。因此，本申请要求美国临时专利申请No.61/375,360的优先权。
于2010年12月18日提交的标题为“基片泵静电放电装置”且在本文中称为’625申请的美国临时专利申请序列号61/424,625(代理人案件号SE-2841-TD)。因此，本申请要求美国临时专利申请No.61/424,625的优先权。
技术领域
本发明涉及电子系统和半导体器件领域。
背景技术
传统的基片泵对于大尺寸的夹存在低效率的问题。例如，传统泵中的中央梳形物具有比边缘梳形物高的有效体电阻并且在边缘梳形物之前被触发。中央梳形物比边缘梳形物接通得强并且在边缘梳形物到达故障阈值之前到达故障阈值。随着传统基片泵夹的尺度变大，这种不一致性变得更加严重。因此，降低了传统基片泵夹的总体效率。
发明概述
在一个实施方案中，提供隔离外延调制装置。所述隔离外延调制装置包括：基片；势垒结构，其形成在所述基片上；隔离外延区，其形成在所述基片的上方并且通过所述势垒结构与所述基片电隔离；半导体器件，所述半导体器件位于所述隔离外延区中；调制网络，其形成在所述基片上并且与所述半导体器件电耦合；接合焊盘；以及接地焊盘。所述隔离外延区与所述接合焊盘和所述接地焊盘中的至少一个电耦合。所述半导体器件和外延调制网络配置为调制输入电压。
附图说明
理解附图仅描述了示例性实施方案且因此不视为对范围的限制，通过使用附图将另外具体地、详细地描述示例性实施方案，在附图中：
图1为隔离外延调制装置的一个实施方案的框图。
图2为隔离外延调制装置的一个实施方案的简化电路图。
图3为示例性隔离外延调制装置的俯视图。
图4为隔离外延调制装置的一个实施方案的简化剖视图。
图5为描述包括至少一个示例性隔离外延调制装置的系统的一个实施方案的高级框图。
图6为描述制造隔离外延调制装置的方法的一个实施方案的流程图。
依据通常的惯例，绘制各个所述的特征不是按比例决定而是绘制用于强调与示例性实施方案相关的特定特征。
附图中主要部件的附图标记的列表
100调制装置
102隔离外延区
104接合焊盘
106外延调制网络
108接地焊盘
110半导体器件
122基片
124势垒结构
200隔离外延调制装置
202隔离外延区
204I/O焊盘
206外延调制网络
208接地焊盘
210半导体器件
212电阻
214电容
216晶体管
218体环
220P+环
222基片
224势垒结构
301体带
303梳形物
315栅极
317源极区
319漏极区
318体环
320GND P+环
322基片
324埋层
328势阱
330NTUB
401体带
403梳形物
418体环
500隔离外延调制装置
505系统
509功率变流器
511电源
513处理电路
发明详述
在下面的详细说明中，参考附图，附图构成说明的部分，并且在附图中通过示例具体的示例性实施方案的方式显示。然而，应当理解的是，可以使用其它的实施方案，并且可以进行逻辑的、机械的、和电气的改动。此外，在绘制的图和说明书中提供的方法不应解释为限制各个动作可以实施的次序。因此，不应在限制的意义上看待下面的详细说明。
图1为隔离外延调制装置100的一个实施方案的框图。调制装置100包括与接合焊盘104耦合的隔离外延区102、外延调制网络106和接地焊盘108。在本文中描述的示例性实施方案中，接合焊盘104实施为输入/输出(I/O)焊盘。然而，应当理解的是，在其它的实施方案中接合焊盘104可以不同的方式实施。例如，接合焊盘104可以实施为输入焊盘、输出焊盘、输入/输出(I/O)焊盘、信号焊盘、测试焊盘、可编程焊盘或电源焊盘(例如，与Vdd、Vcc、Vee、Vss等耦合)。
另外，半导体器件110位于隔离外延区102中。半导体器件110与接地焊盘108、外延调制网络106和接合焊盘104耦合。能够实施为半导体器件110的示例性半导体器件包括但不限于金属氧化物半导体场效应晶体管(MOSFET)、双极结型晶体管(BJT)、或横向扩散金属氧化物半导体(LDMOS)器件。示例性半导体器件可以在例如互补金属氧化物半导体(CMOS)技术、双极结型晶体管-CMOS(BiCMOS)技术、绝缘体上硅(SOI)技术、金刚石上硅(SOD)、蓝宝石上硅(SOS)或双极CMOS-DMOS(BCD)技术中实施。示例性半导体器件可以在硅锗(SiGe)、硅锗碳(SiGeC)、砷化镓(GaAs)、氮化镓(GaN)以及其它III-V半导体技术中实施，但不限于这些技术。
半导体器件110和外延调制网络106一起调制输入电压。因此，当接合焊盘104实施为信号焊盘(例如，输入焊盘、输出焊盘或输入/输出焊盘)时，隔离外延调制装置100可用于例如保护电路免受电压瞬变或电流尖峰脉冲，诸如静电放电(ESD)电流、和电过载(EOS)。然而，应当理解的是，还可以构思调制装置100的其它用途。例如，当接合焊盘104实施为电源焊盘时，隔离外延调制装置100可以实施为ESD电源夹网络(例如，两个电源管脚之间的ESD网络)。
调制装置100中还包括有基片122和势垒结构124。基片可由所属领域技术人员公知的任何适当的材料构成，诸如硅、石英或其它材料。势垒结构124将外延区102与基片122电隔离。因此，隔离外延区102的电位可独立于基片122而被修正。例如，在一些实施方案中，势垒结构124实施为将区102与基片122分隔开的偏压埋层。然而，应当理解的是，在其它实施方案中可以不同方式实施势垒结构124。例如，在一些实现中，势垒结构124为氧化物绝缘材料。势垒结构的侧边可以为硅冶金结结构、浅槽隔离(STI)结构、深槽(DT)结构、通晶片转接(TWV)结构或通硅转接(TSV)结构。浅槽隔离和深槽(DT)隔离结构可以填充有氧化物、聚酰亚胺或多晶硅材料。另外，基片122和接地焊盘108不一定与相同的电位耦合。然而，在一些实施方案中，基片122耦合到与接地焊盘108相同的电位。
图2为隔离外延调制装置200的一个实施方案的电路图。在图2所示的实施方案中，调制装置200实施为对ESD电流进行分流的保护装置。半导体器件210实施为作为对ESD电流进行分流的主保护装置的n沟道金属氧化物半导体(NMOS)。特别地，在该特定实施方案中，NMOS为多梳形物NMOS。也就是说，NMOS由如图3所示且在下文进行描述的多个平行晶体管构成。
另外，在图2所示的实施方案中，外延调制网络206包括电阻212和电容214，电阻212和电容214形成电阻器-电容器(RC)鉴别器。外延调制网络206还包括一个或多个晶体管216。在该实施例中一个或多个晶体管216也实施为NMOS。电容214表示I/O焊盘204和半导体器件210与晶体管216的栅极节点之间的电容。电阻212表示从半导体器件210和晶体管216的栅极到接地(GND)208的电阻。电阻器元件可以为硅电阻器、金属电阻器或多晶硅电阻器。电容器元件可以为硅冶金结、金属-绝缘体-金属(MIM)电容器、MOS电容器、垂直平行板(VPP)电容器或垂直天然板电容器(VNP)。
势垒结构224将隔离外延区202与基片222电隔离。隔离外延区102还包括体环218，体环218在图2中描述为节点。然而，体环218环绕半导体器件210，如下文更加详细说明的。体环218还包括位于具有相邻源极区的半导体器件210的梳形物之间的带，如下文更加详细说明的。体环218和P+环220之间的有效电阻在图2中标记为Rb。
在ESD电流开始时，由于I/O焊盘204和GND焊盘208之间的电阻/电容(RC)耦合，NMOS半导体器件210的栅极电位和晶体管216的栅极电位升高。由晶体管216传导的电流流过Rb并且抬高体环218的电位。NMOS半导体器件210的源极与GND焊盘208连接，因此正向偏压管体到源极的结。结果，以相对较低的电压触发NMOS半导体器件210的梳形物。换句话说，NMOS半导体器件210的梳形物接通或者开始以相对较低的电压进行分流。NMOS半导体器件210的源极管体结的正向偏压也有助于促进NMOS梳形物的均匀接通。NMOS半导体器件210的体电位由环绕NMOS半导体器件210的体环218控制。一旦梳形物被接通，梳形物开始对ESD电流进行分流从而保护其它部件免受ESD电流破坏。随着管体区的升高，晶体管的电流驱动提高。MOSFET电流驱动与(VG-VT)成比例，此处VG为栅极电压，而VT为阈值电压。由于管体升高，MOSFET体效应降低，引起较低的阈值电压。该效应也称作MOSFET反向体效应或动态阈值MOSFET效应。由于VT降低，晶体管的电流驱动Ids使得提高了对ESD电流进行放电的能力。
图3为调制装置200的简化剖视图。隔离调制装置200包括P+基片322、覆盖P+基片322的N+埋层324和覆盖N+埋层324的隔离外延区202(也标记且称作P体区)。调制装置200还包括N+势阱328，N+势阱328与N+埋层324耦合且封闭隔离外延区202。N+埋层324和N+势阱328在该实施方案中用作势垒结构以将隔离外延区202与基片222电隔离。在一些实施方案中，埋层324经由势阱328和NTUB 330与接地焊盘208耦合。在其它的实施方案中，埋层324浮动、偏压或与电源或基准电压耦合。在埋层324和N+势阱或边缘328为绝缘体结构的情况下，如果埋层324中的材料为多晶硅，则可发生偏压。在埋层324和势阱328为绝缘体的情况下，当埋层324中的材料为二氧化硅、金刚石或石英时，未建立起偏压条件。在一些实施方案中，势阱328可抵接或延伸越过埋层324。势阱328可以为深槽(DT)、或延伸到埋层324或在埋层324的下边缘下方延伸的通硅转接(TSV)。
在该实施例中，在各对相邻源极N+梳形物303之间添加专用P+体带301，如上文讨论的。P+体带301和N+梳形物303形成在隔离外延区202中。另外，N+势阱328与NTUB 330电耦合，NTUB 330与接合焊盘304或接地焊盘308电耦合。
体带301与源极N+梳形物303分隔开。每个梳形物303包括栅极315、源极区317和与焊盘(即，I/O焊盘204)连接的漏极区319。因此，体带301位于相邻源极区317之间。在该实施例中，利用金属材料将体带301与体环318连接。各栅极侧源极边缘与体环318之间的有效体电阻近似等于另一栅极侧源极边缘和体环318之间的有效体电阻。该有效体电阻在本文中称为且在图3中标记为Rf。因此，任一栅极侧源极边缘和GND P+环320之间的有效电阻为Rb+Rf，此处Rb为体环318和GND P+环320之间的电阻。在一些实施方案中，GND P+环320可与接地焊盘208耦合。在其它的实施方案中，GND P+环320与单独的接地电位耦合。
因此，体电阻横过NMOS半导体器件210内的不同梳形物303均匀地分布并且均匀地分布在各个梳形物303内。即，体电阻不依赖于位置。此外，由于体电阻的均匀分布，所有梳形物303均几乎同时被触发且以近似相等的强度接通。
另外，由于体电阻的均匀分布，所有的梳形物203几乎同时到达故障阈值。故障阈值为能够无误地进行分流的最大电流的点。因此，调制装置200能够达到与理论上的最大故障阈值近似相等的故障阈值。改进的故障阈值是由于这样的事实：调制装置200不限于较快地到达故障阈值的梳形物203的较低故障阈值。换句话说，如果体电阻不均匀地分布，则一些梳形物将更快地到达故障阈值。因此，调制装置200的故障阈值将受到梳形物203中的一个的早期故障阈值的限制。然而，通过近似均匀地分布体电阻，所有的梳形物203近似均匀地共享负荷并且几乎在相同的时间点到达故障阈值，这反过来增加了调制装置200的总故障阈值。
此外，由于均匀的体电流流动，与不具有均匀体电流流动的调制装置相比，MO 202的有效体电阻减小，并且保持电压Vsp升高，这使得能具有更多的操作净空高度。可通过Rtrig和Ctrig单独地调节触发电压Vt1，使得对Vsp的影响最小或没有影响。
图4为示例性隔离外延调制装置200的俯视图。从图4中可以看出，体环418包括位于梳形物403的相邻源极区之间的多个体带401。如图4中进一步显示的，各栅极侧源极边缘和体环418之间的有效体电阻近似等于另一栅极侧源极边缘和体环418之间的有效体电阻。
本文描述的隔离外延调制装置的实施方案可用于例如任意集成电路或装置中，以保护输入/输出管脚免受ESD电流的破坏。例如，图5为描述包括至少一个隔离外延调制装置500的示例性系统505的高级框图。系统505包括与电源511耦合的功率变流器509和处理电路513。
在图5所示的示例性实施方案中，功率变流器509并入了如上所述的至少一个隔离外延调制装置500-1。功率变流器509与电源511耦合且配置为将从电源接收到的功率转换成处理电路513可用的级别和极性。例如，功率变流器509可实施为直流(DC)-直流变流器以将从电源511接收到的功率的电压水平降低或升高到处理电路513所需的水平。可选择地，功率变流器509可实施为交流(AC)-直流(DC)变流器。
另外，在一些实施方案中，功率变流器509为高电流和高电压功率变流器。然而，本文中描述的隔离外延调制装置的实施方案在其它功率器件、高功率密度和高效DC功率变流器和高电压AC/DC功率变流器中实施。例如，隔离外延调制装置可在片外驱动器中实施。
在一个实施方案中，电源511在装置505的外部。例如，电源511可以为经由电插座与装置505耦合的主电源。在其它的实施方案中，电源511可以在装置505的内部，诸如电池。
另外，在该实施方案中，处理电路513还包括在处理电路513中保护电路的输入/输出管脚的至少一个隔离外延调制装置500-2。处理电路513和隔离外延调制装置500-2可在单片集成电路中或在包含单独管芯的共封装装置中实施。
装置505可以实施为任何电子装置，诸如手机、计算机、导航装置、微处理器、高频装置等。因此，处理电路的实施取决于特定的装置。例如，当装置505实施为手机时，处理电路513可以包括所属领域技术人员公知的数字信号处理器(DSP)、模拟-数字(ADC)转换器、射频发送接收放大器、存储器电路和微处理器。隔离外延调制装置500-2配置为保护处理电路513免受电压和/或电流尖峰脉冲的破坏，诸如静电放电(ESD)电流。
图6为描述制造诸如上文描述的示例性隔离外延调制装置的隔离外延调制装置的示例性方法的流程图。在块602处，势垒结构形成在基片上。例如，在一些实施方案中，偏压的埋层形成在基片上。在块604处，利用所属领域技术人员公知的技术将外延区形成在势垒结构上。势垒结构封闭外延区并且将外延区与基片电隔离。
在块606处，调制网络形成在基片上。例如，可以利用所属领域技术人员公知的技术来形成电阻器、电容器和晶体管。在块608处，利用所属领域技术人员公知的技术将诸如具有上述多个平行晶体管的示例性半导体器件的半导体器件形成在隔离外延区中。半导体器件与调制网络耦合。在实施具有多个平行晶体管的半导体器件的实施方案中，方法600任选地包括：在块610处，在隔离外延区中形成导电环。导电环环绕多个平行晶体管。在这样的实施方案中，方法600还任选地包括：在块612处，形成与导电环耦合的多个导电带。多个导电带中的每个形成在多个平行晶体管的相邻源极区之间。在块614处，接合焊盘形成在装置上。接合焊盘可以为信号焊盘或电源焊盘。接合焊盘与隔离外延区中的半导体器件电耦合。
尽管本文已经阐述且描述了特定实施方案，所属领域技术人员应当理解的是，预测实现相同目的的任何布置可以替代所示的特定实施方案。因此，明确地表明本发明仅受权利要求及其等同布置的限制。

Claims (27)

1.一种隔离外延调制装置，包括：
基片；
势垒结构，其形成在所述基片上；
隔离外延区，其形成在所述基片的上方并且由所述势垒结构与所述基片电隔离；
半导体器件，所述半导体器件位于所述隔离外延区中；
调制网络，其形成在所述基片上并且与所述半导体器件电耦合；
接合焊盘；以及
接地焊盘；
其中，所述隔离外延区与所述接合焊盘和所述接地焊盘中的至少一个电耦合；并且
其中，所述半导体器件和外延调制网络配置为调制输入电压。
2.如权利要求1所述的隔离外延调制装置，其中，所述半导体器件包括金属氧化物半导体场效应晶体管(MOSFET)、双极结型晶体管(BJT)和横向扩散金属氧化物半导体(LDMOS)器件中的一种。
3.如权利要求1所述的隔离外延调制装置，其中，所述调制网络包括电阻器-电容器(RC)鉴别器和晶体管。
4.如权利要求1所述的隔离外延调制装置，其中，所述半导体器件包括：
多个平行晶体管，其配置为对静电放电(ESD)电流进行分流，各所述晶体管具有栅极、漏极区和源极区；
其中，所述隔离外延调制装置进一步包括：
导电体环，其位于所述隔离外延区中并且环绕多个梳形物，所述导电体环具有一个或多个体带，其中各个所述体带位于所述多个梳形物的相邻源极区之间；以及
接地环，其环绕所述体环且与所述体环耦合。
5.如权利要求4所述的隔离外延调制装置，其中，所述接地环和所述接地焊盘与相同的接地电位耦合。
6.如权利要求1所述的隔离外延调制装置，其中，所述接合焊盘实施为输入焊盘、输出焊盘、输入/输出(I/O)焊盘或电源焊盘中的一种。
7.如权利要求1所述的隔离外延调制装置，其中，所述半导体器件以互补金属氧化物半导体(CMOS)技术、双极结型晶体管-CMOS(BiCMOS)技术、绝缘体上硅(SOI)技术、金刚石上硅(SOD)、蓝宝石上硅(SOS)或双极CMOS-DMOS(BCD)技术中的一种实施。
8.如权利要求1所述的隔离外延调制装置，其中，所述势垒结构包括：
埋层；以及
势阱，其与所述埋层耦合以封闭所述隔离外延区。
9.如权利要求8所述的隔离外延调制装置，其中，所述势阱包括硅冶金结结构、浅槽隔离(STI)结构、深槽(DT)结构、通晶片转接(TWV)结构或通硅转接(TSV)结构中的一个。
10.一种集成电路，包括：
基片；
处理电路，其形成在所述基片上；
势垒结构，其形成在所述基片上；
隔离外延区，其形成在所述基片的上方并且由所述势垒结构与所述基片电隔离；
半导体器件，所述半导体器件位于所述隔离外延区中；
调制网络，其形成在所述基片上并且与所述半导体器件电耦合；以及
信号焊盘，其与所述隔离外延区电耦合；
其中，所述半导体器件和外延调制网络配置为保护所述处理电路免受电流尖峰脉冲破坏。
11.如权利要求10所述的集成电路，其中，所述半导体器件包括多梳形物n沟道金属氧化物半导体(NMOS)，所述梳形物中的每个包括栅极、漏极区和源极区。
12.如权利要求11所述的集成电路，进一步包括位于所述隔离外延区中的导电结构，所述导电结构与接地电位耦合并且包括：
导电环，其环绕所述半导体器件；以及
多个导电带，其与所述导电环耦合，各导电带位于所述多个梳形物的相邻源极区之间。
13.如权利要求10所述的集成电路，其中，所述调制网络包括电阻器、电容器和晶体管。
14.如权利要求10所述的集成电路，进一步包括接地焊盘，所述接地焊盘与所述隔离外延区电耦合。
15.如权利要求10所述的集成电路，进一步包括电源焊盘，所述电源焊盘与所述隔离外延区电耦合。
16.如权利要求10所述的集成电路，其中，所述势垒结构包括氧化物绝缘材料。
17.一种系统，包括：
处理电路；
功率变流器，其与电源耦合且配置为将来自所述电源的功率转换成可由所述处理电路使用的功率水平或极性；以及
一个或多个隔离外延调制装置，其配置为调制输入电压，所述一个或多个隔离外延调制装置中的每个与所述处理电路和所述功率变流器中的对应一个耦合；
其中，所述一个或多个隔离外延调制装置中的每个包括：
基片；
势垒结构，其形成在所述基片上；
隔离外延区，其形成在所述基片的上方并且由所述势垒结构与所述基片电隔离；
半导体器件，所述半导体器件位于所述隔离外延区中；
调制网络，其形成在所述基片上并且与所述半导体器件电耦合；以及
接合焊盘，其与所述隔离外延区耦合；
其中，所述半导体器件和所述外延调制网络配置为调制所述输入电压。
18.如权利要求17所述的系统，其中，所述半导体器件包括金属氧化物半导体场效应晶体管(MOSFET)。
19.如权利要求17所述的系统，其中，所述调制网络包括耦合到所述接合焊盘和接地电位之间的晶体管。
20.如权利要求17所述的系统，其中，所述半导体器件包括：
多个平行晶体管，各所述晶体管具有栅极、漏极区和源极区；
其中，所述隔离外延调制装置中的每个进一步包括位于所述隔离外延区中的导电结构，所述导电结构包括：
导电环，其环绕所述多个平行晶体管；以及
多个导电带，其与所述导电环耦合，各所述导电带位于所述多个平行晶体管的相邻源极区之间。
21.如权利要求17所述的系统，其中，所述一个或多个隔离外延调制装置包括与所述功率变流器耦合的第一隔离外延调制装置和与所述处理电路耦合的第二隔离外延调制装置；
其中，所述第一隔离外延调制装置中的所述接合焊盘包括电源焊盘，并且所述第二隔离外延调制装置中的所述接合焊盘包括信号焊盘。
22.如权利要求17所述的系统，其中，所述电源包括电池。
23.一种制造隔离外延调制装置的方法，所述方法包括：
在基片上形成势垒结构；
在所述势垒结构上形成外延区；
在隔离外延区中形成半导体器件；
在所述基片上形成调制网络，所述调制网络与所述半导体器件耦合；
形成接合焊盘，所述接合焊盘与所述隔离外延区中的所述半导体器件电耦合。
24.如权利要求23所述的方法，其中，所述形成接合焊盘包括形成信号焊盘和电源焊盘中的一个。
25.如权利要求23所述的方法，其中，形成所述势垒结构包括：
形成偏压埋层；以及
形成由所述偏压埋层耦合的偏压势阱。
26.如权利要求23所述的方法，其中，在所述隔离外延区中形成半导体器件包括形成多个平行晶体管。
27.如权利要求26所述的方法，所述方法进一步包括：
在所述隔离外延区中形成导电环，所述导电环环绕所述多个平行晶体管；以及
形成与所述导电环耦合的多个导电带，各个所述带电带形成在所述多个平行晶体管的相邻源极区之间。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104508827A (zh) * 2012-06-28 2015-04-08 天工方案公司 高电阻率基底上的双极型晶体管
US10263072B2 (en) 2012-06-28 2019-04-16 Skyworks Solutions, Inc. Integrated RF front end system

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8362564B2 (en) 2010-08-20 2013-01-29 Intersil Americas Inc. Isolated epitaxial modulation device
US20130168772A1 (en) * 2011-12-28 2013-07-04 United Microelectronics Corporation Semiconductor device for electrostatic discharge protecting circuit
US9577035B2 (en) * 2012-08-24 2017-02-21 Newport Fab, Llc Isolated through silicon vias in RF technologies
US8981483B2 (en) * 2013-03-28 2015-03-17 Semiconductor Manufacturing International (Shanghai) Corporation ESD protection structure and ESD protection circuit
JP6600491B2 (ja) * 2014-07-31 2019-10-30 エイブリック株式会社 Ｅｓｄ素子を有する半導体装置
US10439024B2 (en) 2016-06-13 2019-10-08 Texas Instruments Incorporated Integrated circuit with triple guard wall pocket isolation
JP6824667B2 (ja) * 2016-08-31 2021-02-03 ラピスセミコンダクタ株式会社 半導体装置
US10819110B2 (en) * 2018-02-27 2020-10-27 Globalfoundries Inc. Electrostatic discharge protection device
US11380759B2 (en) * 2020-07-27 2022-07-05 Globalfoundries U.S. Inc. Transistor with embedded isolation layer in bulk substrate
KR20230096669A (ko) * 2021-12-23 2023-06-30 주식회사 엘엑스세미콘 정전 방지 회로

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293087A (en) 1963-03-05 1966-12-20 Fairchild Camera Instr Co Method of making isolated epitaxial field-effect device
US3780426A (en) 1969-10-15 1973-12-25 Y Ono Method of forming a semiconductor circuit element in an isolated epitaxial layer
CA1155969A (en) 1980-09-26 1983-10-25 Clement A.T. Salama Field effect transistor device and method of production thereof
DE3272436D1 (en) 1982-05-06 1986-09-11 Itt Ind Gmbh Deutsche Method of making a monolithic integrated circuit with at least one isolated gate field effect transistor and one bipolar transistor
US4673965A (en) 1983-02-22 1987-06-16 General Motors Corporation Uses for buried contacts in integrated circuits
US5087579A (en) 1987-05-28 1992-02-11 Texas Instruments Incorporated Method for fabricating an integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias
US5399507A (en) * 1994-06-27 1995-03-21 Motorola, Inc. Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications
EP0788151A1 (en) 1996-01-31 1997-08-06 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Method of fabricating junction-isolated semiconductor devices
US5940258A (en) 1996-02-29 1999-08-17 Texas Instruments Incorporated Semiconductor ESD protection circuit
US6034399A (en) * 1997-03-06 2000-03-07 Lockheed Martin Corporation Electrostatic discharge protection for silicon-on-insulator
US5949094A (en) 1997-08-29 1999-09-07 Texas Instruments Incorporated ESD protection for high density DRAMs using triple-well technology
JP3419672B2 (ja) 1997-12-19 2003-06-23 富士通株式会社 半導体装置及びその製造方法
DE19859502C2 (de) 1998-12-22 2000-12-07 Siemens Ag Sperrschicht-Feldeffekttransistor mit höher dotiertem Verbindungsgebiet
US6411480B1 (en) 1999-03-01 2002-06-25 International Business Machines Corporation Substrate pumped ESD network with trench structure
US6404269B1 (en) * 1999-09-17 2002-06-11 International Business Machines Corporation Low power SOI ESD buffer driver networks having dynamic threshold MOSFETS
US6452220B1 (en) 1999-12-09 2002-09-17 The Regents Of The University Of California Current isolating epitaxial buffer layers for high voltage photodiode array
US6469362B2 (en) 2000-02-15 2002-10-22 Winbond Electronics Corp. High-gain pnp bipolar junction transistor in a CMOS device and method for forming the same
TW454327B (en) 2000-08-08 2001-09-11 Taiwan Semiconductor Mfg ESD protection circuit triggered by substrate
US6667865B2 (en) 2000-09-11 2003-12-23 Texas Instruments Incorporated Efficient design of substrate triggered ESD protection circuits
TW473979B (en) 2001-03-28 2002-01-21 Silicon Integrated Sys Corp ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with substrate triggering technique
US6475848B1 (en) 2001-06-15 2002-11-05 National Semiconductor Corporation Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor
US6784065B1 (en) 2001-06-15 2004-08-31 National Semiconductor Corporation Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor
US6465768B1 (en) 2001-08-22 2002-10-15 United Microelectronics Corp. MOS structure with improved substrate-triggered effect for on-chip ESD protection
TW510040B (en) 2001-10-19 2002-11-11 Taiwan Semiconductor Mfg Electrostatic discharge protection circuit for substrate-triggered high-low voltage input/output circuit
US6933567B2 (en) 2002-05-15 2005-08-23 Texas Instruments Incorporated Substrate pump ESD protection for silicon-on-insulator technologies
TW550779B (en) 2002-07-01 2003-09-01 Macronix Int Co Ltd Substrate charging circuit for input/output electrostatic discharge protection and its protection method
TW548824B (en) 2002-09-16 2003-08-21 Taiwan Semiconductor Mfg Electrostatic discharge protection circuit having high substrate triggering efficiency and the related MOS transistor structure thereof
US6900969B2 (en) 2002-12-11 2005-05-31 Texas Instruments Incorporated ESD protection with uniform substrate bias
US6724592B1 (en) 2002-12-11 2004-04-20 Pericom Semiconductor Corp. Substrate-triggering of ESD-protection device
JP4597618B2 (ja) * 2004-09-15 2010-12-15 Ｏｋｉセミコンダクタ株式会社 半導体装置およびその製造方法
US7129545B2 (en) * 2005-02-24 2006-10-31 International Business Machines Corporation Charge modulation network for multiple power domains for silicon-on-insulator technology
US7042028B1 (en) 2005-03-14 2006-05-09 System General Corp. Electrostatic discharge device
US7289307B2 (en) 2005-11-09 2007-10-30 Silicon Integrated Systems Corp. High voltage ESD circuit by using low-voltage device with substrate-trigger and gate-driven technique
US7348643B2 (en) 2006-06-06 2008-03-25 Texas Instruments Incorporated Semiconductor dual guardring arrangement
US7605431B2 (en) * 2006-09-20 2009-10-20 Himax Technologies Limited Electrostatic discharge protection apparatus for semiconductor devices
US8362564B2 (en) 2010-08-20 2013-01-29 Intersil Americas Inc. Isolated epitaxial modulation device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104508827A (zh) * 2012-06-28 2015-04-08 天工方案公司 高电阻率基底上的双极型晶体管
CN104508827B (zh) * 2012-06-28 2018-11-09 天工方案公司 高电阻率基底上的双极型晶体管
US10263072B2 (en) 2012-06-28 2019-04-16 Skyworks Solutions, Inc. Integrated RF front end system
US10522617B2 (en) 2012-06-28 2019-12-31 Skyworks Solutions, Inc. Integrated RF front end system

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