CN102365735B - 用于半导体器件的互连结构及相关的制造方法 - Google Patents

用于半导体器件的互连结构及相关的制造方法 Download PDF

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CN102365735B
CN102365735B CN201080013955.0A CN201080013955A CN102365735B CN 102365735 B CN102365735 B CN 102365735B CN 201080013955 A CN201080013955 A CN 201080013955A CN 102365735 B CN102365735 B CN 102365735B
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semiconductor device
conductive pad
stacked
marginal portion
conduction
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CN102365735A (zh
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C·奇尔德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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GlobalFoundries Inc
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Abstract

本发明提供一种具有器件衬底(102)的半导体器件(50)。该半导体器件(50)包括形成为叠置在该器件衬底(102)上的导电垫(110)；形成为叠置在该导电垫(110)上且密封一空腔的导电平台(160)，其中，该导电平台(160)具有从该导电垫(110)延伸离开的边缘部分(162)及在该边缘部分(162)的上面的顶盖部分(170)；以及设置在该空腔中的缓冲材料(140)。

Description

用于半导体器件的互连结构及相关的制造方法
技术领域
本发明主题的实施方式大致上是关于适合用在半导体器件的互连结构。更具体而言，本发明主题的实施方式是关于用于半导体器件互连结构的弹性应力吸收器。
背景技术
背景技术包括用于将半导体芯片连接至电路板、其它器件、衬底等多种技术及互连结构。例如，经常使用焊珠(solder bead)将倒装芯片(flip chip)连接至外部电路。这些焊珠通常设置在倒装芯片的导电凹槽或端点且经回焊以形成用于连接至外部器件(如电路板)的珠粒。这些焊珠通常由铅或铅合金形成。最近，以银取代铅以减少废弃芯片对环境所产生的任何影响。
用于形成焊料连接的另一工艺为生成柱状互连件且在该柱状互连件顶面形成焊珠。该柱状互连件通常设置在半导体器件的接触垫上且向上延伸。可制作具有非常小节距的柱状互连件的数组以适应高密度应用。之后，该数组的焊珠可使用回焊技术与外部电路耦接。
当使用柱状互连件时，外部电路所施加的任何力会传导至该柱状互连件。该柱状互连件转而将该力传导至于该柱状互连件与该器件之间的耦接处的半导体器件。与直接设置在芯片的焊珠(使用传统技术)相比，柱状互连件具有更窄的基底，从而使施加在该半导体器件上的应力更大。所造成的应变可能会以各种非所欲的方式显现出来，如某些材料的裂化或剥离。
发明内容
本发明提供具有器件衬底的半导体器件。该半导体器件包括形成为叠置在该器件衬底上的导电垫；形成为叠置在该导电垫上且密封一空腔的导电平台，其中，该导电平台具有从该导电垫延伸离开的边缘部分及在该边缘部分上面的顶盖部分；以及设置在该空腔中的缓冲材料。
本发明亦提供具有器件衬底的半导体器件结构。该半导体器件结构包括形成为叠置在该器件衬底上的导电接触垫、设置在该接触垫上并经调适成响应于力而弹性变形的弹性块、实质上围绕该弹性块且与该弹性块耦接以及与该接触垫电耦接的导电平台、设置在该平台上面而与该平台电耦接且延伸至一末端的导电柱状互连件、以及形成在该末端上的焊珠。
本发明亦提供形成用于器件衬底的接触平台的方法。该方法包括提供具有导电接触组件、在该导电接触组件上面的钝化层、以及延伸穿过该钝化层且终止在该导电接触组件的凹槽的半导体器件结构；以弹性材料至少部分地填充该凹槽以获得经填充的凹槽；从该经填充的凹槽选择性地去除一部分弹性材料以形成位在该凹槽中的弹性垫，该弹性垫叠置在该导电接触组件上且与该钝化层分隔开；以及在该凹槽中形成导电平台以使该导电平台至少部分围绕该弹性垫。
此发明内容是用于简要说明概念的选集，这些概念将在下文中进一步详细说明。此发明内容非意欲指出所主张的发明主题的关键特征或基本特征，亦非意欲用作确定所主张的发明主题的范围的辅助。
附图说明
可通过参照详细说明及权利要求并结合下列附图更完整的理解本发明主题，其中，相似的参考符号在整个附图中是指相似的组件。
图1是具有应力吸收互连结构的群组的半导体器件的实施方式的透视图；
图2是具有弹性应力吸收器的互连结构的透视图；
图3是图2的互连结构的横截面示意图；
图4是图2的互连结构的顶视图；
图5至图14是显示包括弹性应力吸收器的例示性互连结构的形成的横截面示意图；以及
图15是在形成该弹性应力吸收器后的该互连结构的横截面示意图。
具体实施方式
以下详细说明仅在本质上说明而非意欲限制该主题的实施方式或这些实施方式的应用及使用。本文中所述的术语“例示性”意指“用作实例、例子或例证”。作为例示性的任意实施不必然被解读为更优于或更有利于其它实施的实施。再者，本文非意欲限于任何揭示在上文的技术领域、背景技术、发明内容或下文的实施方式的明示或暗示理论。
“耦接(couple)”——以下说明是指组件或节点或特征被“耦接”在一起。除非明白地另行说明，本文所述的“耦接”意指一个组件/节点/特征直接或间接地连接至(或直接或间接连通于)另一个组件/节点/特征，且不必然与直接机械连接相连接。应理解耦接的组件/节点/特征互相施加影响。因此，虽然图1的图解揭示了组件的一种例示性方案(scheme)，但是所揭示主题的实施方式中可存在其它的组件、器件、特征或组件。
“调整(adjust)”——某些组件、组件及/或特征被描述为可调整的或已调整的。除非明白地另行说明，本文所叙述的“调整”意指定位、改进、改变或设置组件或组件或组件或组件的一部分以适应环境及实施方式。在某些情况下，若对于实施方式所处环境为合适或有需要，则调整后组件或组件或组件或组件的一部分的位置、状态及/或状况可维持不变化。在某些情况下，若合适或有需要，则该组件或组件可更改、改变或改进为新位置、状态及/或状况。
“抑制”——本文所述的抑制是用于描述减小效应或最小化效应。当揭示一组件或特征被描述为抑制活动、移动或状况时，该组件或特征可完全防止结果或后果或将来的状态。另外，“抑制”亦可指反之则可能会发生的后果、性能及/或效应的降低或减少。藉此，当揭示一组件、组件或特征被指为可抑制结果或状态时，其不一定完全阻止或消除该结果或状态。
此外，某些用于以下说明中的术语亦仅作为参考，因此非意欲限制本发明。例如，“上部”、“下部”、“上方”及“下方”等术语是指附图中的方向，而附图中的参考架构是一致但为随意者。这些术语可包括上述特别提到的词语、这些词语的衍生物以及相似舶来词。类似地，除非文中另行说明，涉及结构的术语“第一”、“第二”及其它这些数字并非表示次序或顺序。
为了简洁起见，关于半导体器件制造的传统技术可能不在此详细说明。再者，本文所述的多种工作及工艺步骤可并入在具有本文未详细揭示的其它步骤或功能的更复杂的步骤或工艺。特别地，制造半导体是晶体管的多个步骤已广泛习知，因此，为了简洁起见，多个传统步骤仅简单说明或将全部省略而不提供习知工艺细节。
本文所揭示的技术及工艺可用以制造用于任何数量的半导体系器件(如晶体管器件、二极管、开关、传输线等)的互连件。另外，发明主题是关于控制塌陷芯片连接(controlled collapse chipconnection)，其经常使用在倒装芯片，且包括在下述的半导体器件结构的说明中。
对于使用柱状互连件技术的半导体器件而言，与缓冲垫或弹性垫类似的弹性应力吸收器可位在该柱状互连件下方以减少传送至该半导体器件的环绕区域的应力。该弹性应力吸收器较宜包括至少一个导电部分，藉此实现该半导体器件与该柱状互连件之间的电连接。在较佳实施方式中，弹性部分是并入至互连结构；该弹性部分在遭受应力时可发生弹性形变。因此，该柱状互连件所接收的力及应力在传送至该半导体器件之前会被吸收。
图1是具有多个互连结构60的半导体器件50的透视图。互连结构60可用于将半导体器件50与其它组件或外部电路耦接。互连结构60可提供耦接点，该耦接点不仅机械地将组件耦接在一起，亦提供导电沟道，通过该导电沟道，半导体器件50的特征可通过如外部电路板操作。其它器件亦可与半导体器件50耦接。
虽然基于例示的目的显示一定数量的互连结构60，惟不同实施例的确切数量可不同。另外，熟知本领域的技术人员将认识到额外的互连结构60可存在于半导体器件50的多种实施例中。再者，当对实施例适合时，不同集中度、排列、群组及形状可用在互连结构60。
图2是一个互连结构100的详细示意图。互连结构100除了别的组件还包括导电柱状互连件180及在柱状互连件180顶面的焊珠190。柱状互连件180较佳于导电平台160与互连结构100耦接。其它层、特征及/或组件可形成在柱状互连件180及/或焊珠190周围，但为了简洁而予以省略。另外，如上所述，其它互连结构可存在于单个半导体器件上。
图3是沿着图2的线3-3所取得的互连结构100的横截面示意图。互连结构100较佳包括，但不限于：器件衬底102、导电接触组件或接触垫110、第一层绝缘材料(如氮化物层)120、第二层绝缘材料(如氧化物层)130、弹性块140、粘合层150、导电平台160、柱状互连件180及焊珠190。导电平台160可包括边缘部分162及顶盖部分170。
本文所述的器件衬底102表示半导体器件50的一部分，该半导体器件50包括功能器件特征、导电线路、互连栓、电路组件等。换言之，器件衬底102包括任意操作特征及组件，以及相关的电连接及导电线路。例如，器件衬底102可包括不同材料的任何数量的层，如半导体材料层、介电质材料层、导电金属层等。这些不同材料层可用以形成主动器件(如晶体管)、电接触、夹层连接及其它通常会发现在半导体器件的特征。为了说明的简要，不在图中绘示器件衬底102的详细特征(每个器件的特征互相不同)。
器件衬底102可包括半导体材料，该半导体材料可使用广泛习知的技术及工艺步骤(如关于掺杂、光刻法及图案化、蚀刻、材料生长、材料沉积、表面平坦化等的技术及步骤)处理，此处将不详细说明。器件衬底102可使用绝缘体覆硅上(SOI)衬底来实现，其中，半导体材料设置在绝缘体材料层上，该绝缘体材料转而由载体芯片(未显示)支持。在替代实施例中，器件衬底102可使用块体硅衬底代替SOI衬底来实现。
虽然可使用任意适当的半导体材料，但是本实施例中，器件衬底102中的半导体材料是包括硅材料，其中，本文所述的术语“硅材料”包括普通单晶硅及通常用在半导体工业的相对纯的硅材料，以及与其它元素(如锗、碳等)混合的硅。另外，器件衬底102可包括锗、砷化镓等。
导电垫110可形成为覆盖在器件衬底102上。实际上，导电垫110相当于互连结构100的一个电节点、端口(port)或连接点，且导电垫110表示用在互连结构100的电界面。例如，导电垫110可为形成在器件衬底102上的晶体管器件的源极、栅极或漏极所用的接触区域。导电垫110可使用任意所欲的技术及/或工艺形成。较佳地，导电垫110包括导电金属材料，如纯铜或铜合金。然而，可视实施例的需要而使用其它导电材料，如铝及铝合金、银及银合金等。虽然导电垫110是显示为沿着器件衬底102延伸一定长度，但导电垫110的确切尺寸可视实施例的不同而改变。再者，可将多于一个的柱状互连件180与单个导电垫110耦接。
氮化物层120及氧化物层130位在导电垫110上方且围绕边缘部分162。氮化物层120可由任意适当的氮化物化合物(包括硅氮化物)形成。如下文更详细的说明，氮化物层120定义至少凹槽(如含有导电平台160的凹槽132)的一部分。氮化物层120可沿着导电垫110以所欲的程度延伸，以与互连结构100的其它特征适当地作用。氮化物层120可具有约4000至5000埃(Angstrom)的厚度。在某些实施例中，氮化物层120视需要可更薄或更厚。
氧化物层130至少部分覆盖在氮化物层120上，且其形状与氮化物层120的形状一致。因此，氧化物层130较佳为与氮化物层120类似地定义相同凹槽132的至少一部分。氧化物层130可由任意适当的材料形成，如氧化硅或低k材料。氧化物层130可具有约4000至5000埃的厚度，惟在某些实施例中，氧化物层130视需要可更薄或更厚。
氮化物层120及氧化物层130可作为电绝缘体。另外，虽然揭示了两个钝化层，但更多或更少的钝化层可存在于不同实施例中选择用于该实施例的互连结构100中。因此，某些实施方式可具有单个钝化层，而其它实施方式可具有两个或更多个钝化层。
弹性部分或弹性块140可形成为覆盖导电垫110。如图所示，弹性块140位在导电平台160下方的空腔中。在某些实施例中，弹性块140直接形成在导电垫110上且与导电垫110相邻接。较佳地，弹性块140由具有线形弹性应力/应变机械特性的材料构成。因此，可适当地设计或组构弹性块140以使其在非负载状态下保持不变形的形状(如矩形块)。然而，当力施加在弹性块140时，弹性块140可响应于该力而发生弹性变形，当去除力时，弹性块140恢复至其未变形的形状。因此，弹性块140就像弹簧或缓冲垫，可通过弹性形变吸收应力。因此，弹性块140可称为缓冲块、缓冲材料、应力吸收组件等等。
因此，弹性块140较佳由显现这些机械特性以及易于成形的材料形成。这些类型的材料的其中一种为聚醯亚胺，较佳为易于制造的光敏聚醯亚胺。再者，弹性块140可视需要实现为具有由不同材料形成的多个不同层、部分或区域的复合结构。弹性块140是绘示为直方角柱，惟不需为特定尺度或比例。因此，可视需要使用其它尺寸及尺度。较佳地，弹性块140具有实质上四边形的形状。
弹性块140可具有厚度(即高度，从导电垫110上方测量的延伸度)。较佳地，弹性块140的最大高度比氮化物层120与氧化物层130的总厚度小一适当的间隙，以让具有所欲厚度的顶盖部分170可形成。因此，弹性块140较佳具有小于围绕的氮化物层120与氧化物层130的总高度的高度。在某些实施例中，弹性块140具有约600至1000埃的范围内的厚度。另外，弹性块140较佳与氮化物层120及氧化物层130隔开。在某些实施例中，此间隔可为约400至800奈米的范围内。
粘合层150可有助于将导电平台160粘合至弹性块140及导电垫110，如下文更详细的说明。因此，粘合层150位在导电平台160与弹性块140之间以及导电平台160与导电垫110之间。如图3所示，粘合层150较佳为形成在氮化物层120及氧化物层130的凹槽中，且覆盖弹性块140以及位在导电平台160的边缘部分162下方的导电垫110部分。因此，弹性块140的上表面及侧表面可由粘合层150覆盖。
粘合层150可包括铬或铬合金，或其它促进弹性块140与用于导电垫110的材料之间的粘合并能允许导电于其间的材料(如铜及/或铜合金)。粘合层150可通过溅镀工艺形成，以沉积在互连结构100上。粘合层150可具有实质上均匀的厚度，如20至40埃之间，但是该厚度在不同的实施例中可不同。
导电平台160较佳为形成在导电垫110及弹性块140上方。导电平台160包括边缘部分162及顶盖部分170。边缘部分162较佳为围绕弹性块140的弹性块140的整个高度。顶盖部分170较佳为覆盖边缘部分162及弹性块140，并密封弹性块140所在的空腔。如图3所示，凹槽132相当于由顶盖部分170、边缘部分162及导电垫110所定义的空间。在某些实施例中，边缘部分162可延伸至导电平台160的最大高度，而顶盖部分170仅为直接在弹性块140顶面的部分。因此，在不同的实施例中，导电平台160的各部分不同，但仍具有相同功能以及实质上相同的特征。导电垫110通过该粘合层与导电平台160电耦接。
边缘部分162较佳为形成在弹性块140及氮化物层120及氧化物层130之间的空间中。如图所示，边缘部分162可形成在粘合层150的顶面。在将粘合层150自导电垫110的表面去除的其它实施例中，边缘部分162可直接形成在导电垫110的表面上。粘合层150仍可形成弹性块140的侧壁与边缘部分162之间的表面。边缘部分162较宜向上延伸以与顶盖部分170耦接。
顶盖部分170可形成在弹性块140的顶面上，且如上所述，在某些实施例中，顶盖部分170亦形成在边缘部分162的顶面上。顶盖部分170较佳为被调适成覆盖弹性块140的实质上平坦的组件，且与导电垫110实质上平行地延伸。顶盖部分170的厚度在不同实施例中可不同。边缘部分162与顶盖部分170的在导电垫110上方的组合高度较佳为实质上等于氮化物层120及氧化物层130的高度。因此，弹性块140、粘合层150及导电平台160的组合较佳为填满显示于氮化物层120及氧化物层130中的凹槽。
顶盖部分170具有外边缘及内边缘。该外边缘或外边界为顶盖部分170的最大延伸限度。顶盖部分170横跨弹性块140而由边缘部分162支撑。因此，该内边缘为由弹性块140的外边缘所界定的边界，且在该内边界或内边缘内，顶盖部分170是通过粘合层150由弹性块140支撑。
边缘部分162及顶盖部分170较佳由高导电金属材料构成，如铜、铝、银、金或其合金。边缘部分162及顶盖部分170可整体形成一个连续的或整体的组件，或可形成两个连接或耦接在一起的不同组件。
柱状互连件180可形成在导电平台160的顶面上。如图所示，柱状互连件180较佳具有实质上圆柱形的形状。柱状互连件180可直接形成在顶盖部分170上、或在柱状互连件180与顶盖部分170之间形成一个或多个另外的导电层。较佳地，柱状互连件180由高导电金属材料形成，如铜、铝或其合金。实际上，柱状互连件180、导电平台160及导电垫110皆可由相同材料形成。
另外参照图4，可以看到柱状互连件180及顶盖部分170的顶视图，其中顶盖部分170的内边缘172以虚线标出。可以看出，柱状互连件180在其基底具有外径、外边缘184或外边界，其中该基底与导电平台160耦接。柱状互连件180的外边缘184可当成柱状互连件180与顶盖部分170之间的接触面积的底面积(footprint)。较佳地，柱状互连件180的外边缘184是被定义或界定为全部位在顶盖部分170的内边缘172内。因此，柱状互连件180较佳为在全部在弹性块140上的区域与顶盖部分170耦接。因此，在较佳实施例中，柱状互连件180的接触表面没有任一部分设置成覆盖在边缘部分162上。其它实施例可具有其它组构。
柱状互连件180可由其它材料围绕，如其它钝化或导电层及/或垫(视所实施的器件或电路的需要)。柱状互连件180可在其相对于导电垫110的顶部具有末端182。视所使用的连接技术的需要，末端182可为光滑者或具有纹理。焊珠190可形成在末端182上或柱状互连件180的顶部。焊珠190可由铅、银、锡或任意其它所欲的材料构成。
来自互连结构100与外部电路之间的连接的应力、或来自热膨胀差的应力可在焊珠190处被接收且传送通过柱状互连件180。传送通过柱状互连件180的应力或力转而施加在导电平台160上或由导电平台160所接收或经历。因为导电平台160与弹性块140耦接，扭力及压缩应力等应力可传送至弹性块140。弹性块140可响应于所接收的应力而发生弹性变形，藉此吸收所接收的应力且抑制贯穿互连结构100的传送。因此，可其它特征与接收自外部组件以及热膨胀的应力隔离以保护这些特征。
图5至图15是显示用于半导体器件的例示性互连结构的形成的横截面示意图。上述互连结构100可根据下述工艺制造。应理解不同实施例的形成可包括任意数量的其它或替代步骤，此处将不再赘述这些步骤。另外，用于标示图5至图15的某些特征的数字与上述特征的数字相同，惟在适当时增加300的数目。如下所述，亦可具有其它的特征及/或变形。
图5为处于在前端处理之后及形成互连结构之前的状态的半导体器件。图5为显示形成器件衬底402、导电垫410、氮化物层420及氧化物层430之后的整体制造工艺的中间状态。器件衬底402可包括不同材料的任何数量的层(如半导体层、电介质层、导电金属层等)及并入特征(如主动器件(如晶体管)、电接触、夹层连接以及其它通常用在半导体器件的特征)。另外，虽然揭示了具体的化合物，如氧化物、氮化物，但亦可使用其它材料，如低k及超低k电介质材料。氮化物420及氧化物430层可用作某些工艺的终止指示器或终止层(如下所述)。
当获得图5所示的结构之后，可选择性地去除材料以形成凹槽432，如图6所示。使用广泛知道的工艺技术选择性地自氮化物420及氧化物430层去除材料。例如，适当的图案化蚀刻掩膜可形成在430的上表面上，且该蚀刻掩膜可用在选择性地蚀刻氧化物层430及氮化物层420以定义凹槽432。较佳地，材料的去除是向下延伸至导电垫410。实际上，器件衬底402可能需要多个(如数十个、数百个、数千个或更多个)互连结构。因此，虽然图6仅显示用于一互连结构的一个凹槽432，但是为了对应多个互连结构，实际中的实施例可在氮化物层420及氧化物层430蚀刻凹槽数组。因此，此处及下文所述的用于制造弹性块及导电平台的工艺步骤可用于制造任意数量的半导体器件结构。
形成凹槽432之后，能以弹性材料500至少部分地填充凹槽432(如图7所示)。如上所述，弹性材料500可为光敏聚醯亚胺，其适合对应后续工艺步骤。
在某些实施例中，弹性材料500通过适当的沉积技术形成，如涂覆技术(如旋涂)。较佳地，保形地沉积弹性材料500以使其完全填满凹槽432。因此，在沉积步骤过程中，可将一些量的弹性材料500沉积在氧化物430层上方。图7说明了此过量的材料501(称为“过量层”)如何覆盖在氧化物层130上。至少部分填充凹槽432的弹性材料500的沉积是导致经填充的凹槽532。
该实施例继续进行一个或多个光刻步骤。关于这点，第8图揭示了光刻曝光步骤，在该步骤中弹性材料500(其为光敏材料)曝露至具有预定图案的辐射(如光)。例如在其上定义有适当的光掩膜的图案化玻璃层510的选择性曝光器件可设置在弹性材料500上。如图所示，电磁波谱的适当的部分的光512(不必为可见光)可通过图案化玻璃层510指向互连结构。
经调整的光514将会依照设置在图案化玻璃层510上的图案的设计而穿过图案化玻璃层510。经调整的光514可选择性通过或视需要过滤特定波长而具有改变自光512的特性。众所周知，经调整的光514可调整被曝光的敏弹性材料的特性。例示性实施例使用两个光刻步骤以选择性去除弹性材料500的一部分。如图8所示，在第一步骤中，经调整的光514被传送至弹性材料500在填充凹槽532的部分。如图9所示，被曝光的弹性材料500再以适当的显影剂化学作用显影，以除去一些位在填充凹槽532的弹性材料500。需注意图9所绘示的凹槽632表示因初始显影步骤而去除的弹性材料的部分。
之后，剩余弹性材料500可经受第二曝光及显影步骤。如图9所示，通过第二图案化玻璃层560的第二曝光可获得经调整的光562，而经调整的光562是沿着填充凹槽532的边缘被提供至弹性材料500。在以经调整的光562使弹性材料500曝光之后，将该曝光的材料显影以形成图10所示的弹性块540。
应理解虽然该例示性实施例绘示了在沿着凹槽732的边缘去除弹性材料500之前去除在凹槽632的弹性材料500的宽层，但是可以相反顺序实施操作以实现图10所示的相同结果。另外，虽然绘示及说明了双曝光光刻工艺，但亦可使用以循序渐进的选择性照射及/或控制的浓度以选择性去除弹性材料500的单个光刻工艺。再者，在某些实施例中，双曝光光刻工艺可包括在两个照射步骤之后的仅单个的显影步骤。用于选择性去除弹性材料500的确切技术在不同实施例中可不同，但较佳为导致形成与氮化物120及氧化物130层隔开的弹性块440(如图10所示)。
在形成弹性块之后，该实施例的方法接着附加粘合层450(如图11所示)。粘合层450可使用任意所欲的技术沉积，包括CVD或PVD(包括溅镀法)。较佳地，粘合层450围绕弹性块440。如上所述，粘合层450亦可形成在凹槽732中的导电垫410的顶面上。亦可产生粘合层材料的一些过量层451。沿着导电垫410形成的粘合层450的部分可选择性地被去除。
如图12所示，在形成粘合层450之后，导电材料530可形成在弹性块440上方。导电材料530通常为金属材料。在较佳实施例中，导电材料530包括铜或其合金。或者，导电材料530可包括，但不限于铝或其合金。
导电材料530可通过适当的沉积技术形成，如CVD或PVD技术。较佳地，保形地沉积弹性材料500以使其完全填满凹槽632、732，而同时围绕弹性块440及在弹性块440上。导电材料530的某些过量层531可形成在弹性材料500的过量层501及粘合层450的过量层451上。粘合层450较佳促进及有助于弹性块440与导电材料530之间的耦接。
在沉积导电材料530之后，可将多余材料自互连结构400去除(如图13所示)。更具体地，弹性材料的过量层部分501、粘合层的过量层451及导电材料的过量层531可通过研磨过量层501、531从氧化层430上去除。关于这点，可使用氧化层430作为终止层、终止标记、终端层或端点指针而通过化学机械研磨/平坦化(CMP)去除覆盖层部分。在CMP工艺之后，剩余导电材料530包括边缘部分462及顶盖部分470，其共同形成导电平台460。导电平台460具有上表面472。较佳地，导电平台460的高度与周围的氮化物420及氧化物430层的高度匹配。
如图14所示，在去除工艺之后，可在导电平台460上形成导电柱状互连件480。柱状互连件480较佳设置在顶盖部分470的上表面472上。柱状互连件480可用任何适合的方式形成，包含已知的沉积技术及选择性移除技术。柱状互连件480可根据传统器件制造及半导体封装技术制造，此处将不再详细说明这些传统技术。较佳地，柱状互连件480与导电平台460耦接。另外，如图所示，柱状互连件480较宜叠置在弹性块440上，且未延伸成叠置在边缘部分462上。
如图15所示，在生成柱状互连件之后，焊珠490可形成在柱状互连件480上。焊珠490可使用任意所欲的技术形成，以将其定位在柱状互连件480的末端482上。焊珠490可以多种技术(包括回焊工艺)成形，以有助于其与外部组件及/或电路的连接性。
虽然前面已详细说明至少一个例示性实施例，但应了解存在大量的变形例。亦应了解此处所述的例示性实施例非意欲以任何方式限制所主张的发明主题的范围、应用或组构。相反，前述详细说明将为熟知本领域的技术人员提供方便的用在实施说明的实施例的路线图。应理解在不背离权利要求所定义的范围的条件下可进行组件的功能及设置的多种改变，这些改变包括在申请该专利时所习知的等同物及可预见的等同物。

Claims (9)

1.一种半导体器件(50)，其包括器件衬底(102)及互连结构(60)，该互连结构(60)包括：
形成为叠置在该器件衬底(102)上的导电垫(110)；
形成为叠置在该导电垫(110)上且密封一空腔的导电平台(160)，其中，该导电平台(160)具有从该导电垫(110)延伸离开的边缘部分(162)及在该边缘部分(162)的上面的顶盖部分(170)；
在该导电垫(110)上面且围绕该边缘部分(162)的钝化层(130)；
设置在该空腔中的缓冲材料(140)；以及
设置在该导电垫(110)与该边缘部分(162)之间、以及该缓冲材料(140)与该顶盖部分(170)之间的粘合层(150)。
2.如权利要求1所述的半导体器件(50)，其中，该粘合层(150)进一步设置在该缓冲材料(140)与该边缘部分(162)之间。
3.一种半导体器件(50)，其包括器件衬底(102)及互连结构(60)，该互连结构(60)包括：
形成为叠置在该器件衬底上的导电垫；
形成为叠置在该导电垫上且密封一空腔的导电平台，其中，该导电平台具有从该导电垫延伸离开的边缘部分及在该边缘部分的上面的顶盖部分；
在该导电垫上面且围绕该边缘部分的钝化层；
设置在该空腔中的缓冲材料；以及
形成为至少部分叠置在该导电平台(160)上且与该导电平台(160)电耦接的导电柱状互连件(180)。
4.如权利要求3所述的半导体器件(50)，其中，该导电柱状互连件(180)具有横截面边缘(184)，该横截面边缘(184)全部叠置在该缓冲材料(140)上。
5.一种形成用于器件衬底(102)的接触平台的方法，该方法包括：
提供具有导电接触组件(110)、在该导电接触组件(110)上面且围绕导电平台(160)的边缘部分(162)的钝化层(130)、以及延伸穿过该钝化层(130)且终止在该导电接触组件(110)的凹槽(432)的半导体器件结构(50)；
以弹性材料(500)至少部分地填充该凹槽(432)；
选择性地去除一部分的该弹性材料(500)以形成弹性垫(140)，该弹性垫(140)叠置在该导电接触组件(110)上且与该钝化层(130)分隔开；以及
其中，形成该导电平台(160)以使该导电平台(160)至少部分围绕该弹性垫(140)。
6.如权利要求5所述的方法，进一步包括从该半导体器件结构去除过量弹性材料(501)，该过量弹性材料(501)叠置在该钝化层上。
7.如权利要求6所述的方法，其中，该去除过量弹性材料(501)的步骤包括使用该钝化层(130)作为终止层而研磨该半导体器件结构(50)。
8.如权利要求5所述的方法，进一步包括形成叠置在该导电平台(160)上而与该导电平台(160)电耦接的导电柱状互连件(180)，该导电柱状互连件(180)具有外边缘(184)，该外边缘(184)全部叠置在该弹性垫(140)上。
9.如权利要求5所述的方法，其中，该至少部分地填充该凹槽(432)的步骤包括在该半导体器件结构(50)上沉积聚酰亚胺材料，该聚酰亚胺材料至少部分地叠置在该钝化层(130)上。
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