CN104465576A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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Publication number
CN104465576A
CN104465576A CN201410016957.5A CN201410016957A CN104465576A CN 104465576 A CN104465576 A CN 104465576A CN 201410016957 A CN201410016957 A CN 201410016957A CN 104465576 A CN104465576 A CN 104465576A
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weld pad
district
layer
dielectric layer
region
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CN104465576B (zh
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林忠信
吴秉桓
赖朝文
吴鸿谟
庄英政
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明提出一种半导体元件及其制造方法，包括衬底、介电层、虚拟焊垫、焊垫、重布线层以及金属内连线。衬底包括非元件区与元件区。介电层位于非元件区与元件区上。虚拟焊垫位于非元件区的介电层上。金属内连线位于非元件区的介电层中，与虚拟焊垫连接。焊垫位于元件区的介电层上。缓冲层位于焊垫与介电层之间。缓冲层包括金属、金属氮化物或其组合。重布线层位于介电层上，连接虚拟焊垫与焊垫。

Description

半导体元件及其制造方法
技术领域
本发明是有关于一种半导体元件及其制造方法。
背景技术
随着半导体处理的发展，集成电路（Integrated Circuit，IC）元件也走向高度集成化。在半导体元件的封装处理（packaging process）中，集成电路封装扮演着重要的角色。集成电路封装的型式可以包含打线接合封装（WireBonding Package，WB）、贴带自动接合封装（Tape Automatic Bonding，TAB）与覆晶接合（Flip Chip，FC）等型式。
在封装处理中需提供接合力（bonding force），接点（焊垫）下方的区域必须承受相当大的冲击能量，因而导致焊垫下方的介电层产生裂缝（crack）、剥落（peel）或是变形，而对芯片造成损害。
发明内容
本发明提供一种半导体元件及其制造方法，可以避免焊垫下方的介电层产生裂缝、剥落或是变形。
本发明提出一种半导体元件，包括衬底、介电层、虚拟焊垫、焊垫、重布线层以及金属内连线。衬底包括非元件区与元件区。介电层位于非元件区与元件区上。虚拟焊垫位于非元件区的介电层上。金属内连线位于非元件区的介电层中，与虚拟焊垫连接。焊垫位于元件区的介电层上。缓冲层位于焊垫与介电层之间。缓冲层包括金属、金属氮化物或其组合。重布线层位于介电层上，连接虚拟焊垫与焊垫。
依据本发明实施例所述，所述缓冲层的材料包括钨、钽、钽/氮化钽/钽或其组合。
依据本发明实施例所述，所述焊垫的材料包括铝、铜或其合金。
依据本发明实施例所述，所述元件区包括阵列区、核心电路区或外围电路区。
依据本发明实施例所述，所述阵列区包括开关阵列区、存储器阵列区、逻辑阵列区、电容阵列区、电阻阵列区或电感阵列区。
依据本发明实施例所述，所述半导体元件还包括第二金属内连线，位于所述元件区的所述焊垫下方的所述介电层中，且所述第二金属内连线未与所述焊垫连接。
依据本发明实施例所述，所述第一金属内连线包括多数个第一顶金属层，所述第二金属内连线包括多个第二顶金属层，所述第一顶金属层的线宽大于所述第二顶金属层的线宽。
依据本发明实施例所述，所述第一顶金属层的之间的多数个间隔之间具有多数个第一空隙，且所述第二顶层金属层之间的多数个间隔之间具有多数个第二空隙，其中在单位面积内所述第二空隙的数目大于所述第一空隙的数目。
依据本发明实施例所述，所述半导体元件还包括保护层，覆盖部分所述外围元件区的所述虚拟焊垫、所述重布线层以及部分所述焊垫，且所述保护层具有焊垫开口，裸露出所述焊垫的表面。
依据本发明实施例所述，所述虚拟焊垫、所述重布线层以及所述焊垫的高度相同。
依据本发明实施例所述，所述虚拟焊垫、所述重布线层以及所述焊垫的材料相同。
本发明提出一种半导体元件的制造方法，包括提供衬底，衬底包括非元件区与元件区。非元件区与元件区上形成介电层。在非元件区的介电层中形成金属内连线。在元件区的介电层上形成缓冲层。缓冲层包括金属、金属氮化物或其组合。在介电层上方形成导电层。图案化导电层，以形成虚拟焊垫、焊垫与重布线层。虚拟焊垫位于非元件区上，与金属内连线电性连接。焊垫位于元件区的缓冲层上。重布线层连接虚拟焊垫与焊垫。
依据本发明实施例所述，所述缓冲层的材料包括钨、钽、钽/氮化钽/钽或其组合。
依据本发明实施例所述，所述焊垫的材料包括铝、铜或其合金。
依据本发明实施例所述，所述元件区包括阵列区、核心电路区或外围电路区。
依据本发明实施例所述，所述阵列区包括开关阵列区、存储器阵列区、逻辑阵列区、电容阵列区、电阻阵列区或电感阵列区。
依据本发明实施例所述，所述半导体元件的制造方法还包括形成第二金属内连线，位于所述元件区的所述焊垫下方的所述介电层中，且所述第二金属内连线未与所述焊垫连接。
依据本发明实施例所述，形成所述第一金属内连线与所述第二金属内连线的方法包括：形成金属层；图案化所述金属层，以在所述非元件区形成多数个第一顶金属层，并在所述元件区形成多个第二顶金属层，其中所述第一顶金属层的线宽大于所述第二顶金属层的线宽；在所述非元件区与所述元件区上形成所述介电层；在所述元件区上的所述介电层上形成所述缓冲层；将所述非元件区的所述介电层图案化，以形成至少一介层窗开口，裸露出对应的所述第一顶金属层；以及在所述非元件区与所述元件区上的所述介电层上形成所述导电层。所述导电层还填入于所述至少一介层窗开口中，以形成至少一介层窗。
依据本发明实施例所述，所述半导体元件的制造方法还包括形成保护层，覆盖部分所述非元件区的所述虚拟焊垫、所述重布线层以及部分所述焊垫，且所述保护层具有焊垫开口，裸露出所述焊垫的表面。
本发明实施例的半导体元件及其制造方法，可以避免焊垫下方的介电层产生裂缝、剥落或是变形。
本发明实施例的半导体元件及其制造方法，可以在形成焊垫的同时形成重布线层，因此，可以不需要增加额外的步骤。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至1I是依照本发明实施例示出的一种半导体元件的制造方法的流程剖面图；
图2是依照本发明实施例示出的一种半导体元件的上视图。
附图标记说明：
10：衬底；
12、14：介电层；
16、18：间隔；
19、20：空隙；
22：缓冲材料层；
22a、22b：缓冲层；
24、28、38：掩膜层；
26、30：开口；
32：介层窗开口；
34：导电层；
36：介层窗；
40：虚拟焊垫；
42：焊垫；
44：重布线层；
48、49：焊垫开口；
50：保护层；
52：氧化硅层；
54：氮化硅层；
56：聚酰亚胺层；
58：焊线；
60：第一金属内连线；
66：第一顶金属层；
80：第二金属内连线；
86：第二顶金属层；
100：非元件区；
200：元件区；
W1、W2：线宽；
I-I：切线。
具体实施方式
图2是依照本发明实施例示出的一种半导体元件的上视图。图1G是图2的切线I-I的剖面图。
请参照图1I与图2，本发明的半导体元件是将焊垫42设置在元件区200上，而在非元件区100上设置虚拟焊垫40。焊垫42通过同层的重布线层（RDL）44直接电性连接虚拟焊垫40，以与虚拟焊垫40下方的第一金属内连线60电性连接。由于焊线是形成在元件区200的焊垫42上，而非元件区100的虚拟焊垫40被保护层50覆盖，而不会有焊线形成，因此，非元件区100的介电层14上不会面临接合处理所产生的问题。再者，在元件区200上的焊垫42下方设置缓冲层22b，可以改善元件区200上的介电层14因为接合处理而造成的剥落、裂缝或变形等问题。
请参照图1I与图2，更详细地说，本发明的半导体元件包括衬底10、介电层12、14、虚拟焊垫40、第一金属内连线60、焊垫42、缓冲层22b、第二金属内连线80、重布线层44以及保护层50。
衬底10包括非元件区100与元件区200。本实施例所述的非元件区100内不会形成半导体元件（例如是位于第一金属内连线60下方的晶体管）。在一实施例中，非元件区100内不会形成阵列、核心电路或外围电路。元件区200表示不是非元件区100的区域。元件区200可以是核心电路区、外围电路区或是阵列区。阵列区例如是开关阵列区、存储器阵列区、逻辑阵列区、电容阵列区、电阻阵列区或电感阵列区，但不以此为限。在一实施例中，请参照图2，非元件区100可位于元件区200的探针接垫区（probe pad region）、边缘接垫区（edge pad region）或中心接垫区（central pad region）之中，但本发明并不以此为限。在另一实施例中，非元件区100可与元件区200相隔一距离。
介电层14位于衬底10的非元件区100与元件区200上方。虚拟焊垫40位于非元件区100的介电层14上。焊垫42位于元件区200的介电层14上。缓冲层22b位于焊垫42与介电层14之间。缓冲层22b还可以位于虚拟焊垫40与介电层14之间。缓冲层22b包括金属、金属氮化物或其组合。缓冲层22b的材料例如是包括钨、钽、钽/氮化钽/钽或其组合。缓冲层22b的厚度例如是300埃至5000埃。
重布线层44位于介电层14上，连接位于非元件区100的虚拟焊垫40与位于元件区200的焊垫42。重布线层44与焊垫42以及虚拟焊垫40都是位于介电层14上，且是经由同一层金属层图案化而形成，因此，重布线层44与焊垫42以及虚拟焊垫40的高度大致相同。
第一金属内连线60位于非元件区100的介电层12、14中，与上方的虚拟焊垫40连接。第二金属内连线80位于元件区200的焊垫42下方的介电层12、14中，且第二金属内连线80未与焊垫42连接。第一金属内连线60包括多个第一顶金属层66，且第二金属内连线80包括多个第二顶金属层86，其中第一顶金属层66中至少有一个的线宽W1大于第二顶金属层86其中之一的线宽W2。介电层14难以完全填满第一顶金属层66之间的间隔16以及第二顶层金属层86之间的间隔18，而在间隔16、18中形成空隙19、20。由于非元件区100上的第一顶金属层66的线宽W1大于元件区200上的第二顶金属层86的线宽W2，因此，在单位面积的非元件区100内的空隙20的数目小于在单位面积的元件区200内的空隙19的数目。
此外，第一金属内连线60还包括多个介层窗（或单一个介层窗）36，位于介电层14中，连接第一顶金属层66与虚拟焊垫40，而第二金属内连线80的第二顶金属层86上则无介层窗与焊垫42连接。
保护层50覆盖部分虚拟焊垫40、重布线层44以及部分焊垫42，且保护层50具有裸露出焊垫42表面的焊垫开口48以及裸露出虚拟焊垫40表面的焊垫开口49。焊线58形成在焊垫42上。
图1A至1I是依照本发明实施例示出的一种半导体元件的制造方法的流程剖面图。图2是图1G的上视图。
请参照图1A，提供衬底10。衬底10包括非元件区100与元件区200。衬底10可包括半导体材料、绝缘体材料、导体材料或上述材料的任意组合，且衬底10包括单层结构或多层结构。举例来说，衬底10可由选自于Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs与InP所组成的族群中的至少一种半导体材料形成。此外，也可使用绝缘体上硅（silicon on insulator，SOI）衬底。衬底10可由多层材料组成，例如Si/SiGe、Si/SiC。衬底10的材料并不以此为限。
接着，请继续参照图1A，在非元件区100与元件区200上形成介电层12。介电层12的材料可以是氧化硅、硼磷硅玻璃（BPSG）、磷硅玻璃（PSG）、无掺杂硅玻璃（USG）、氟掺杂硅玻璃（FSG）、旋涂式玻璃（SOG）或是介电常数低于4的低介电常数材料。衬底10与介电层12之间可包括其他的元件，例如是金氧半导体元件，诸如N型信道场效晶体管（NMOS）、P型信道场效晶体管（PMOS）或是互补式场效晶体管（CMOS），为简略起见，这些元件未示出，而被介电层12覆盖。
之后，请参照图1A，在非元件区100的介电层12中形成第一金属内连线60的一部分，并且在元件区200的介电层12中形成第二金属内连线80。更具体地说，第一金属内连线60的一部分包括第一顶金属层66及其下方的多层的下层金属层以及介层窗。同样地，第二金属内连线80包括第二顶金属层86及其下方的多层的下层金属层以及介层窗。第一金属内连线60与第二金属内连线80可以利用各种已知的处理方法同时形成。第一顶金属层66、第二顶金属层86以及下层金属层的材料例如是铝、铜或其合金。介层窗的材料例如是铝、铜或是钨。非元件区100上的第一顶金属层66中至少有一个的线宽W1大于元件区200上的第二顶金属层86其中之一的线宽W2。
接着，在非元件区100与元件区200上形成介电层14。介电层14的材料可以是氧化硅、硼磷硅玻璃、磷硅玻璃、无掺杂硅玻璃、氟掺杂硅玻璃、旋涂式玻璃或是介电常数低于4的低介电常数材料。
其后，请参照图1B，在非元件区100与元件区200的介电层14上形成缓冲材料层22。缓冲材料层22的材料包括金属、金属氮化物或其组合。缓冲材料层22例如是钨、钽、钽/氮化钽/钽或其组合。缓冲材料层22的形成方法可以是物理气相沉积法或是化学气相沉积法。化学气相沉积例如是等離子辅助化学气相沉积、低压力化学气相沉积等；物理气相沉积例如是蒸镀或溅镀等。缓冲材料层22的厚度可以是3000埃至5000埃。
之后，请参照图1B，在缓冲材料层22上形成图案化的掩膜层24。图案化的掩膜层24至少覆盖住元件区200上的缓冲材料层22。图案化的掩膜层24具有开口26裸露出非元件区100上的缓冲材料层22。图案化的掩膜层24例如是光刻胶层。图案化的掩膜层24的形成方法例如先形成光刻胶层，然后利用光刻处理图案化。开口26的大小可以依照实际的需要调整。在本实施例中，仅暴露出非元件区100上一部分的缓冲材料层22，但本发明并不以此为限。
接着，请参照图1C，以图案化的掩膜层24为蚀刻掩膜，进行蚀刻处理，以移除开口26所裸露的缓冲材料层22。蚀刻处理可以是干式蚀刻处理，例如是等離子蚀刻处理。等離子蚀刻处理所使用的气体例如是CF4与NF3，但不以此为限。在本实施例中，留下来的缓冲材料层22称为缓冲层22a。缓冲层22a覆盖在元件区200的介电层14以及非元件区100上部分的介电层14。
其后，请参照图1D，移除图案化的掩膜层24。之后，形成图案化的掩膜层28。图案化的掩膜层28具有多个开口30，裸露出非元件区100的介电层14。图案化的掩膜层28例如是光刻胶层。图案化的掩膜层28的形成方法例如先形成光刻胶层，然后利用光刻处理图案化。
继之，请参照图1E，以图案化的掩膜层28为蚀刻掩膜，进行蚀刻处理，以图案化非元件区100的介电层14，形成多个介层窗开口32。介层窗开口32裸露出第一顶金属层66。蚀刻处理可以是干式蚀刻处理，例如是等離子蚀刻处理。在一实例中，介层窗开口32的深度可以是6000埃至20000埃，例如是63埃，但不以此为限。
其后，请参照图1F，将图案化的掩膜层28移除。其后，在非元件区100与元件区200上形成导电层34。导电层34覆盖于非元件区100与元件区200的介电层14上，并且还填入在非元件区100的介层窗开口32中以形成介层窗36。介层窗36可构成第一金属内连线60的另一部分。导电层34的材料可以是金属或是金属合金，例如是铝、铜或其合金。导电层34的形成方法可以是物理气相沉积法，例如是溅镀法。导电层34的厚度可以是8000埃至20000埃，例如是74埃，但不以此为限。之后，在导电层34上形成图案化的掩膜层38。图案化的掩膜层38覆盖非元件区100与元件区200上部分的导电层34，裸露出部分的导电层34。
之后，请参照图1F、1G与图2，以图案化的掩膜层38为蚀刻掩膜，将导电层34以及缓冲材料层22图案化，以形成虚拟焊垫40、焊垫42、重布线层44以及缓冲层22b。虚拟焊垫40位于非元件区100上，与第一金属内连线60电性连接。焊垫42位于元件区200上。重布线层44连接位于非元件区100的虚拟焊垫40以及位于元件区200上的焊垫42。缓冲层22b则位于虚拟焊垫40、焊垫42、重布线层44与介电层14之间。之后将图案化的掩膜层38移除。
其后，请参照图1H，在衬底10上形成保护层50，覆盖虚拟焊垫40、焊垫42与重布线层44。保护层50可以是单层、双层或是多层结构。保护层50的材料可以包括氧化硅、氮氧化硅、氮化硅、有机材料、聚合物或其组合。有机材料例如是苯并环丁烯（BCB）。聚合物例如是聚酰亚胺（PI）。保护层50可以以化学气相沉积法或是涂布法来形成。在本实施例中，保护层50包括氧化硅层52、氮化硅层54以及聚酰亚胺层56，其厚度分别为63埃、83埃与83埃，但本发明不以此为限。
其后，将保护层50图案化，以在保护层50中形成焊垫开口48、49。焊垫开口48裸露出元件区200上的焊垫42的表面。焊垫开口49裸露出元件区100上的虚拟焊垫40的表面。留下来的保护层50覆盖部分虚拟焊垫40、重布线层44以及部分的焊垫42。将保护层50图案化的方法可以是光刻与蚀刻法。
之后，请参照图1I，进行打线处理以在焊垫42上成焊线（bonding wire）58。打线处理可以采用各种已知的方法来形成，并无特别的限制，在此不再赘述。
本发明实施例的半导体元件是将焊垫设置在元件区上，而在非元件区设置虚拟焊垫，焊垫通过重布线层电性连接虚拟焊垫，以与虚拟焊垫下方的金属内连线电性连接。由于焊垫设置在元件区上，焊线不会形成在非元件区上方，因此，可以避免非元件区的介电层因为进行接合处理（bonding process）而剥落、裂缝或变形。再者，在本发明实施例中，将焊垫设置在元件区上且在焊垫下方设置缓冲层，可以在封装程中承受由接合力产生之冲击能量，维持其原有结构之健全性，避免产生裂缝、剥落或是材料变形，进而排除使用厚的封装材料，降低处理成本。再者，重布线层的材料可与虚拟焊垫以及焊垫的材料相同，且可同时形成，因此，无需再增加额外的步骤，且无需使用其他的材料来形成。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (19)

1.一种半导体元件，其特征在于，包括：
衬底，包括非元件区与元件区；
介电层，位于所述非元件区与所述元件区上；
虚拟焊垫，位于所述非元件区的所述介电层上；
第一金属内连线，位于所述非元件区的所述介电层中，与所述虚拟焊垫连接；
焊垫，位于所述元件区的所述介电层上；
缓冲层，位于所述焊垫与所述介电层之间，其中所述缓冲层包括金属、金属氮化物或其组合；以及
重布线层，位于所述介电层上，连接所述虚拟焊垫与所述焊垫。
2.根据权利要求1所述的半导体元件，其特征在于，所述缓冲层的材料包括钨、钽、钽/氮化钽/钽或其组合。
3.根据权利要求1所述的半导体元件，其特征在于，所述焊垫的材料包括铝、铜或其合金。
4.根据权利要求1所述的半导体元件，其特征在于，所述元件区包括阵列区、核心电路区或外围电路区。
5.根据权利要求4所述的半导体元件，其特征在于，所述阵列区包括开关阵列区、存储器阵列区、逻辑阵列区、电容阵列区、电阻阵列区或电感阵列区。
6.根据权利要求1所述的半导体元件，其特征在于，还包括第二金属内连线，位于所述元件区的所述焊垫下方的所述介电层中，且所述第二金属内连线未与所述焊垫连接。
7.根据权利要求1所述的半导体元件，其特征在于，所述第一金属内连线包括多数个第一顶金属层，所述第二金属内连线包括多个第二顶金属层，所述第一顶金属层的线宽大于所述第二顶金属层的线宽。
8.根据权利要求7所述的半导体元件，其特征在于，所述第一顶金属层的之间的多数个间隔之间具有多数个第一空隙，且所述第二顶层金属层之间的多数个间隔之间具有多数个第二空隙，其中在单位面积内所述第二空隙的数目大于所述第一空隙的数目。
9.根据权利要求1所述的半导体元件，其特征在于，还包括保护层，覆盖部分所述外围元件区的所述虚拟焊垫、所述重布线层以及部分所述焊垫，且所述保护层具有焊垫开口，裸露出所述焊垫的表面。
10.根据权利要求1所述的半导体元件，其特征在于，所述虚拟焊垫、所述重布线层以及所述焊垫的高度相同。
11.根据权利要求1所述的半导体元件，其特征在于，所述虚拟焊垫、所述重布线层以及所述焊垫的材料相同。
12.一种半导体元件的制造方法，其特征在于，包括：
提供衬底，所述衬底包括非元件区与元件区；
在所述非元件区与所述元件区上形成介电层；
在所述非元件区的所述介电层中形成第一金属内连线；
在所述元件区的所述介电层上形成缓冲层，其中所述缓冲层包括金属、金属氮化物或其组合；
在所述介电层上方形成导电层；以及
图案化所述导电层，以形成虚拟焊垫、焊垫与重布线层，其中虚拟焊垫位于所述非元件区上，与所述第一金属内连线电性连接，所述焊垫位于所述元件区的所述缓冲层上，且所述重布线层连接所述虚拟焊垫与所述焊垫。
13.根据权利要求12所述的半导体元件的制造方法，其特征在于，所述缓冲层的材料包括钨、钽、钽/氮化钽/钽或其组合。
14.根据权利要求12所述的半导体元件的制造方法，其特征在于，所述焊垫的材料包括铝、铜或其合金。
15.根据权利要求12所述的半导体元件的制造方法，其特征在于，所述元件区包括阵列区、核心电路区或外围电路区。
16.根据权利要求15所述的半导体元件的制造方法，其特征在于，所述阵列区包括开关阵列区、存储器阵列区、逻辑阵列区、电容阵列区、电阻阵列区或电感阵列区。
17.根据权利要求12所述的半导体元件的制造方法，其特征在于，还包括形成第二金属内连线，位于所述元件区的所述焊垫下方的所述介电层中，且所述第二金属内连线未与所述焊垫连接。
18.根据权利要求17所述的半导体元件的制造方法，其特征在于，形成所述第一金属内连线与所述第二金属内连线的方法包括：
形成金属层；
图案化所述金属层，以在所述非元件区形成多数个第一顶金属层，并在所述元件区形成多个第二顶金属层，其中所述第一顶金属层的线宽大于所述第二顶金属层的线宽；
在所述非元件区与所述元件区上形成所述介电层；
在所述元件区上的所述介电层上形成所述缓冲层；
将所述非元件区的所述介电层图案化，以形成至少一介层窗开口，裸露出对应的所述第一顶金属层；以及
在所述非元件区与所述元件区上的所述介电层上形成所述导电层，其中所述导电层还填入于所述至少一介层窗开口中，以形成至少一介层窗。
19.根据权利要求12所述的半导体元件的制造方法，其特征在于，还包括形成保护层，覆盖部分所述非元件区的所述虚拟焊垫、所述重布线层以及部分所述焊垫，且所述保护层具有焊垫开口，裸露出所述焊垫的表面。
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