CN102364345B - 具有所装配的电路载体的电路装置及相应功率半导体模块 - Google Patents

具有所装配的电路载体的电路装置及相应功率半导体模块 Download PDF

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CN102364345B
CN102364345B CN201110167479.4A CN201110167479A CN102364345B CN 102364345 B CN102364345 B CN 102364345B CN 201110167479 A CN201110167479 A CN 201110167479A CN 102364345 B CN102364345 B CN 102364345B
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fragment
narrow
circuit arrangement
metal layer
power semiconductor
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CN102364345A (zh
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T.洪
M.托本
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/20—Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
    • G01R1/203—Resistors used for electric measuring, e.g. decade resistors standards, resistors for comparators, series resistors, shunts
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Abstract

本发明涉及具有并联电阻的电路装置。本发明涉及一种具有装配有并联电阻（3）的电路载体（2）的电路装置。该装置包括：具有上侧（5a）的扁平绝缘载体（5）以及施加到该上侧（5a）上的结构化的金属化层（6）；第一功率半导体芯片（1），其布置在金属化层（6）的第一片段（61）上并且具有与第一片段（61）导电地连接的第一下芯片负载接线端子（11）。并联电阻（3）布置在金属化层（6）的第二片段（62）上并且具有与第二片段（62）导电连接的下主接线端子（31）。在第一片段（61）与第二片段（62）之间构造有导电连接（4），其包括构造在第一片段与第二片段之间的狭窄部（40），在电路装置运行时在第一下芯片负载接线端子（11）与下主接线端子（31）之间流动的电流必然经过狭窄部（40）。

Description

具有所装配的电路载体的电路装置及相应功率半导体模块
技术领域
本发明涉及借助于并联电阻的电阻测量。并联电阻具有两个在下面被称为主接线端子的接线端子，借助于这些接线端子，电阻元件与要测量的电流串联。通过确定在电阻元件上下降的电压，可以结合电子元件的已知电阻值来确定在主接线端子之间流动的负载电流。为了在此获得尽可能高的测量精度，原则上所期望的是尽可能高的测量电压，这要求高的电阻值。但是，另一方面，应当将电阻值保持得尽可能小，因为损耗功率与电阻元件的电阻成比例地升高。除了高的损耗功率本身由于与此联系的发热而已经是不期望的以外，这样的发热还改变电阻元件的电流电压特征曲线。因此，在实际中，必须始终找出恰好仍允许的损耗功率与所要求的测量精度之间的折衷。但是不是总能找出满足全部竞争性边界条件的折衷。
背景技术
造成困难的还有，在电路装置中要利用并联电阻来测量的电流例如在该电流在电路板的导体平面中流动时可能在其在导体平面上的电流分布方面根据相应的电路状态而变化，使得电流测量的结果高度地取决于电路装置的相应电路状态下的电流分布。因此，在具有桥电路的功率半导体模块中的电路装置的情况下，确定总电流值与实际电流值之间的取决于电流方向的偏差为高达2％。但是所期望的是实现1％或更低的偏差。
在制造多个尤其是具有用于利用并联电阻进行电流测量的组件的相同电路装置时，同样可能出现测量不精确性。在理想情况下，用来分接出在并联电阻上下降的电压的分接头在不同的电路装置中恰好安装在对应的相同位置处。但是在实际中，由于不可避免的制造公差而得出与理想情况的偏差，使得在不同电路装置中，在意义上分别相同的电势分接头在不同电路装置的一般相同的构造和相同的通电关系的情况下分接出不同的电势。
此外，常规的并联电阻通常具有两个主接线端子，这两个主接线端子都被焊接到电路载体的金属化部上。这样的构造要求电路载体上的许多空间，这转化为费用。这尤其是在将昂贵的陶瓷衬底用作电路载体时是重要的。此外，这样的并联电阻在电路载体上的安装要求特有的工艺技术，这同样提高了制造成本和制造费用。此外，这些并联电阻由于其构造方式而要求较长的通电线路，由此显著提高了电感。但是由此尤其是可能在快速开关过程中导致高的感应电压，由于该感应电压，在并联电阻处分接的测量信号可能失真。
发明内容
本发明的任务在于，提供一种具有并联电阻的电路装置，该电路装置实现利用并联电阻的精确测量，其中并联电阻要求尽可能小的空间，并且该电路装置可以以小的成本来制造。本发明的另一任务在于，提供一种具有这样的电路装置的功率半导体模块。这些任务通过根据权利要求1所述的电路装置以及通过根据权利要求17所述的功率半导体模块来解决。本发明的配置和改进是从属权利要求的主题。
本发明设置了具有所装配的电路载体的电路装置，该电路载体具有带有上侧的扁平绝缘载体以及在该上侧施加的结构化的金属化层。此外，该电路装置包括第一功率半导体芯片，该第一功率半导体芯片布置在金属化层的第一片段上并且具有第一下芯片负载接线端子，该第一下芯片负载接线端子与第一片段导电地连接。此外，设置有并联电阻，该并联电阻布置在金属化层的第二片段上并且具有下主接线端子，该下主接线端子与第二片段导电地连接。在第一片段与第二片段之间构造有导电连接，该导电连接包括在第一片段与第二片段之间构造的狭窄部，在电路装置运行时，在第一下芯片负载接线端子与并联电阻的第一主接线端子之间流动的电流必然经过该狭窄部。利用一个或多个这样的电路载体，可以实现功率半导体模块。
附图说明
下面参考附图根据多个实施例来阐述本发明。
图1示出具有并联电阻的电路装置的原理图，该电路装置可以采取不同的开关状态，在这些开关状态中电流以不同的方向流经该并联电阻；
图2A示出具有结构化的金属化层的电路载体，该金属化层具有两个通过该金属化层的狭窄部导电地彼此连接的片段，其中一个片段装配有功率半导体芯片，并且另一片段装配有并联电阻；
图2B示出具有在图2A中所示的在其被装配有两个功率半导体芯片和一个并联电阻以后的电路载体的电路装置；
图2C以截平面E1示出通过图2B中所示的所装配的电路载体的纵截面；
图2D在一个图示中示出根据图2A的未装配的电路载体，从该图示中可以看出，狭窄部对在金属化层中在其通过狭窄部彼此连接的片段之间流动的电流进行引流并且由此基本上与电路状态无关地负责并联电阻区域中的电流分布；
图3示出根据图2A和2D的未装配的电路载体，其中被设置用于安装并联电阻的安装面位于与根据图2A和2D的电路载体不同的位置；
图4示出另一电路载体，该电路载体与根据图2A、2D和3的电路载体的不同在于狭窄部的另一位置；
图5示出未装配的电路载体，该电路载体与根据图4的电路载体相同，但是其中设置有另一位置以用于安装并联电阻；
图6示出未装配的电路载体，其中用于并联电阻的安装面被槽包围，该槽在去除狭窄部的情况下完全包围该安装面；
图7示出未装配的电路载体，该电路载体与根据图6的未装配的电路载体的不同在于，在金属化层的连续片段上设置有安装面以用于安装两个功率半导体芯片；
图8示出未装配的电路载体，其中金属化部的上面应布置并联电阻的片段与金属化层的上面设置有用于两个功率半导体芯片的安装面的另一片段被两个朝向彼此的狭长槽分开，在所述槽的末端之间构造有狭窄部；
图9示出未装配的电路载体，其中狭窄部位于上金属化部中的狭长槽的一端与连续片段的侧面边缘之间；
图10示出未装配的电路载体，其中并联电阻布置在两个功率半导体芯片之间，其中每个功率半导体芯片都通过金属化层的狭窄部与并联电阻连接；
图11A示出根据图2A和2D的在其被装配以一个并联电阻和两个功率半导体芯片以后的所装配的电路载体，其中狭窄部为了减小电阻而借助于接合线进行桥接；
图11B示出狭窄部的放大图示，该狭窄部具有对其进行桥接的接合线；
图11C以图11A和11B所示的截平面示出通过所装配的电路载体在狭窄部区域中的纵截面；
图12A示出根据图11A至11C的装置的可替代的配置，其中狭窄部的桥接借助于焊剂进行；
图12B以截平面E3示出通过根据图12A的电路装置的纵截面；
图13A示出根据图11A至11C的装置的可替代的配置，其中桥接通过超出狭窄部所焊接的金属片进行桥接；
图13B以截平面E4示出通过根据图13A的电路装置的纵截面；
图14示出功率半导体模块的俯视图，该功率半导体模块具有三个电路装置，其中每个电路装置都被装配以半桥，其中金属化部的布局在三个电路载体中都是相同的，但是其中分别有一个并联电路位于对应布局上的不同位置；以及
图15示出另一功率半导体模块的俯视图，该功率半导体模块被构造成变频器模块并且具有三个电路装置，其中上金属化部的第一、第二和第三片段分别被相同地构造，并且其中第二片段分别与并联电阻连接，该并联电阻在三个电路装置中位于第二片段上的不同位置。
如果未另行说明，则相同的附图标记表示具有相同功能的相同的元件。
具体实施方式
图1示出具有并联电阻的电路装置的原理图，该电路装置可以采取不同的开关状态，例如诸如在变频器中使用的半桥。该半桥包括两个电串联的开关元件1和2，这些开关元件例如可以是可控功率半导体开关，如MOSFET、IGBT、J-FET、晶闸管、二极管或任意其他的开关元件。半桥在串联的开关元件1和2之间的电路节点K处提供用于运行要连接到相位输出端P上的负载的电势。该电势尤其是取决于开关元件1和2的开关状态。给具有开关元件1和2的半桥供应正供电电势V+和负电势V-。在这样的半桥正常运行时，总是最多连接开关元件1和2之一，以便避免短路，也就是说，如果连接开关元件1、2之一，则另一开关元件2、1被打开。
为了测量负载电流设置并联电阻3，该并联电阻3一方面连接到电路节点K并且另一方面连接到相位接线端子P。此外，为了确定在并联电阻3上下降的电压，设置第一电势接线端子V31和第二电势接线端子V32。
在第一开关元件1闭合并且第二开关元件2打开的情况下，在电路节点K处存在电势V+，这在电路节点K与相位接线端子P之间导致电流I1，该电流I1取向为从电路节点K到相位接线端子P的方向。而在开关元件1打开并且开关元件2闭合的情况下，在电路节点K处存在电势V-，这导致电流I2，该电流I2取向为从相位接线端子P到电路节点K。因此，电流I2与电流I1相反。
根据电路布局的几何结构，电流分布取决于相应电流I1或I2的方向，使得并联电阻3上的电压降的绝对值、即第一电势接线端子V31与第二电势接线端子V32之间的电势差的绝对值对于电流I1和I2而言即使在电流I1和I2的绝对值相等的情况下仍然可能是不同的。
并联电阻上的电压降的取决于电流方向的偏差尤其是在电路被构造在具有大面积印制导线的电路板上时是显著的，这些大面积印制导线允许电流绝对值的取决于电流方向的不同分布。为了在利用并联电阻3测量电流时提高测量精度，针对例如在图2A至2D中示出的电路示出一种电路装置，利用该电路装置可以在通过并联电阻检测电流时减小取决于电流方向的测量不精确性。
图2以俯视图示出未装配的电路载体8，该电路载体具有带有上侧的介电绝缘载体5，在该上侧上施加有结构化的上金属化层6。因此，电路载体8形成电路板。上金属化层6具有第一片段61、第二片段62和第三片段63。片段61和62借助于导电连接4彼此连接。在所示的示例中，电连接4被实现在上金属化层6内，使得片段61和62构成上金属化层6的连续片段65的构件。
在该示例中，导电连接4完全以并联电阻3的朝向导电连接4一侧的高度延伸。换言之，并联电阻3位于并联电阻3的横向侧面的两个延长部之间，所述延长部连接到并联电阻3的朝向狭窄部40的（同样为横向的）侧面。
在片段61、62、63上以虚线示出的方式标出了安装面11’、13’以及12’。如结合图2B可以看出的那样，安装面11’和12’被设置为在其上安装第一功率半导体芯片1或第二功率半导体芯片2。对应地，第三安装面13’被设置为安装并联电阻3。现在，导电连接4被构造为使得其形成连续片段65的片段61和62之间的狭窄部40。由于狭窄部40，安装在安装面11’上的第一功率半导体芯片1与安装在第三安装面13’上的并联电阻3之间的电流必然、更具体而言与电流方向无关地经过狭窄部40处的导电连接4。因此，与常规电流装置相比，并联电阻3的电势连接、以及伴随于此第二片段62内的电流分布比在没有这样的狭窄部的对应常规装置中以显著更小的程度取决于电流方向。狭窄部40可以具有最小的宽度b40，该宽度b40例如可以处于比并联电阻3的长度13小90％的范围中。并联电阻3的长度13及其宽度b3分别与绝缘载体5的上侧5a平行地和以彼此垂直的方向被测得，其中长度13大于宽度b3。可选地，宽度b40可以被选择为大于650μm，以便实现一定的最小电流承载能力。
可替代地或附加地，狭窄部40的宽度b40既可以被选择为小于第一下芯片负载接线端子11的最小宽度b11，又可以被选择为小于下主接线端子31的最小宽度b31，其中宽度b40、b11和b31分别与绝缘载体5的上侧5a平行地被确定。
图2B示出在图2A中所示的在其在第一安装面11’上装配以第一功率半导体芯片1、可选地在第二安装面12’上装配以第二功率半导体芯片2、以及在第三安装面13’上装配以并联电阻3以后的电路载体8。
此外，该电路与接合线81、82、83、85、86以符合电路的方式接线。接合线81被电并联，并且连接在相位接线端子P上，这如图1所示。接合线82用于将功率半导体芯片1和2的负载线路与半桥串联以及按照根据图1的电路图将该半桥连接到正供电电势V+以及负供电电势V-上。接合线83分别与第一以及第二功率半导体芯片1及2的未详细示出的控制接线端子相连接。
此外还设置有接合线85、86，这些接合线用于确定在并联电阻3上下降的电势差以及如图1所示的那样分接出电势V31以及V32。从该电势差中可以确定流经并联电阻3的电流I1、I2的强度和方向。为此，接合线85在并联电阻3附近靠近安装面13’地与第二片段62接合。而另一接合线86与并联电阻3的金属化部32接合。
如从图2A和2B中可以明显地认识到的那样，可以生成两个朝向彼此的槽51以及52的末端之间的狭窄部40，这两个槽被引入到上金属化层6中，并且以垂直方向、即与绝缘载体5的上侧5a垂直地完全穿透该金属化层6。
图2C以截平面E1示出通过根据图2B的装置的纵截面。在该截面图中能够认识到，电路载体8除了金属化层6以外还可以具有可选的、施加到绝缘载体5的下侧5b上的下金属化层7。该下金属化层7可以任选地被结构化或者未结构化。
上金属化层6和可选的下金属化层6固定地与绝缘载体5的上侧5a以及下侧5b连接。绝缘载体5例如可以是陶瓷。适于作为用于此的陶瓷材料例如有氮化铝（AlN）、氧化铝（Al2O3）、氮化硅（Si3N4）、碳化硅（SiC）、或者氧化铍（BeO）。
上金属化层6和可选的下金属化层7可以完全或至少主要由铜或铝制成。电路载体8例如可以是DCB衬底（DCB＝Direct Copper Bonding，直接铜接合）、AMB衬底（AMB＝Active Metal Brazing，活性金属钎焊）、或者DAB衬底（DAB＝Direct Aluminum Bonding，直接铝接合）。可选地，金属化层6和/或7还可以薄薄地用材料银、NiAu、NiPd、NiPdAu中的一种或多种来镀层，以便产生可焊接的表面或借助于低温压力烧结连接技术来使芯片连接变得容易。
第一功率半导体芯片1是具有半导体本体10的垂直功率半导体器件，其配备有下负载接线端子11和上负载接线端子12。第一功率半导体芯片1的负载电流流经负载接线端子11、12。负载接线端子11、12例如可以是漏极/源极、发射极/集电极或者阳极/阴极。
为了将下负载接线端子11与所属的安装面11’（参见图2A）导电地连接，设置有焊剂层15。对应地，在图2C中被遮盖的第二功率半导体芯片2具有半导体本体20，该半导体本体20配备有下负载接线端子21和上负载接线端子22。在此，下负载接线端子21也利用焊剂层25与所属的安装面12’连接。
并联电阻3同样被构造成垂直器件并且具有掺杂的半导体本体30，该半导体本体30是并联电阻3的电阻元件。半导体本体30例如可以由基体材料硅制成，但是也可以由每种任意的其他半导体材料——例如碳化硅、锗、砷化镓等制成。但是原则上也可以使用每种任意的其他材料来制造电阻元件30。
尽管半导体材料的电阻特征曲线取决于温度，但是例如功率半导体模块在许多情况下总归具有例如利用NTC电阻传感器、例如硅温度传感器的温度测量，使得在电阻测量时的温度漂移可以容易地被补偿。
此外，并联电阻3在电阻元件30的朝向电路载体8的下侧具有下主接线端子31、以及上主接线端子32，该上主接线端子32位于半导体本体30的背向电路载体8的上侧上。下主接线端子31借助于焊剂35与所属安装面13’导电地连接。
因此，这样的并联电阻3如功率半导体芯片1、2那样同样分别具有一个上接线端子和一个下接线端子以及半导体本体。这所具有的优点是，并联电阻3可以与功率半导体芯片1、2利用相同的工艺技术并且在相同的装配步骤中在电路载体8上被装配和布线。与利用常规技术、例如通过简单焊接与电路载体8连接的常规并联电阻不同，所阐述的并联电阻3可以与要求高温的现代工艺技术、例如扩散焊接或低温压力烧结（NTV，英语：LTJT）兼容。
功率半导体芯片1、2的负载接线端子11、12、21、22以及并联电阻3的主接线端子31、32可以是相应半导体本体10、20以及30的金属化部。替代于焊剂层15、25以及35，也可以使用任意其他的导电连接材料——例如导电粘胶剂——或者压力烧结层，该压力烧结层用银粉和含有熔剂的膏体制成。
图2D以俯视图再次示出来自图2A至2C的未装配的电路载体8。根据本发明的一个可能的配置，狭窄部40所具有的位置和宽度b40被选择为使得在其末端之间构造有狭窄部40的槽51、52中的每一个处都存在直线g1和g2，该直线g1和g2从安装面11’以及12’向安装面13’延伸并且与第一以及第二槽51以及52相交。
图3以俯视图示出另一电路载体8，该电路载体与根据图2A至2D的电路载体8的区别在于狭窄部40的位置并且因此片段61与62之间的导电连接4的位置、以及第二片段62上的安装面13’的位置。在该布局下，可以不确定从第一安装面11’向安装面13’延伸并且在此与狭窄部40相交的直线。因此，安装面13’位于从安装面11’来看为准“死角”处。
图4和5中所示的电路载体8具有上金属化层6的相同结构化。它们的区别仅仅在于安装面13’在第二片段62上的位置。已经发现，由于如本发明中设置的狭窄部40，在确定并联电阻3的电阻值时取决于电流方向的测量误差基本上不取决于其安装面13’在上金属化层6的片段62上的位置。
在根据图5的装置中，槽51延伸到并联电阻3的朝向槽51的横向侧面的全部长度上。在根据图6的装置中，对应的情况适用于槽52。
在图6中所示的示例中，安装面13’在安装并联电阻3时在四个侧面被槽51环形地包围，该槽51在去除狭窄部40的情况下形成围绕安装面13’的闭合圆环。
在所有迄今为止所示的布局中，第三安装面63相对于连续片段65以及因此相对于其片段61和62间隔开，其中该第三安装面63被设置用于安装可选的第二功率半导体芯片2。但是如示例性地在图7中所示的那样，这不是一定必需的。在该示例中，用于第一以及第二功率半导体芯片1以及2的两个安装面11’和12’都被设置在金属化层6的第一片段61上。在该示例中，安装面13’也被槽51包围，该槽51在与绝缘载体5的上侧5a垂直的垂直方向上在其整个长度上完全穿透金属化层6，并且除了狭窄部40以外环形地包围安装面13’。
在图8和9中示出另外的配置，其中安装面11’和12’为了安装第一以及第二功率半导体芯片1以及2被布置在上金属化层6的相同片段61上，而被设置为安装并联电阻3的安装面13’位于上金属化层6的第二片段62上，该第二片段62仅仅通过狭窄部40处的导电连接4与第一片段61连接。在根据图8和9的布局下，安装面11’、12’、13’相对于彼此位于相同位置。两个装置的区别仅仅在于，狭窄部40位于不同位置，并且狭窄部40在根据图8的装置中位于上金属化层6中的两个朝向彼此的槽51和52的末端之间，而狭窄部40在根据图9的装置中位于上金属化层6中的槽51的末端与连续片段65的侧边之间。
图10中示出本发明的另一配置。在此，并联电阻3布置在上金属化层6的第二片段62的安装面13’上的两个功率半导体芯片1和2之间。该第二片段62仅仅借助于两个狭窄部40和40’与上金属化层6的第一片段61连接。用于第一以及第二功率半导体芯片1以及2的安装面11’和12’分别位于第一片段61上，使得第一狭窄部40位于安装面12’和13’之间，而第二狭窄部40’位于安装面11’和13’之间。
本申请的另一方面在于，通过将电流集中在特定的尽可能狭窄的区域中来精确地定义电流分布。为了同样好地在狭窄部的区域中实现足够小的功率电阻，可选地可以超出狭窄部40地通过施加一个或多个接合线88或扁平接合带（后者未示出）来设置功率电阻， 所述接合线88或扁平接合带延伸得超出狭窄部40并且分别在狭窄部4的两侧与连续片段65导电地连接。图11A示出对此的一个示例，其中示例性地有三个接合线88延伸得超出狭窄部40并且其中每个接合线都在狭窄部40的两侧与上金属化层6的连续片段65接合。换言之，接合线88中的每一个都与第一片段61以及第二片段62接合。
图11B示出来自狭窄部40的区域的放大片段。图11C是根据图11B的放大片段的以狭窄部40的区域中的截平面方式的截面图。仅仅在狭窄部40的区域中进行第一片段61与第二片段62之间的整个电连接4，由此可以实现将电流最大化地集中到狭窄部40的区域上。在该装置中，导电连接4包括上金属化层6中的被构造在第一片段61与第二片段62之间的连接路段、以及接合线88。
因此，针对第一片段61与第二片段62之间的整个导电连接存在至少一个截平面E2，在该截平面中，导电连接4的整个截面可以布置在具有预先给定的直径D40的圆内。直径D40例如可以处于650μm至并联电阻3的长度13的90％的范围中。
图12A示出对此的另一示例，该图再次示出电路装置的放大片段，该放大片段对应于根据图11B的片段。与该图不同，焊剂层89超出狭窄部地被施加到上金属化层6上，该 上金属化层6在狭窄部40的两侧接触连续片段65。图12B以截平面E3示出通过狭窄部的上面施加有焊剂89的纵截面。因此，焊剂层89在狭窄部40的每侧都与连续片段65导电地连接。换言之，焊剂层89接触第一片段61以及第二片段62。
图13A示出又一示例。在该图中，设置有导电金属片90，该金属片延伸得超出狭窄部40并且在狭窄部40的两侧与连续片段65导电地连接。该导电连接例如可以借助于焊剂89来进行。图13B以截平面E4示出根据图13A的装置的截面图。在该截面图中可以看出，焊剂89位于金属片90与上金属化层6之间。替代于焊剂89例如也可以使用压力烧结层或导电胶粘剂来产生金属片90与上金属化层6之间的导电连接。换言之，金属片90被焊接到第一片段61以及第二片段62上。
对应于根据图11C的装置，在根据图12和13B的装置中也分别示出圆，该圆具有直径D40并且在该圆中分别存在第一片段61与第二片段62之间的整个电连接4的整个截面。为根据图11C的装置所给定的直径D40的尺寸同样也适用于根据图12B和13B的装置。
图14示出具有壳体101的功率半导体模块，该壳体具有安装孔102，并且在该壳体的情况下盖板被移除。在该模块中相叠地存在三个电路装置，这些电路装置分别具有上金属化层6的相同结构化。对于这些电路装置中的上面一个而言，使用与迄今为止的图中相同的附图标记，但是其中在中间和下面的电路装置中，同样作为补充给其配备单上标或双上标，以用于区分。在所示的示例中，用于不同电路装置的上金属化层6、6’、6”布置在相同绝缘载体5上。但是可替代于此地，也可以为三个电路载体中的每一个设置单独的绝缘载体5、5’以及5”。
在该实施例中，附图标记1、1’以及1”分别表示布置在第一片段61、61’以及61”上的功率半导体芯片，而附图标记2、2’以及2”分别表示位于第三片段63、63’以及63”上的功率半导体芯片。对应地用附图标记3、3’以及3”来表示位于上金属化层6、6’以及6”的第二片段62、62’以及62”上的并联电阻。
用附图标记1、1’、1’’、2、2’、以及2’’表示的较大的功率半导体芯片分别是可控功率半导体芯片（例如MOSFET、IGBT、J－FET、SiC J－FET），这也可以通过从其上侧分别示出的控制接线端子来认识到，该控制接线端子在该示例中位于相应上负载接线端子内。而用附图标记1、1’、1’’、2、2’、以及2’’表示的较小的功率半导体芯片分别是续流二极管，这些续流二极管连接到有关的距其最近的较大的功率半导体芯片1、1’、1’’、2、2’、以及2’’。
可替代地，替代于分别与可控功率半导体芯片和续流二极管并联，也可以分别与SiC J－FET和MOSFET、尤其是SiC J－FET和Si－MOSFET并联。
如所提到的那样，上金属化部6、6’以及6’’可以被相同地结构化，并且可选地被装配以相同的功率半导体芯片1/2、1’/2’、1’’/2’’。在所示的示例中，三个电路装置在相应功率半导体芯片1/2、1’/2’、1’’/2’’的布置方面彼此无区别。但是区别在于有关并联电阻3、3’以及3’’在有关上金属化层6、6’以及6’’的相应第二片段62、62’以及62’’上的位置。
为了对功率半导体模块中的并联电阻3、3’以及3’’进行电布线，除了相应的上金属化层6、6’以及6’’以外还设置有接合线81、81’、81’’、85、85’、85’’、86、86’、86’’，所述接合线在电路载体侧与根据图2B的装置相对应地与相应并联电阻3、3’、3’’的上侧接合以及在有关并联电阻3、3’、3’’附近与所属上金属化部6、6’、6”的第二片段62、62’、62’’接合。接合线81、81’、81’’、85、85’、85’’、86、86’、86’’的另一侧为了模块外的接触能力而与置入到模块的壳体框中的连接片的脚区域接合。出于清楚的原因未示出模块中包含的另外的接合线。适于作为用于在本发明中所使用的接合线的材料的尤其是铝和/或铜。
替代于接合线，在根据图14的装置的情况下同样可以如在所有其他装置的情况下那样由其他电连接线来代替接合线。示例性地提出有扁平带或板材，这些扁平带或板材被焊接、扩散焊接、接合、超声焊接、或者借助于低温压力烧结连接被连接。
此外，在功率半导体模块的情况下可以设置接线端子、例如所提到的接线片，所述接线片用于外部接触模块。这些接线端子可以构造在被设置为在模块外部进行接触的那侧，被构造成焊接接线端子或旋拧接线端子或者被构造成压入接触部或弹簧接触部。
由于在根据本发明的电路装置的情况下设置的狭窄部40，在并联电阻3的区域中导致电势的非常平坦的梯度，使得在安装用于检测在并联电阻上下降的电压的分接头85/86、85’/86’、85’’/86’’时，由于制造技术造成的位置不精确性不至于导致电压测量的显著分散以及伴随于此的电流测量的显著分散。
最后应当指出，在所有前述电路装置的情况下，第一片段61与第二片段62之间的整个导电连接4持久地将这些片段61和62导电地彼此连接。
同样应当指出，导电连接4不必一定包括上金属化层6的片段。原则上，狭窄部40也可以借助于一个或多个根据图11A至13B所阐述的导电连接装置（接合线或接合带88、焊剂层、粘接层或烧结层89、金属片90）来实现。
图15示出另一功率半导体模块的俯视图。该功率半导体模块与根据图14的功率半导体模块的区别在于，设置有分别具有绝缘载体5、5’和5’’的三个单独的电路载体8、8’和8’’，以及在于功率半导体模块1、2、1’、2’、1’’、2’’的数目。布置在上金属化层6、6’、6’’的同一第一或第三片段61、61’、61’’或63、63’、63’’上并且与其负载线路电并联的所有功率半导体芯片分别通过虚线椭圆标出，该虚线椭圆针对有关功率半导体芯片用附图标记1、2、1’、2’、1’’以及2’’标出。
该模块总共具有三个半桥，其中每个半桥都具有相位输出端P、P’和P’’，其中每个相位输出端同时形成整个功率半导体模块的主接线端子。三个半桥的供电通过功率半导体模块的另外的主接线端子V+和V-来输送并且通过上金属化部6、6’和6’’的另外的片段连接到各个半桥上。
主接线端子V+、V-、P、P’被实施成旋拧接线端子，而该模块的所有其他电接线端子都借助于大量压入接触部104来实现，所述压入接触部104在其制造时被注入到壳体101中，并且根据壳体框101被布置为环形地围绕电路载体8、8’、8’’的整体分布。这些压入接触部例如可以气密地压入到例如包含用于模块的控制和/或调节和/或监视电子系统和/或保护电路的电路板的接触孔中。
此外，根据图15的功率半导体模块具有金属接合板103，该接合板103完全或至少基本上由铜制成并且通过该接合板103可以将模块中聚集的热排出到冷却体。为了将功率半导体模块与这样的冷却体旋拧在一起，设置有安装孔102。
同样如在根据图14的功率半导体模块中那样，在根据图15的功率半导体模块中，各个并联电阻3、3’、3’’布置在被相同地成形的第二片段62、62’、62’’上，以及布相对于这些片段布置在不同位置处。在其上侧，并联电阻3、3’、3’’分别利用多个电并联的接合线81、81’和81’’连接到形成相位输出端P、P’和P’’的主接线端子的脚区域。为此，从模块外侧可到达的主接线端子穿过壳体框101延伸到模块的内部空间，在那里，至少这些主接线端子的脚区域露出，并且因此对于接合线81、81’、81’’的联合（Anbondung）是可到达的。

Claims (16)

1.一种具有所装配的电路载体（2）的电路装置，包括：
具有上侧（5a）的扁平绝缘载体（5）以及施加到该上侧（5a）上的结构化的金属化层（6）；
第一功率半导体芯片（1），该第一功率半导体芯片（1）布置在金属化层（6）的第一片段（61）上并且具有第一下芯片负载接线端子（11），该第一下芯片负载接线端子（11）与第一片段（61）导电地连接；
并联电阻（3），该并联电阻（3）布置在金属化层（6）的第二片段（62）上并且具有下主接线端子（31），该下主接线端子（31）与第二片段（62）导电地连接；
其中在第一片段（61）与第二片段（62）之间构造有导电连接（4），该导电连接（4）包括构造在第一片段与第二片段之间的狭窄部（40），在电路装置运行时，在第一下芯片负载接线端子（11）与下主接线端子（31）之间流动的电流必然经过该狭窄部（40）；
其中第一片段（61）和第二片段（62）是结构化的金属化层（6）的连续片段（65）的构件；
其中狭窄部（40）处的连续片段（65）具有宽度，该宽度小于第一下芯片负载接线端子（11）的最小宽度并且小于下主负载接线端子（31）的最小宽度，其中连续片段（65）在狭窄部（40）处所具有的宽度、第一下芯片负载接线端子（11）的最小宽度以及下主负载接线端子（31）的最小宽度分别与绝缘载体（5）的上侧（5a）平行地被确定。
2.根据权利要求1所述的电路装置，其中狭窄部（40）处的连续片段（65）的宽度大于650μm。
3.根据权利要求1所述的电路装置，其中在连续片段（65）中引入狭长的第一槽（51），该第一槽（51）延伸直到狭窄部（40）并且以垂直于上侧（5a）的方向（v）在第一槽（51）的整个长度（151）上完全穿透所述连续片段（65）。
4.根据权利要求2或3所述的电路装置，其中能够确定从第一片段（61）向第二片段（62）延伸并且与第一槽（51）相交的直线（g1，g2）。
5.根据权利要求1至3之一所述的电路装置，其中不能够确定从第一片段（61）向第二片段（62）延伸并且在此与狭窄部（40）相交的直线。
6.根据权利要求2或3所述的电路装置，其中第一槽（51）沿着并联电阻（3）的一侧、两侧、三侧或四侧延伸。
7.根据权利要求2或3所述的电路装置，其中第一槽（51）围绕第二片段（62）延伸，使得狭窄部（40）布置在第一槽（51）的两个彼此相对的末端之间。
8.根据权利要求2或3所述的电路装置，其中将狭长的第二槽（52）引入到连续片段（65）中，该第二槽（52）延伸直到狭窄部（40）并且以垂直于上侧（5a）的方向（v）在第二槽（52）的整个长度（152）上完全穿透所述连续片段（65）。
9.根据权利要求1至3之一所述的电路装置，其中导电连接（4）在第一片段（61）与第二片段（62）之间仅仅由连续片段（65）形成。
10.根据权利要求1至3之一所述的电路装置，其中导电连接（4）包括至少一个导电元件，其中每个导电元件
在狭窄部（40）的一侧上被导电地施加到金属化层（6）上并且在那里与第一片段（61）导电地连接；以及
在狭窄部（40）的另一侧上被导电地施加到金属化层（6）上并且在那里与第二片段（62）导电地连接。
11.根据权利要求10所述的电路装置，其中至少一个导电元件被构造成：
接合到金属化层（6）上的接合线或扁平接合带；
被施加到金属化层（6）上的焊剂层；
被施加到金属化层（6）上并且与该金属化层（6）导电地焊接、粘接或烧结在一起的金属片。
12.根据权利要求1至3之一所述的电路装置，具有第二功率半导体芯片（2），该第二功率半导体芯片（2）
被布置在金属化层（6）的第三片段（63）上，其中第三片段（63）与第一片段（61）间隔开；
具有第二下芯片负载接线端子（21），该第二下芯片负载接线端子（21）与第三片段（63）导电地连接；
与第一功率半导体芯片（1）串联成半桥。
13.根据权利要求1至3之一所述的电路装置，其中
并联电阻（3）具有宽度和大于该宽度的长度（13）；
在第一片段（61）与第二片段（62）之间在狭窄部（40）处的整个导电连接（4）在至少一个截平面（E2，E3，E4）中具有圆直径（D40）小于所述长度（13）的90％和/或大于650μm的截面。
14.根据权利要求1至3之一所述的电路装置，其中并联电阻（3）具有：掺杂的半导体本体（30），下主接线端子（31）被施加到该半导体本体（30）上；以及上主接线端子（32），该上主接线端子（32）在掺杂的半导体本体（30）的背向下主接线端子（31）那侧被施加到半导体本体（30）上。
15.一种具有一个或至少两个分别根据权利要求1至14之一构造的电路装置的功率半导体模块，其中在至少两个电路装置的情况下成立的是，这些电路装置在相应的扁平绝缘载体和相应的结构化的金属化层方面被以如下尺寸相同地构造，即使得并联电阻相对于相应的第二片段被布置在不同位置处。
16.根据权利要求15所述的功率半导体模块，其中在至少两个电路装置的情况下成立的是，所述至少两个电路装置中的每个的绝缘载体（8）都被一体化构造。
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CN102364345A (zh) 2012-02-29

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