CN102338849A - Insert for test handler - Google Patents

Insert for test handler Download PDF

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Publication number
CN102338849A
CN102338849A CN2011101991506A CN201110199150A CN102338849A CN 102338849 A CN102338849 A CN 102338849A CN 2011101991506 A CN2011101991506 A CN 2011101991506A CN 201110199150 A CN201110199150 A CN 201110199150A CN 102338849 A CN102338849 A CN 102338849A
Authority
CN
China
Prior art keywords
semiconductor element
terminal
insert
guide portion
loading chute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011101991506A
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Chinese (zh)
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CN102338849B (en
Inventor
具泰兴
黄正佑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Techwing Co Ltd
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Techwing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Techwing Co Ltd filed Critical Techwing Co Ltd
Publication of CN102338849A publication Critical patent/CN102338849A/en
Application granted granted Critical
Publication of CN102338849B publication Critical patent/CN102338849B/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2865—Holding devices, e.g. chucks; Handlers or transport devices
    • G01R31/2867—Handlers or transport devices, e.g. loaders, carriers, trays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R33/00—Coupling devices specially adapted for supporting apparatus and having one part acting as a holder providing support and electrical connection via a counterpart which is structurally associated with the apparatus, e.g. lamp holders; Separate parts thereof
    • H01R33/74—Devices having four or more poles, e.g. holders for compact fluorescent lamps
    • H01R33/76—Holders with sockets, clips, or analogous contacts adapted for axially-sliding engagement with parallely-arranged pins, blades, or analogous contacts on counterpart, e.g. electronic tube socket

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Environmental & Geological Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The invention provides an insert for a test handler. According to the insert, the following techniques with respect to an insert used fro loading a ball grid array semiconductor element are disclosed, namely, guiding parts are formed merely near four corners of a supporting bench supporting the semiconductor element, therefore, manufacture single cost of the insert is reduced, manufacture procedures of the insert are easier, and loading reject ration of the semiconductor element is also reduced.

Description

The insert that is used for Test handler
Technical field
The present invention relates to Test handler, especially, relate to the insert that can load spherical semiconductor element.
Background technology
Semiconductor element includes wire type (thin-type small-size encapsulation (TSOP according to the shape of electrical contact terminal; Thin Small Outline Package), small size encapsulation (SOP; Small Outline Package), slim quad flat package (TQFP; Thin Quad Flat Pack), quad flat package (QFP, Quad Flat Pack)) semiconductor element and sphere (BGA (BGA, Ball Grid Array), thin space BGA (FBGA; Fine-Pitch Ball Grid Array)) semiconductor element the present invention relates to load the insert of spherical semiconductor element.
In the spherical semiconductor element; The terminal of ball shape (below; Abbreviate " terminal " as) be arranged in its bottom surface with the ranks form; About the technology of the insert that can load this spherical semiconductor element Korea S's publication 10-2005-0009066 number (denomination of invention: the technology that the carrier module that is used for the semiconductor element test separator) is proposed (below, be called " prior art ") is arranged.
In the prior art, the marginal position of guide hump and the semiconductor element outside joins and forms.
In addition, the size of the semiconductor element of wafer (wafer) state begins to diminish gradually along with the development of technology and designing technique.But even the size of the semiconductor element of wafer state diminishes, the size of packed semiconductor element can't reduce therewith pro rata.Its reason is, is restricted aspect the spacing between size that reduces terminal and terminal.One in this restriction does, the electric connection of the precision when testing packed semiconductor element between desired terminal and the tester.
In the 1Gb DRAM packaging part of current use, diameter be 78 of the terminals of 0.45mm with the 0.8mm spacing arrangement, if the accuracy of testing apparatus is enhanced, can expect that then the size of packed semiconductor element can be littler.
But; In the prior art; Each marginal position outside of guide hump and semiconductor element joins and forms continuously; Therefore become spacing between littler or terminal when becoming narrower when the size of terminal; Not only the processing precise degree of each guide hump is required strictly more, and because the Redundancy Design value that the manufacturing tolerance of the terminal of the manufacturing tolerance that in the insert manufacture process, takes place, semiconductor element and the spacing tolerance between terminal etc. cause becomes not enough, so it is very high that bad probability takes place.
In addition; In the prior art, because manufacturing tolerance takes place when semiconductor element is loaded into insert, thereby causing being difficult to all correctly is inserted between the guide hump gabarit terminal; Wherein, each marginal position outside of said guide hump and semiconductor element joins and forms.
Summary of the invention
The object of the present invention is to provide the technology that on the brace table of the downward disengaging that is used to prevent semiconductor element, only forms the guide portion of minimum number.
The insert that is used for Test handler according to the present invention in order to achieve the above object comprises: have can settle spherical semiconductor element (below; Abbreviate " semiconductor element " as) the main body of loading chute; Wherein, Said spherical semiconductor element has spherical terminal (below, abbreviate " terminal " as) in the bottom; Can clamp the clamping device of the semiconductor element of the loading chute that is placed in said main body; Wherein, But the bottom of said loading chute is formed with the brace table of the marginal position of support semiconductor element; To be used to preventing that the semiconductor element downward direction that is placed in said loading chute breaks away from; Said brace table has a plurality of guide portion of the installation position that can guide semiconductor element and between the linearity sector between guide portion and the guide portion, the length sum between between said linearity sector can guarantee with the linearity sector between the quantity of terminal of the corresponding semiconductor element of length more than quantity by the terminal of the semiconductor element of said a plurality of guide portion guiding.
Said a plurality of guide portion preferably lays respectively at by the formed four jiaos of corner parts that expose the hole in the position, inside edge of said brace table, and wherein, the terminal that is placed in the semiconductor element of loading chute exposes downwards through the said hole of exposing.
At least one guide hump in the said guide hump can inwards protrude than the residue guide hump more.
Said guide portion can comprise can be inserted in the terminal of arranging with tetragonal attitude in the bottom of semiconductor element with the guide hump between the adjacent terminal of second spacing; Wherein, said second gap ratio is wideer with first spacing between the adjacent terminal of first spacing.
Aforesaid the present invention has following effect.
At first, through making the minimized part that requires accuracy that reduces of guide portion, therefore can make the manufacturing of insert become easy and can reduce its manufacturing unit price.
Second; As long as guide portion is accurate; Therefore for other part; The manufacturing tolerance of the manufacturing tolerance that not only takes place in the insert manufacture process, the terminal of semiconductor element and the spacing tolerance between the terminal are compensated, and the manufacturing tolerance that takes place in the time of can also making semiconductor element be loaded into insert is compensated, so can reduce improper stowage.
Therefore, owing to support further to dwindle by the size of the terminal of the semiconductor element of encapsulation ultimately or further shorten the spacing between the terminal, thereby the size of the semiconductor element that can reduce to encapsulate.
Description of drawings
Fig. 1 is the ground plan that is loaded into the semiconductor element of the insert that is used for Test handler according to of the present invention;
Fig. 2 is the planimetric map according to the insert that is used for Test handler of first embodiment of the invention;
Fig. 3 is the enlarged drawing that the major part of the insert of Fig. 2 is amplified, and it conceptually illustrates the state that semiconductor element is loaded;
Fig. 4 is the enlarged drawing that amplifies according to the major part of the insert of second embodiment of the invention, and it conceptually illustrates the state that semiconductor element is loaded.
The explanation of main label: 100 is insert, and 110 is main body, and 111 is loading chute, and 112 is brace table, and 112a to 112d is a guide portion, and 112a-1 to 112a-5,211a-1 are guide hump, and 113 for exposing groove, and 121,122 is clamping device.
Embodiment
Below, illustrate and describe according to a preferred embodiment of the invention above-mentioned, but succinct for what describe, omit or the description of reduction repetition as far as possible.
<u ><> for semiconductor element;</u>
Fig. 1 is for the ground plan that can be loaded into according to the semiconductor element D of insert of the present invention.
As shown in Figure 1, the size that is arranged in the terminal of semiconductor element D has the diameter of A, adjacent terminal (for example, b 3And b 4Terminal) mainly keep the first spacing B (B＞A), symbol b 1And b 2Terminal between keep and compare the second wideer spacing C of first spacing (C＞B).Certainly, can be according to performance, the spacing between the terminal of semiconductor element can be merely first spacing, and does not comprise second spacing.
As an example, when the diameter A of terminal was 0.325mm, terminal was arranged with the 0.5mm as first spacing equally spacedly; When the diameter A of terminal was 0.25mm, terminal was with first spacing of 0.4mm and second spacing arrangement of 0.52mm.
<u ><The first Shi Shili > for insert;</u>
Fig. 2 is for the planimetric map according to the insert 100 of the first embodiment of the present invention.
As shown in Figure 2, insert 100 comprises main body 110 and a pair of clamping device 121,122.
Be formed with loading chute 111 and brace table 112 on the main body 110.
Load semiconductor element on the loading chute 111, brace table 112 break away from downwards for the semiconductor element that prevents to be placed in loading chute 111 and the marginal position of support semiconductor element around.In addition, brace table 112 has guide portion 112a, 112b, 112c, the 112d to the installation position of four jiaos of side directed semiconductor elements of corner part that expose hole 113, and wherein, the said hole 113 of exposing is formed by the position, inside edge of said brace table 112.At this, expose hole 113 terminal of the semiconductor element that is placed in loading chute 111 is exposed downwards.
In addition, Fig. 3 conceptually illustrates the state that semiconductor element D is loaded into the insert 100 of Fig. 2.
As shown in Figure 3; Guide portion 112a (for ease; Use description to replace description to remaining guide portion 112b, 112c and 112d to the guide portion of symbol 112a) have a plurality of guide hump 112a-1,112a-2,112a-3,112a-4,112a-5, in the insertion groove that forms by these guide humps 112a-1,112a-2,112a-3,112a-4,112a-5 (omission label), be inserted with the corner part that is positioned at tetragonal attitude among the terminal b that arranges with tetragonal attitude in the bottom of semiconductor element D and be positioned at the terminal b of gabarit.
In this example, guide hump 112a-1,112a-2,112a-3,112a-4,112a-5 are formed on the angle part, turning, but according to circumstances, the part that guide hump is formed on except that corner part is also harmless.
In addition, (for example, between the guide portion of the guide portion of label 112a indication and label 112b indication, between the guide portion of the guide portion of label 112b indication and label 112d indication) has L between the linearity sector between a side guide and the adjacent opposite side guide portion 1, L 2L between this linearity sector 1, L 2Design the design of insert 100 and manufacturing are become easily, and bring and the reduction of this easily suitable manufacturing unit price.In the present embodiment, L between the linearity sector 1, L 2Be furnished with 15 or 8 terminal b (is benchmark with the terminal center), but according to performance, L between the linearity sector 1, L 2Length as long as longer than the first spacing B (at least than the spacing between adjacent two terminals), then can realize the present invention as expected.
Certainly, preferably, (comprise L between the linearity sector between a plurality of linearity sectors 1, L 2And remain between two linearity sectors) the length sum should be able to guarantee following condition, that is, and (comprise L between the linearity sector 1, L 2And remaining between two linearity sectors) quantity of the terminal b of corresponding semiconductor element D is more than the quantity by the terminal b of the semiconductor element D of a plurality of guide portion 112a, 112b, 112c, 112d guiding.That is, be preferably the quantity that minimizes the semiconductor element b that supports by a plurality of guide portion 112a, 112b, 112c, 112d, as long as correctly be arranged to not formation problem of insert 100 for semiconductor element D.
As shown in Figure 3, (comprise L between the linearity sector between this a plurality of linearity sectors 1, L 2And remain between two linearity sectors) be positioned at the gabarit part of the terminal b of semiconductor element D.
In addition; The guide hump of label 112a-1 indication among a plurality of guide hump 112a-1,112a-2,112a-3,112a-4, the 112a-5; Than residue guide hump 112a-2,112a-3,112a-4,112a-5, inwards direction is (when cutting apart loading chute 111 equably through the straight line Z of the center O of loading chute 111 1, Z 2Direction) many protrusion t.The guide hump of this label 112a-1 indication is formed at and label b 1And b 2Between the corresponding position of second spacing, this is to have considered the wide situation of second gap ratio, first spacing.When as semiconductor element D is standardized as only the spacing between the terminal b of some part when wideer above-mentionedly; The size of guide hump 112a-1 that can be through will be corresponding with this part forms the guiding of the bigger clear and definite semiconductor element D of coming; Thereby can improve the accuracy of proving installation, therefore can aspect the spacing between size that reduce terminal b or the terminal b bigger help arranged.
<u ><The second Shi Shili > for insert;</u>
Fig. 4 is the planimetric map of major part that is in the insert according to a second embodiment of the present invention 200 of the state that is mounted with semiconductor element D.
As shown in Figure 4, in the insert 200 according to second embodiment, brace table 212 only has and is inserted in to compare terminal (for example, the label b that the second wide spacing of first spacing is kept 1And b 2The terminal of indication) the guide hump 211a-1 between, 211a-2,211a-3,211a-4, the minimizing of the convenience of further thus expectation manufacturing insert 200 and the production unit price that brings thereof.
Certainly, form L between the linearity sector between guide hump 211a-1,211a-2,211a-3, the 211a-4 3
As stated; Carried out detailed description by embodiment for invention with reference to accompanying drawing; But the foregoing description only is the description for preferred exemplary of the present invention; Therefore should the present invention be interpreted as to be confined to the foregoing description, protection scope of the present invention should be understood that scope and the equivalents thereof that claims are asked.

Claims (5)

1. an insert that is used for Test handler is characterized in that, comprising:
Main body with the loading chute that can settle spherical semiconductor element, wherein, said spherical semiconductor element has spherical terminal in the bottom;
The clamping device of semiconductor element that can clamping be placed in the loading chute of said main body,
Wherein, the bottom of said loading chute is formed with the brace table of marginal position that can the support semiconductor element, being used to preventing that the semiconductor element that is placed in said loading chute breaks away from downwards,
Said brace table has a plurality of guide portion of the installation position that can guide semiconductor element and between the linearity sector between guide portion and the guide portion, the length sum between between said linearity sector can guarantee with the linearity sector between the quantity of terminal of the corresponding semiconductor element of length more than quantity by the terminal of the semiconductor element of said a plurality of guide portion guiding.
2. the insert that is used for Test handler according to claim 1 is characterized in that,
Said a plurality of guide portion is positioned at respectively by the formed four jiaos of corner parts that expose the hole in the position, inside edge of said brace table, and wherein, the terminal that is placed in the semiconductor element of loading chute exposes downwards through the said hole of exposing.
3. the insert that is used for Test handler according to claim 1 is characterized in that,
At least one guide hump in the said guide hump inwards protrudes than the residue guide hump more.
4. the insert that is used for Test handler according to claim 1 is characterized in that,
Said guide portion comprise can be inserted in the terminal of arranging with tetragonal attitude in the bottom of semiconductor element with the guide hump between the adjacent terminal of second spacing; Wherein, said second gap ratio is wideer with first spacing between the adjacent terminal of first spacing.
5. an insert that is used for Test handler is characterized in that, comprising:
Main body with the loading chute that can settle spherical semiconductor element, wherein, said spherical semiconductor element has spherical terminal in the bottom;
The clamping device of semiconductor element that can clamping be placed in the loading chute of said main body,
Wherein, the bottom of said loading chute is formed with the brace table of marginal position that can the support semiconductor element, being used to preventing that the semiconductor element that is placed in said loading chute breaks away from downwards,
Said brace table has between a plurality of guide portion of the installation position that can guide semiconductor element and at least one guide portion and the linearity sector between another guide portion in said a plurality of guide portion; Said a plurality of guide portion is positioned at respectively by the formed four jiaos of corner parts that expose the hole in the position, inside edge of said brace table; Wherein, the terminal that is placed in the semiconductor element of loading chute exposes downwards through the said hole of exposing.
CN201110199150.6A 2010-07-15 2011-07-12 Insert for test handler Active CN102338849B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100068728A KR101556324B1 (en) 2010-07-15 2010-07-15 Insert for test handler
KR10-2010-0068728 2010-07-15

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CN102338849A true CN102338849A (en) 2012-02-01
CN102338849B CN102338849B (en) 2014-10-29

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103785619A (en) * 2012-10-26 2014-05-14 泰克元有限公司 Insert for test sorting machine

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102836829A (en) * 2012-09-19 2012-12-26 无锡红光微电子有限公司 TO251/252 sorter feed zone holding block structure
KR101715827B1 (en) * 2012-09-27 2017-03-14 (주)테크윙 Insert for test handler
KR101469218B1 (en) * 2013-05-02 2014-12-10 주식회사 오킨스전자 Insert for loading semiconductor device
KR102229229B1 (en) * 2015-06-17 2021-03-18 (주)테크윙 Insert for test handler
CN106486572B (en) * 2015-09-02 2020-04-28 新世纪光电股份有限公司 Light emitting diode chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050009066A (en) * 2003-07-15 2005-01-24 미래산업 주식회사 Carrier Module for Semiconductor Test Handler
CN1670539A (en) * 2004-03-15 2005-09-21 未来产业株式会社 Transducer assembly for semiconductor device testing processors
CN1822124A (en) * 2001-09-21 2006-08-23 蒂雅克株式会社 Optical disk device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1822124A (en) * 2001-09-21 2006-08-23 蒂雅克株式会社 Optical disk device
KR20050009066A (en) * 2003-07-15 2005-01-24 미래산업 주식회사 Carrier Module for Semiconductor Test Handler
CN1670539A (en) * 2004-03-15 2005-09-21 未来产业株式会社 Transducer assembly for semiconductor device testing processors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103785619A (en) * 2012-10-26 2014-05-14 泰克元有限公司 Insert for test sorting machine
CN103785619B (en) * 2012-10-26 2017-03-01 泰克元有限公司 Testing, sorting machine plug-in unit
CN106862093A (en) * 2012-10-26 2017-06-20 泰克元有限公司 Testing, sorting machine plug-in unit
CN106862093B (en) * 2012-10-26 2020-01-03 泰克元有限公司 Plug-in for test handler

Also Published As

Publication number Publication date
TW201202723A (en) 2012-01-16
CN102338849B (en) 2014-10-29
TWI429930B (en) 2014-03-11
KR20120007932A (en) 2012-01-25
KR101556324B1 (en) 2015-09-30

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