CN102272907A - 形成倒装芯片互连的原位熔化和回流处理及其系统 - Google Patents
形成倒装芯片互连的原位熔化和回流处理及其系统 Download PDFInfo
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- CN102272907A CN102272907A CN200980153949.2A CN200980153949A CN102272907A CN 102272907 A CN102272907 A CN 102272907A CN 200980153949 A CN200980153949 A CN 200980153949A CN 102272907 A CN102272907 A CN 102272907A
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Abstract
一种用于制造倒装芯片半导体封装的方法,该方法包括处理半导体器件(例如半导体芯片)以及处理器件载体(例如衬底)。半导体器件包括在其表面上形成的凸块结构。衬底包括在其表面上形成的焊接焊盘。半导体芯片被加热至芯片处理温度。芯片处理温度使凸块结构上的焊料部分熔化。衬底被加热至衬底处理温度,其中,所述衬底处理温度可以不同于芯片处理温度。半导体芯片在空间上关于衬底进行对准,从而相应地使凸块结构关于焊接焊盘进行对准。半导体芯片朝向衬底移动,从而使凸块结构邻接焊接焊盘,从而在它们之间形成焊接。还公开了执行上述方法的系统。
Description
技术领域
本发明一般涉及封装半导体部件或器件的方法。更具体地,本发明涉及制备倒装芯片半导体封装的方法。
背景技术
半导体封装一般包括将半导体部件或器件(例如,半导体芯片)包封或容纳在器件载体或衬底内。器件载体或衬底支撑半导体芯片并且便于方便地处理半导体芯片。此外,器件载体包括用于将半导体芯片电连接至外部电路的外部连接或终端。
已知的半导体封装方法,更具体地,在引线框(FCOL)半导体封装上形成倒装芯片的方法采用了电镀引线框。引线框是有图案的金属片。金属片(一般是铜)通常被镀有银、镍或钯中的一种。电镀是必要的,从而防止金属片氧化并且提供表面,其中,焊料将黏附至该表面上,或者当采用导线焊接时,金或铝可焊接至该表面上。金属片的图案提供了用于形成FCOL半导体封装的引线框。
一般地,用于形成FCOL半导体封装的引线框具有包括内部引线部分和外部引线部分的引线。内部引线部分排列成在内部引线部分上具有互连位置的图案,该图案与半导体芯片表面上形成的焊盘的图案相匹配。焊料凸块或焊料球沉积于在半导体芯片表面上形成的焊盘上。焊料凸块的回流便于半导体芯片的焊盘与引线框的焊接,更具体地,便于半导体芯片的焊盘与引线框的内部引线部分上的互连位置的焊接。
然后将半导体芯片放置在引线框上,半导体芯片的焊盘邻接于引线框的内部引线部分上的互连位置。然后将半导体芯片和引线框的组件加热至高温,以回流焊料凸块,从而在半导体芯片和引线框之间形成焊料互连。组件的加热通常是在加热腔或加热炉中进行。由此形成的半导体封装在本领域中被称为FCOL半导体封装。
如上所述用于回流焊料凸块的当前加热处理已被认为是非常耗时的,从而损害了半导体封装的制备或生产效率以及生产能力。
此外,半导体芯片的热膨胀系数(CTE)一般不同于引线框或其他衬底的热膨胀系数。因此,当加热半导体芯片和引线框的组件时,在半导体芯片和引线框之间出现差异膨胀。半导体芯片和引线框之间的差异膨胀会导致半导体芯片的焊盘上的焊料凸块和引线框的内部引线部分上的焊料凸块之间未对准,从而导致半导体芯片和引线框之间焊料互连受损或故障。这种未对准和受损的焊料互连尤其普遍存在于具有精细间距的半导体芯片或封装中。
现代电子设备日益增加的功能、速度和便携性已导致了越来越多的将更多电子部件或元件集成到半导体芯片中的需要。因此,在半导体产业中,半导体芯片的相邻焊盘或电互连之间、以及在相邻焊盘或电互连上形成的焊料凸块之间的间距或距离的减少变得日益重要。
然而,半导体芯片的焊盘或电互连之间减少的间距或距离增加了相邻焊盘或电互连之间桥接的风险和发生,从而导致电短路。
相应地,在相邻焊盘或电连接之间电短路的增加的风险和发生对所制备的半导体封装的可靠性和质量造成不良影响。
因此,本领域技术人员将理解,需要制备倒装芯片半导体封装的改进方法,其能够解决上述问题中至少一个。
发明内容
为了解决上述问题中的至少一个问题,本发明提供了半导体部件或器件封装的示例性方法。
根据本发明的一个方面,公开了一种用于器件封装的方法,所述方法包括:将半导体器件加热至第一温度。所述半导体器件包括多个凸块结构,所述多个凸块结构的每一个都包括焊料部分。所述第一温度至少是所述多个凸块结构的每一个的所述焊料部分的熔化温度。所述方法进一步包括将衬底加热至第二温度,所述衬底包括多个接触焊盘;以及在加热所述半导体器件和所述衬底之后,通过使用对准装置在空间上使所述多个凸块结构与所述多个接触焊盘对准。在将所述半导体器件加热至所述第一温度期间,所述半导体器件远离所述衬底设置,随后所述半导体器件和所述衬底中的至少一个可向另一个位移,从而使所述多个凸块结构的每一个与所述多个接触焊盘中相应的一个接触焊盘相邻接。
根据本发明的第二方面,公开了一种用于封装器件的系统,所述系统包括:用于将半导体器件加热至第一温度的装置。所述半导体器件包括多个凸块结构,所述多个凸块结构的每一个都包括焊料部分。所述第一温度至少是所述多个凸块结构的每一个的所述焊料部分的熔化温度。所述系统进一步包括:用于将衬底加热至第二温度的装置,所述衬底包括多个接触焊盘。所述系统进一步包括对准装置,所述对准装置用于在加热所述半导体器件和所述衬底之后,在空间上使所述多个凸块结构与所述多个接触焊盘对准。在将所述半导体器件加热至所述第一温度期间,所述半导体器件远离所述衬底设置。将半导体器件加热至第一温度使得焊料部分能够达到处于熔融状态的熔点。随后,所述半导体器件和所述衬底中的至少一个可向另一个位移,从而使所述多个凸块结构的每一个与所述多个接触焊盘中相应的一个接触焊盘相邻接。所述半导体器件和所述衬底中的至少一个的厚度被校准,从而控制所述半导体器件和所述衬底中的至少一个向另一个的位移。
附图说明
下面将参照附图描述本发明的示例性实施方式,在附图中:
图1是根据本发明的实施方式用于制造倒装芯片半导体封装的示例性方法的部分方法流程图;
图2是在图1的示例性方法的步骤中执行的示例性半导体芯片处理过程的部分过程流程图;
图3a至图3h示出了图2的示例性半导体芯片处理过程的步骤;
图4是图1的示例性方法的步骤中执行的示例性衬底处理过程的部分过程流程图;
图5a至图5i示出了图4的示例性衬底处理过程的步骤;
图6是由图4的示例性衬底处理过程的步骤执行的示例性焊剂转移过程的部分过程流程图;
图7示出了图6的示例性焊剂转移过程的步骤;
图8是图1的示例性方法的步骤中执行的示例性焊接过程的部分过程流程图;
图9a至图9d示出了图6的示例性焊接过程的步骤;
图10示出了在图6的示例性焊接过程期间,用于管理位移高度的部分公式;
图11示出了图1的示例性方法的关键步骤的部分过程流程图;
图12示出了在图1的示例性方法期间的示例性温度曲线;
图13示出了通过图1的示例性方法制造的倒装芯片半导体封装的部分截面图;
图14示出了图13的倒装芯片半导体封装分解的部分截面图“A”;
图15a至图15b提供了在通过图1的示例性方法制造的倒装芯片半导体封装的衬底上形成的焊料凸块或互连之间的间距补偿的图样概况;
图16示出了根据本发明的实施方式用于制造倒装芯片半导体封装的示例性系统的部分系统示意图;
图17和图18示出了图16的示例性系统的示例性焊接台的部分等距视图;以及
图19示出了图16的示例性系统的水制冷机制的部分等距视图。
具体实施方式
制造倒装芯片半导体封装的现有方法是,在将半导体芯片和器件载体(例如,衬底)的组件加热以回流焊料凸块并在半导体芯片和器件载体之间形成焊料互连之前,通常将在半导体芯片的焊盘或柱上形成的焊料凸块放置于在器件载体上形成的接触焊盘上。这个加热过程通常是耗时的,从而对倒装芯片半导体封装的制造或生产效率以及生产能力造成不利影响。现有方法一般也包括使用相当大的力来使半导体芯片的焊盘邻接于器件载体的接触焊盘,从而产生可靠的焊点。因此,在其加热期间使用相当大的力会对半导体芯片或器件载体造成损害。此外,制造倒装芯片半导体封装的现有方法与在半导体芯片和器件载体之间形成的相邻互连之间的电短路的问题相关联。相邻互连之间的电短路的问题尤其普遍存在于具有精细间距的半导体芯片和封装中。而且,在半导体芯片和器件载体之间的互连或焊料互连的形成过程中,半导体芯片关于器件载体的准确定位或对准也会难以实现。因此,本发明提供了用于封装半导体器件的改进方法,更具体地提供了用于制造半导体倒装芯片封装的改进方法,其能够解决上述问题中的至少一个。
为了简洁和清楚,下文中本发明实施方式的描述仅限于制造或生产倒装芯片半导体封装的方法。然而,本领域技术人员将理解的是,这并没有排除本发明的其他应用,在其他应用中需要普遍存在于本发明的各种实施方式中的基本原则,如操作、功能或性能特征。
根据本发明的实施方式,提供了制造倒装芯片半导体封装10的示例性方法100。在图1中示出了示例性方法100的方法流程图。
在示例性方法100的步骤110中,处理半导体器件或部件。半导体器件例如是半导体芯片12,并且在下文中被称为半导体芯片12。
优选地,通过执行本发明所提供的示例性半导体芯片处理过程200,发生半导体芯片12的处理。图2中示出了示例性半导体芯片处理过程200的过程流程图。
在示例性半导体芯片处理过程200的步骤210中,提供了半导体芯片12。优选地,半导体芯片12设置在芯片托盘14或包含有多个半导体芯片12的芯片容器上。半导体芯片12优选地包括在其表面上形成的凸块结构16。这种凸块结构16优选地包括金属桩18,在金属桩18的自由端处形成有焊料部分20。用于焊料部分20的焊料类型包括但不限于金属和金属合金,如银、锡。
可选地,凸块结构16与第09/564,382号美国专利申请中描述的柱凸块的凸块结构相似,该申请以引用方法并入本说明书。可选地,半导体芯片12包括在半导体芯片12的表面上形成的接触焊盘(集合在一起称为焊盘阵列)上形成的凸块或焊料凸块。凸块结构16用于促进半导体芯片12与衬底22或外部电路的电通信。本领域技术人员将理解的是,可选的凸块结构或电互连也可用于执行凸块结构16的上述功能。
在步骤220,半导体芯片12从芯片托盘14转移到芯片拾取工具24。为了执行步骤220,转移工具26或夹持器用于从芯片托盘14拾取半导体芯片12。优选地,转移工具26采用真空或抽吸以拾取半导体芯片12,并且确保将半导体芯片12固定至转移工具26。然后,转移工具26将半导体芯片12竖直翻转180度,以将半导体芯片12放置在拾取位置,以用于随后由芯片拾取工具24拾取或者转移至拾取工具24。然而,本领域技术人员将理解的是,转移工具26可以可选地被移动或者旋转,从而对半导体芯片12进行移动和定位。
然后,在步骤230中测量半导体芯片12的厚度或高度。可选地,半导体芯片12被转移到高度校准台(未示出),以测量半导体芯片12的厚度或高度。使用编码器(未示出)测量半导体芯片12的厚度或高度,该编码器连接至芯片拾取工具24,以确定其空间位置。优选地,通过首先读回与第一视觉透镜30相接触的点处的编码器值(其用作基准面),随后当与第一视觉透镜30上放置的校准量规相接触时测量附加的编码器值,从而执行芯片拾取工具24的校准。
在步骤230中,半导体芯片12也被定向或对准。更具体地,半导体芯片12被定向或对准,从而对应于在芯片预热台28上形成的槽(未示出)。通过使用第一视觉透镜30,半导体芯片12的定位或定向是很方便的。第一视觉透镜30使得在定位到芯片预热台28之前,能够视觉校正或视觉对准半导体芯片12。
在随后的步骤240中,半导体芯片12被放置在芯片预热台28上。更具体地,半导体芯片12优选地放置于在芯片预热台28上形成的槽上。半导体芯片12优选地通过真空或抽吸被保持或固定至芯片预热台28。可选地,半导体芯片12通过机械装置(例如通过夹持器(未示出))被保持或固定至芯片预热台28。
然后在步骤250中,将放置在芯片预热台28上的半导体芯片12预加热至预定温度。预定温度是,例如200℃。通过将半导体芯片12越过一系列加热器34移向焊接工具位置来逐步执行半导体芯片12的预热。更具体地,半导体芯片12被附接到预热缓冲台(也被称为转台),其被旋转以使半导体芯片12越过一系列加热器34移动。加热器34优选地是对流加热器。优选地,预设每个加热器34的温度,从而当半导体芯片12沿着一系列加热器34从一个进行到另一个时,提供对半导体芯片12的增量加热。通过加热器对半导体芯片12的加热可被传导、对流或辐射中的至少之一所影响。而且优选地,根据需要,每个加热器34的温度可以维持不变或者可以改变。
半导体芯片12的逐步预热(这也可被称为半导体芯片12的受控预热)减少或消除了对半导体芯片12的热冲击。本领域技术人员将理解的是,根据需要,通过改变任一个或多个辐射式加热器34的温度,可以调节半导体芯片12的预热曲线(profile)。本领域技术人员还将理解的是,根据需要,通过改变预热台的移动速度和/或半导体芯片12与辐射式加热器34之间的间隔,可以调节半导体芯片12的预热曲线。芯片预热台28的速度控制和半导体芯片12的预热控制可以是手动控制或软件控制的。
如前所述,在步骤250期间,朝向焊接工具位置移动芯片预热台28。在焊接工具位置处,在步骤260中通过焊接工具36拾取半导体芯片12。半导体芯片12优选地通过真空或抽吸被保持或固定至焊接工具36。可选地,半导体芯片12通过机械装置(例如通过夹持器(未示出))被保持或固定至焊接工具36。
优选地,在步骤260中拾取半导体芯片12之前,焊接工具36被预热并且维持在预定的高温。预定的温度优选地足够高,从而足以熔化凸块结构16的焊料部分20。焊接工具36的预定高温例如是260℃。然而,本领域技术人员将理解的是,根据需要,通过本领域公知的方法可以调整预定的高温。还将理解的是,在半导体芯片12被拾取之后,根据需要,焊接工具36的温度可以被调节,更具体地是升高或降低。焊接工具36的温度控制可以是手动控制或软件控制的。
然后在步骤270中,通过焊接工具36将半导体芯片12加热至芯片处理温度。在将半导体芯片12加热至芯片处理温度期间,焊接工具36的温度优选地被维持在预定温度,例如260℃。优选地,芯片处理温度足够高,以加热半导体芯片12,从而熔化在半导体芯片12上形成的凸块结构16的焊料部分20。此外,芯片处理温度优选地足够高,从而足以使凸块结构16的焊料部分20保持在熔融状态或液态。在接收到半导体芯片12之后,根据需要可以改变焊接工具36的温度。使用本领域技术人员已知的方法可以实现焊接工具36的温度的变化或改变。
在步骤280中,附接有半导体芯片12的焊接工具36被定位在第二视觉透镜38之上。第二视觉透镜38便于半导体芯片12关于衬底22进行x、y平移对准和θ角对准。更具体地,第二视觉透镜38便于半导体芯片12的凸块结构16关于在衬底22上形成的焊接焊盘64或凸块结构(也称为互连)进行x、y平移对准和θ角对准。
步骤280的完成优选地完成了半导体芯片12处理过程200。然而,本领域技术人员将理解的是,通过过程200可以附加地执行其他半导体芯片12处理步骤和技术。
示例性方法100进一步包括处理衬底22的步骤120。优选地,同时执行步骤110和步骤120。可选地,顺序执行步骤110和步骤120。
衬底22可以是半导体芯片12的载体,或者是载体的一部分。可选地,衬底22可以是引线框。优选地,通过执行本发明提供的示例性衬底处理过程300,对衬底22进行处理。图4中示出了示例性衬底处理过程300的处理流程图。
在示例性衬底处理过程300的步骤310中,提供了衬底22。优选地,经由衬底盒50提供衬底22。然后在步骤320中,衬底22通过衬底拾取工具52或衬底拾取装置被拾取并且被转移到焊剂台54上。优选地,通过真空或抽吸将衬底22保持或固定至焊剂台54。可选地,衬底22通过机械装置(例如通过夹持器(未示出))被保持或固定至焊剂台54。
在步骤330,焊剂56(也被称为熔剂)从焊剂转移台58被转移至衬底22的表面,更具体地,转移至衬底22的焊接焊盘64上。经由示例性焊剂转移过程400,优选地实现了步骤330。图6中示出了示例性焊剂转移过程400的过程流程图。
在示例性焊剂转移过程400的步骤410中,预定量的焊剂56被分配到焊剂转移台58上。焊剂56或熔剂包括本领域技术人员所公知的一种或多种材料或化学品。在步骤420中,塞子工具60被按压在焊剂转移台58上的焊剂56上。优选地,塞子工具60以预定压力按压在焊剂56上。塞子工具60的末端62是弹性的,并且符合在焊剂转移台58上形成的图案。优选地,在焊剂转移台58上形成的图案对应于在焊剂转移台58上形成的孔或结构(未示出)的图案。优选地,焊剂56包含于在焊剂转移台58上形成的孔或结构内。
根据需要,可以使用本领域技术人员已知的技术来确定并且改变在焊剂转移台58上形成的孔或结构的图案。优选地,焊剂转移台58上的孔或结构的图案对应于在衬底22上形成的焊接焊盘64的图案。当塞子工具60被按压在焊剂转移台58上的焊剂56上时,焊剂56的一部分附接至塞子工具60的末端62或者通过塞子工具60的末端62被拾取。优选地,焊剂转移台58上的孔或结构的图案被确定,从而使从焊剂转移台58转移到衬底22的焊接焊盘64上的焊剂56定位。换句话说,焊剂转移台58上的孔的图案优选地提高了焊剂转移到衬底22的焊接焊盘64上的准确性。
在随后的步骤430中,塞子工具60对准或定位在衬底22的上方。优选地,塞子工具60相对于在衬底22的表面上形成的焊接焊盘64对准或定位。在步骤440中,塞子工具60然后被移动,从而以预定速度和压力按压在衬底22的表面上。
在步骤450中,优选地,将塞子工具60按压到衬底22的表面上引起了焊剂56从塞子工具60的末端62转移到衬底22的表面上。
虽然上面仅描述了示例性焊剂转移过程400,但是本领域技术人员将理解的是,将焊剂56转移到衬底22的表面上的其他方法和设备可以用于执行步骤330。
例如,通过丝网印刷或针转移技术或方法可以实现步骤330中的焊剂56的转移。优选地,针转移的使用使得能够自动对准,并且由于软针设计而为平行度/平面度提供鲁棒性更强的焊剂转移过程。可选地,焊剂56可以被直接分配到衬底22的表面上。
本领域技术人员也将理解的是,焊剂56可以包括本领域技术人员所公知的任一种或多种焊剂材料或熔剂。
焊剂转移过程400也可以替换为使用无流式底部填充。无流式底部填充可以经由本领域技术人员已知的方法转移或分配到衬底22的表面上。例如,无流式底部填充可以通过使用针状物(未示出)直接分配到衬底22上。
在步骤340中,通过使用衬底拾取工具72将在其表面上包含焊剂56的衬底22从焊剂台54转移到衬底预热台66(也被称为衬底预热板或支架)上。优选地,衬底预热台66被预热并且维持在预定的高温,例如150℃。本领域技术人员将理解的是,根据需要,通过本领域已知的技术可以预先确定和改变衬底预热台66的预定高温。
在步骤350,衬底预热台66上的衬底22被加热至转变温度。根据需要,衬底22的转变温度可以选择并且还是可变的。衬底预热台66上的衬底22的加热控制可以是手动控制或软件控制的。
在衬底22已经转移到衬底预热台66上并且被加热至转变温度之后,可选地,可以执行步骤330中发生的焊剂54的转移。
在步骤360中,通过使用衬底转移工具72将衬底22从衬底预热台66转移到焊接台70(也被称为焊接板或支架)。衬底拾取工具52和68以及衬底转移工具72可以是相同的工具。衬底22优选地通过利用真空或抽吸被保持或固定至焊接台70上。可选地,衬底通过可选的机械装置或机制被保持或固定至焊接台70上。优选地,真空或抽吸被应用到保持在焊接台70上的衬底22上的特定或预定位置处。更优选地,特定位置不对应于衬底22上的焊接焊盘64的位置。这是为了防止在加热衬底22时,衬底22变形或翘曲。
优选地,焊接台70被预热并且维持在预定的高温。焊接台70的预定高温是,例如200℃。根据需要,使用本领域技术人员已知的技术可以选择并且改变焊接台70的预定高温。焊接台70的温度可以是手动控制或软件控制的。
焊接台70的温度可以根据很多因素来选择和改变。例如,焊接台70的温度可以根据凸块结构16上的焊料部分20的熔点来选择和改变。优选地,焊接台70的温度维持在这样的温度,其使得不能够使半导体芯片12的凸块结构16上的焊料部分20熔化,并且不能够使半导体芯片12的凸块结构16上的焊料部分20维持在熔融状态或液态。进一步优选地,焊接台70的温度维持在比半导体芯片12的凸块结构16的焊料部分20的熔点更低的温度。焊接台70的温度可以进一步依赖于焊剂的活化温度或者依赖于无流式底部填充的固化温度(当无流式底部填充代替焊剂使用时)。
在焊接台70接收衬底22之后,焊接台70的温度可以根据需要改变。使用本领域技术人员已知的方法可以实现焊接台70的温度的变化或改变。焊接台70被设计为减少或防止热量从衬底22消散到焊接台70。优选地,焊接台70被设计为使得可能存在于衬底22上的铜迹线不会接触到焊接台70,从而减少热消散或热损失。可选地,焊接台70被设计为,其与铜迹线接触的区域由绝热材料(包括但不限于陶瓷)构成。
然后在步骤370中,通过焊接台70将位于焊接台70上的衬底22进一步加热至衬底处理温度。衬底22的衬底处理温度优选地低于半导体芯片12的芯片处理温度。可选地,衬底22的衬底处理温度优选地等于或类似于半导体芯片12的芯片处理温度。优选地,在步骤350中将衬底22加热至转变温度减少了步骤370中将衬底22进一步加热至衬底处理温度所需的时间。焊接台70的温度优选地维持在预定的高温,例如200℃。
在步骤380中,通过衬底厚度测量工具74或设备测量并记录衬底22的厚度或高度。衬底厚度测量工具74优选地参照由焊接台70限定的基准来确定衬底22的厚度或高度。进一步优选地,衬底厚度测量工具74测量不包括焊接焊盘64和焊剂56的衬底22的厚度。优选地,衬底厚度测量工具74进一步测量衬底22上焊剂56的厚度和衬底22上形成的焊接焊盘64(也被称为接触焊盘)的高度中的至少一个。
然后在步骤390中,焊接台70被定位在第二视觉透镜38的下方。优选地,第二视觉透镜38便于衬底22关于半导体芯片12进行x、y平移对准和θ角对准中的至少一个。更具体地,第二视觉透镜38便于在衬底22上形成的焊接焊盘64相对于半导体芯片12上形成的凸块结构16进行x、y平移对准和θ角对准。可选地,第二视觉透镜可以被称为上下查看相机,以便于衬底22关于半导体芯片12进行x、y平移对准和θ角对准中的至少一个。然而,本领域技术人员将理解的是,通过第三视觉透镜(未示出)或本领域中已知的其他对准装置可以实现在衬底22上形成的焊接焊盘64相对于半导体芯片12上形成的凸块结构16进行x、y平移对准和θ角对准。
步骤110中的半导体芯片12的处理以及步骤120中的衬底22的处理为步骤130中半导体芯片12和衬底22之间的焊接做准备。优选地,经由本发明提供的示例性焊接过程500,进行步骤130中半导体芯片12和衬底22之间的焊接。图8中示出了示例性焊接过程500的过程流程图。
如前所述,第二视觉透镜38便于半导体芯片12关于衬底焊接焊盘位置进行x、y线性对准和θ角对准中的至少一个。更具体地,第二视觉透镜38便于半导体芯片12上形成的凸块结构16相对于在衬底22上形成的焊接焊盘64进行x、y线性对准和θ角对准中的至少一个。
在步骤510中,焊接工具36将半导体芯片12定位并对准在位于焊接台70上的衬底22的上方。优选地,步骤510中将半导体芯片12定位在衬底22的上方使得半导体芯片12的凸块结构16对准衬底22的焊接焊盘64。
优选地,第二视觉透镜38便于限定半导体芯片12的第一坐标系以及与半导体芯片12的凸块结构16相交并在设置上相对应的多个基准轴线。此外,第二视觉透镜38进一步便于限定衬底22的第二坐标系以及与衬底22的焊接焊盘64重叠并且在设置上相对应的多个基准顶点。优选地,第二视觉透镜38与可编程控制器(未示出)连接或电通信。
可编程控制器优选地被编程,以限定第一坐标系和第二坐标系。此外,可编程控制器使得第一坐标系能够对准第二坐标系,以使得多个基准轴线中的每一个均与多个基准顶点中相应的一个顶点基本上重叠,从而使半导体芯片12的凸块结构16能够与衬底22的焊接焊盘64准确地空间对准,或者帮助半导体芯片12的凸块结构16与衬底22的焊接焊盘64准确地空间对准。
半导体芯片12优选地处于芯片处理温度,而且衬底22优选地处于衬底处理温度。将半导体芯片12维持在芯片处理温度优选地将其凸块结构16上的焊料部分20维持在熔融状态或液态。
在步骤520中,进行焊接工具36朝向焊接台70的第一阶段移动或位移。焊接工具36朝向焊接台70的移动使得附接至焊接工具36的半导体芯片12朝向焊接台70上的衬底22位移。步骤520中焊接工具36的第一阶段移动优选地是快速完成的,这可以是预定的并且根据需要是可以改变的。
在步骤530中,进行焊接工具36进一步朝向焊接台70的第二阶段移动或位移。焊接工具36朝向焊接台70的移动使得附接至焊接工具36的半导体芯片12朝向焊接台70上的衬底22位移。焊接工具36的第二阶段移动优选地是以比焊接工具36的第一阶段移动更慢的速度完成的。在第二阶段移动期间,焊接工具36的更慢速度使得熔融或液体焊料毛细作用或喷洒到相邻焊接焊盘64以及导致不期望的电短路的风险最小化。
步骤520和530便于在步骤540中将半导体芯片12和衬底22定位在焊接位置。根据本说明书提供的内容,本领域技术人员将理解的是,可以实现焊接工具36关于焊接台70的附加阶段的移动或位移。与步骤520中第一阶段移动或步骤530中第二阶段移动的速度相比,在附加阶段移动期间焊接工具36的移动速度更快或者更慢。此外,在附加阶段移动期间焊接工具36的移动可以朝向或者远离焊接台70。
在焊接位置,半导体芯片12的熔融的或液态的焊料部分20接触衬底22的相应焊接焊盘64。在焊接位置处,半导体芯片12和衬底22之间的分离或间隔可以被称为焊接距离(也被称为分离距离)
优选地,根据在步骤380中所测量的衬底22的厚度的需要,焊接距离被确定并且是可变的。进一步优选地,基于步骤230中所测量的半导体芯片12的高度,焊接距离进一步被确定或改变。优选地,半导体芯片12的高度被获取,以包括在其上形成的凸块结构16的高度。图10中示出了测量并管理焊接距离(以及在步骤520至540期间,半导体芯片12和衬底22之间距离)的示例性计算公式。应该理解的是,在步骤520和530中各自的第一阶段移动和第二阶段移动期间,焊接工具36朝向焊接台70的位移幅度分别被仔细地确定并且选择,以将半导体芯片12的凸块结构16定位在衬底22相应的焊接焊盘64上。
在步骤230期间,测量半导体芯片或管芯的高度或厚度(Hd)。在步骤380期间,测量衬底的高度或厚度(Hs)。优选地,在步骤520和530期间,半导体芯片12的位移幅度被称为实际行程。使用图10中所示的示例性计算公式来计算实际行程。优选地,通过从参考高度(Hf)中减去Hd和Hs并且加上预定的压缩偏移值来计算实际行程(即,实际行程=Hf-Hd-Hs+压缩偏移值),参考高度(Hf)是焊接工具36和焊接台70之间的高度或者是半导体芯片12和衬底22之间的高度。增加压缩偏移以克服来自半导体芯片12和衬底22的任何共面差异。焊接距离(以及步骤520至540期间半导体芯片12和衬底22之间的距离)的管理提高了半导体芯片12和衬底22之间形成的焊接的精确性和稳定性。
焊接工具36和焊接台70分别将半导体芯片12和衬底22维持在芯片处理温度和衬底处理温度。在方法100期间,焊接工具36和焊接台70中的每个的温度优选地被仔细地控制和管理。图12中示出了在方法100期间的示例性温度曲线。
优选地,在方法100期间,焊接工具36和焊接台70中的每个的温度均可以根据需要被仔细地、精确地测量、监控和调整。优选地,焊接工具36和焊接台70中的每个的温度的控制和维持相应地使得在焊接过程500期间能够分别对半导体芯片12和衬底22进行热管理。此外,焊接工具36和焊接台70中的每个的温度的控制和维持帮助控制并维持在凸块结构16的焊料部分20和焊接焊盘64之间连结处的温度。
如上所述,重要的是设置并维持焊接工具36的温度,以将半导体芯片12加热至足够高的温度,从而熔化半导体芯片12的凸块结构16上的焊料部分,并且使半导体芯片12的凸块结构16的焊料部分20维持在熔融状态或液态。
优选地,焊接台70被设计并且被构造为防止快速的热排放(即,将热量保持在其中)。优选地,焊接台70包括与其相连接或者并入其中的绝缘层76。绝缘层76有助于通过焊接台70进行缓慢的热排放或者热传递。也就是说,绝缘层76延长了焊接台70内的热量保留。优选地,保留在焊接台70内的热量使凸块结构16的焊料部分20和衬底22的焊接焊盘64之间连结处的温度维持在足够的高温下,从而使焊料部分20维持在熔融状态或液态。绝缘层76优选地在其之中包括气囊或气泡。可选地,绝缘层76由具有低热导率的材料制成。
优选地,水冷机构或机制610连接到焊接台70,用于减少或者防止热量从焊接台70消散到其他部件。水冷机构或机制610优选地包括邻近焊接台70的表面放置的至少一个板,以及至少一个管连接器612,用于循环通过该至少一个板的流体,从而减少从焊接台70的热消散(或者绝缘的)。
在步骤550中,将半导体芯片12和衬底22维持在焊接位置预定时间,从而允许或便于半导体芯片12和衬底22之间形成充分的焊接或互连。更具体地,将半导体芯片12和衬底22维持在焊接位置预定时间,从而便于半导体芯片12的凸块结构16上的焊料部分20和衬底22的焊接焊盘64之间充分地焊接。
优选地,在步骤550期间,半导体芯片12和衬底22达到焊接温度。更具体地,在步骤550期间,半导体芯片12的凸块结构16和衬底22的焊接焊盘64之间的连结达到焊接温度。在步骤550期间的焊接温度优选地处于芯片处理温度和衬底处理温度之间。更具体地,焊接温度低于芯片处理温度并且高于衬底处理温度。
然后,在步骤560中,焊接工具36将半导体芯片12释放到衬底22上。优选地,在步骤560中将半导体芯片12释放到衬底22之前,通过焊接工具36进行空气吹扫。空气吹扫便于从焊接工具36移除或分离半导体芯片12。优选地,空气吹扫的压力被控制,以防止不期望的压力被施加到存在于半导体芯片12和衬底22之间、更具体地存在于半导体芯片12的凸块结构16和衬底22的焊接焊盘64之间的熔化焊料上。然后,半导体芯片12的凸块结构16和衬底22的焊接焊盘64之间的焊料固化,从而完成半导体芯片12和衬底22之间的焊接。
示例性方法100的步骤110至130的性能便于将半导体芯片12焊接至衬底22,从而形成倒装芯片半导体封装10。在图13和图14中示出了倒装芯片半导体封装10的部分截面图。也就是说,示例性方法100的步骤110至130表示封装半导体芯片12的方法中的步骤。
在步骤140中,形成的倒装芯片半导体封装10(更具体地,焊接有衬底22的半导体芯片12的组件)从加热的焊接台70被转移或卸载至卸载台(未示出)。然后,倒装芯片半导体封装10在卸载台上冷却至室温。可选地,当倒装芯片半导体封装10处于卸载台上时,根据需要冷却至不同温度(其低于焊接台的温度)。
优选地,卸载台的温度可以根据需要被控制和改变,从而便于倒装芯片半导体封装10的受控冷却。倒装芯片半导体封装10的冷却可以自然地实现。可选地,倒装芯片半导体封装10的冷却可以通过强制对流冷却实现。对于强制对流冷却,流体(例如氮等不活泼气体)被泵抽向倒装芯片半导体封装10,用于实现其冷却。
可选地,倒装芯片半导体封装10在转移到卸载台上之前,可以转移至一个或多个中间台(未示出)。优选地,中间台的温度在焊接台70的温度和卸载台的温度之间。进一步优选地,对中间台温度的维持或控制便于倒装芯片半导体封装10的受控冷却。对倒装芯片半导体封装10的冷却的控制可以是手动控制或软件控制的。
虽然上面仅描述了用于制造由实施方式提供的倒装芯片半导体封装的示例性方法100,但是本领域技术人员将理解的是,在不脱离本发明范围的情况下,可以对过程200、300、400、500中的一个或多个的步骤或其顺序的进行各种修改。本领域技术人员还将理解的是,方法100的步骤表示封装半导体部件或装置(例如半导体芯片和晶体管)的一般方法中的步骤。
在示例性方法100中,通过焊接工具36的热管理,使半导体芯片12上形成的凸块结构16的焊料部分20维持在熔融状态或液态。然而,根据本说明书提供的内容,本领域技术人员将理解的是,在焊接过程的步骤510至530之前以及在这些步骤期间,半导体芯片12上形成的凸块结构16的焊料部分20可选地可以维持在固态。在这种情况下,在步骤540中将半导体芯片12定位在焊接位置期间,半导体芯片12上形成的凸块结构16的焊料部分20熔化。
根据本说明书提供的内容,本领域技术人员还将理解的是,用于制造倒装芯片半导体封装10的示例性方法100在加热以使半导体芯片12的凸块结构16和衬底22的焊接焊盘64之间的焊料回流期间,使得半导体芯片12的凸块结构16能够相对于衬底22的焊接焊盘64准确地定位,从而有助于半导体芯片12和衬底22之间形成精确且可靠的互连。
通常,与衬底或载体相比,半导体芯片(以及其他半导体装置)具有不同的热膨胀系数(CTE)。加热CTE不同的物质会引起它们不均匀的热膨胀。因此,加热半导体芯片12和衬底22典型地在半导体芯片12和衬底22之间引起不均匀的热膨胀。在本发明的优选实施方式中,对于衬底22的焊接焊盘64进行间距补偿。衬底22的焊接焊盘64之间的间距补偿优选地被计算并且确定,从而抵消由于其不同的热膨胀系数(CTE)所引起的半导体芯片12和衬底22之间的不均匀热膨胀,由此确保在半导体芯片12的凸块结构16和衬底22的其相应焊接焊盘64之间准确地焊接或互连形成。进一步优选地,进行衬底22的焊接焊盘64之间的间距补偿,以防止所形成的互连之间的电短路。图15a至图15b中示出了衬底22的焊接焊盘64的间距补偿的部分图样概况。
可选地,在半导体芯片12的凸块结构16之间执行间距补偿。半导体芯片12的凸块结构16之间的间距补偿优选地被计算并且确定,从而抵消由于其不同的热膨胀系数(CTE)所引起的半导体芯片12和衬底22之间的不均匀热膨胀。
进一步可选地,对于半导体芯片12的凸块结构16并且对于衬底22的焊接焊盘64执行间距补偿,从而抵消由于其不同的热膨胀系数(CTE)所引起的半导体芯片12和衬底22之间的不均匀热膨胀。
上述间距补偿过程或技术优选地确保了通过示例性方法100在半导体芯片12和衬底22之间(更具体地在半导体芯片12的凸块结构16和衬底22的焊接焊盘64之间)精确或接近精确地焊接。此外,上述间距补偿过程或技术优选地使半导体芯片12和衬底22之间的对准偏移或焊接偏移最小化。根据本说明书提供的内容,本领域技术人员将理解的是,在不脱离本发明范围的情况下,还可以对间距补偿过程进行修改。
本发明还提供了用于封装半导体器件或部件的示例性系统600或设备,更具体地,用于制造倒装芯片半导体封装10的示例性系统。图16中示出了示例性系统600。
示例性系统600包括用于执行上述方法100的装置。更具体地,示例性系统600包括用于执行方法100的步骤100至140、执行过程200的步骤210至280、执行过程300的步骤310至390、执行过程400的步骤410至450、执行过程500的步骤510至560中任意一个或多个的装置。上述装置例如是部件、工具、元件或设备,它们可以使用本领域技术人员已知的技术来确定形状和结构。
为了简洁和清楚,下面将进一步描述系统600的一些关键部件。然而,根据本说明书提供的内容,本领域技术人员将理解的是,以下描述并不是对本发明所覆盖的系统600的范围的限制。
如上所述,系统600包括用于执行过程200的步骤210至280的装置。优选地,系统600包括便于提供半导体芯片12的步骤210所使用的半导体芯片供给器台架602。
系统600进一步包括用于测量半导体芯片12的厚度或高度的装置。优选地,半导体芯片12的厚度或高度的测量通过芯片拾取工具24以及上述编码器信息来实现或变得容易。然而,本领域技术人员将理解的是,可选的机构可用于测量半导体芯片12的厚度或高度。
系统600还包括在步骤240期间预热半导体芯片12以及在步骤270期间将半导体芯片12进一步加热至芯片处理温度的加热装置、元件或器件。重点注意的是,芯片处理温度优选地足够高,以使得能够熔化凸块结构16上的焊料部分20。对半导体芯片12的预热和进一步加热中的至少一个的控制和维持是使用本领域技术人员已知的技术来软件控制或手动控制的。
另外,系统600进一步包括用于在过程300中处理衬底22或执行过程300中的步骤310至390的装置。系统600优选地包括用于在步骤310中提供衬底22的衬底供给器台架604。
系统600进一步包括在步骤320中将焊剂56转移到衬底22上的装置。如上所述,通过使用将沉积在焊剂转移台58上的焊剂56转移到衬底22上的塞子工具60,可以执行焊剂转移。可选地,系统60可以包括将焊剂56转移到衬底22上的其他装置或机制。进一步可选地,系统60包括将代替焊剂56的无流式底部填充转移到衬底22上的其他装置或机制。
系统600进一步包括衬底厚度测量工具74,如图5h所示,用于测量衬底22的厚度或高度。本领域技术人员将理解的是,可选的装置或机制可用于测量衬底22的厚度或高度。
系统600进一步包括在步骤350中预热衬底22以及在步骤370中将衬底22进一步加热至衬底处理温度的加热装置、元件或器件。优选地,衬底22由焊接台70加热至衬底处理温度。焊接台70被设计和构造为便于焊接台70的热管理以及放置在其上的衬底22的热管理。图17和图18示出了示例性焊接台70的设计。焊接台70可以包括便于将热量保留在衬底22内(即,防止热量从中排放)的气囊606。焊接台70优选地包括真空槽608。真空槽608便于施加真空或抽吸,以将衬底22固定至焊接台70。真空槽608的形状和位置被预定,从而与存在于衬底22上的铜迹线的位置不一致。
重要的是,系统600被装配并且设计为,在方法100期间对半导体芯片12和衬底22中的每个进行热管理。更具体地,系统600包括在示例性焊接处理500期间对半导体芯片12和衬底22进行热管理的装置或机制。通过使用本领域技术人员已知的一个或多个计算机软件程序以及手动或机械输入中的一种或多种,热管理可以是很方便的。在半导体芯片12移向衬底22之前,系统600优选地使得凸块结构16上的焊料部分20能够维持在熔融状态,以便以后能够在凸块结构16和衬底22的焊接焊盘64之间形成焊接。
系统600进一步包括如图19所示的水冷机制610。水冷机制610包括管连接器扩展612、制冷板614、衬底表基绝缘体616、热板618以及筒式加热器620。优选地,水冷机制610可以连接至焊接台70,从而至少用于便于其绝缘和制冷之一。换句话说,水冷机制610优选地便于焊接台70的热管理。
本领域技术人员将理解的是,系统600进一步包括执行示例性焊接过程500的步骤的装置。优选地,系统600包括第二视觉透镜38(也被称为上下查看相机),用于在示例性焊接过程500的步骤510中使半导体芯片12关于衬底22对准。更具体地,第二视觉透镜38便于半导体芯片12的凸块结构16相对于衬底22的焊接焊盘64精确对准。本领域技术人员将理解的是,系统600可以利用可选的对准装置或机制,从而使半导体芯片12上形成的凸块结构16与衬底22上形成的焊接焊盘64对准。
此外,系统600使得能够仔细地或精确地管理半导体芯片12和衬底22之间的焊接距离。系统600包括装置,该装置用于控制在步骤520和530中焊接工具36朝向焊接台70的第一阶段移动和第二阶段移动中每一个的速度和位移幅度中的至少一个。焊接工具36朝向焊接台70的位移幅度的控制或管理优选地依赖于通过图10中所示的示例性公式所计算的实际行程值。换句话说,半导体芯片12和衬底22中每一个的厚度或高度的计算使得能够在步骤520和530期间管理焊接工具36朝向焊接台70的位移幅度以及半导体芯片12和衬底22之间的焊接距离。优选地,步骤520和530中焊接工具70朝向焊接台70的位移幅度将半导体芯片12的凸块结构16定位,使其与衬底22的焊接焊盘64相接触。
系统600进一步包括用于在步骤140期间卸载已形成的倒装芯片半导体封装10的装置。如上所述,倒装芯片半导体封装10优选地在卸载台(未示出)冷却。如上所述,本领域技术人员将理解的是,系统可以包括可用于冷却已形成的倒装芯片半导体封装10的可选的冷却装置和机制。例如,系统600可以包括用于实现倒装芯片半导体封装20的强制冷却的流体系统。通过使用本领域技术人员已知的计算机软件和手动或机械装置中的至少一个,便于对已形成的倒装芯片半导体封装10的冷却进行控制。
如上所述,根据本说明书提供的内容,本领域技术人员将理解的是,系统600的装置、部件或元件可以被改变,同时仍有能够实现方法100的步骤110至140的性能。也就是说,用于执行方法100的各步骤以及过程200、300、400和500中的每一个过程的各步骤的系统600的部件、工具或设备可以根据需要通过使用本领域技术人员已知的技术而被改变、确定形状、确定尺寸以及确定结构。
在上述方法中,描述了用于制造本发明提供的倒装芯片半导体封装的示例性方法100和系统600。上面也描述了对示例性方法100和系统600的各种改变和修改,并且这也将被本领域技术人员理解为是在本发明的范围内的。本领域技术人员还将理解的是,本发明不限于上述实施方式的特定形式、布置或结构。由于本公开从而对本领域技术人员来说显而易见的是,在不脱离本发明的范围和精神的情况下,可以对本发明进行多种改变和/或修改。
权利要求书(按照条约第19条的修改)
1.一种用于器件封装的方法,包括:
将半导体器件加热至第一温度,所述半导体器件包括多个凸块结构,所述多个凸块结构的每一个都包括焊料部分,所述第一温度至少是所述多个凸块结构的每一个的所述焊料部分的熔化温度,从而使所述焊料部分达到熔融状态;
将衬底加热至第二温度,所述衬底包括多个接触焊盘,在所述半导体器件和所述衬底分别被加热至所述第一温度和所述第二温度期间,所述半导体器件和所述衬底彼此相距一定距离设置;
在空间上使所述多个凸块结构与所述多个接触焊盘对准;
确定所述半导体器件和所述衬底之间的距离;以及
在加热所述半导体器件和所述衬底之后,使所述半导体器件和所述衬底相对于彼此位移包括所确定的距离的位移距离,从而使所述多个凸块结构的每一个的所述焊料部分均与所述多个接触焊盘中相应的一个接触焊盘相邻接。
2.如权利要求1所述的方法,其中,确定所述半导体器件和所述衬底之间的距离的步骤包括:测量半导体器件厚度和衬底厚度中的至少一个。
3.如权利要求1所述的方法,其中,所述位移距离包括所确定的距离和压缩偏移值。
4.如权利要求3所述的方法,其中,压缩偏移对应于所述半导体器件和所述衬底之间的共面差异。
5.如权利要求1所述的方法,进一步包括:
当所述多个凸块结构的每一个的所述焊料部分均与所述多个接触焊盘中相应的一个接触焊盘相邻接时,终止所述半导体器件和所述衬底相对于彼此的位移。
6.如权利要求5所述的方法,其中,确定所述半导体器件和所述衬底之间的距离便于受控地终止所述半导体器件和所述衬底相对于彼此的位移。
7.如权利要求6所述的方法,其中,所述半导体器件和所述衬底相对于彼此的位移的受控终止预先管理在所述半导体器件和所述衬底中的至少一个上施加压力。
8.如权利要求1所述的方法,其中加热所述衬底的步骤包括:
将所述衬底加热至第二温度,所述第二温度低于所述第一温度。
9.如权利要求8所述的方法,其中所述第二温度低于所述多个凸块结构的每一个的所述焊料部分的所述熔化温度。
10.如权利要求9所述的方法,其中将所述半导体器件加热至所述第一温度的步骤包括:
将所述半导体器件加热至第三温度,所述第三温度低于所述多个凸块结构的每一个的所述焊料部分的所述熔化温度;以及
利用夹持器工具夹持所述半导体器件,所述夹持器工具用于将所述半导体器件加热至所述第一温度。
11.如权利要求10所述的方法,其中将所述半导体器件加热至第三温度的步骤包括:
使所述半导体器件位移越过多个加热元件,所述加热元件被操作,以产生跨过所述加热元件的热量曲线,所述热量曲线被控制,以将所述半导体器件逐渐加热至所述第三温度。
12.如权利要求11所述的方法,其中将所述半导体器件加热至第三温度的步骤进一步包括:
将所述半导体器件设置在板上,所述板能够移动,从而使所述半导体器件位移越过所述多个加热元件。
13.如权利要求12所述的方法,其中将所述半导体器件加热至第三温度的步骤进一步包括:
以旋转方式或线性方式中的一种使所述半导体器件位移,从而以所需的方向将所述半导体器件设置在所述板上;以及
参照由所述板限定的基准确定所述半导体器件的高度。
14.如权利要求9所述的方法,其中将所述衬底加热至第二温度的步骤包括:
将所述衬底设置在第一支架上,所述第一支架用于将所述衬底加热至第四温度,所述第四温度低于所述第二温度;以及
在所述衬底达到所述第四温度后将所述衬底设置在第二支架上,所述第二支架用于将所述衬底加热至所述第二温度。
15.如权利要求14所述的方法,进一步包括:
当所述衬底被设置在所述第一支架上时,将熔剂沉积在所述多个接触焊盘上,所述第二温度低于所述熔剂的活化温度。
16.如权利要求15所述的方法,进一步包括:
当所述衬底被设置在所述第一支架上时,将至少一种底部填充材料沉积在所述多个接触焊盘上,所述第二温度低于所述底部填充材料的固化温度。
17.如权利要求1所述的方法,其中确定所述半导体器件和所述衬底之间的距离的步骤包括:
确定所述半导体器件的高度;
确定所述衬底的高度;以及
在将所述衬底加热至所述第二温度后,将所述半导体器件和所述衬底的所述高度与基准做参照。
18.如权利要求17所述的方法,其中在空间上使所述多个凸块结构与所述多个接触焊盘对准的步骤包括:
限定所述半导体器件上的第一坐标系以及与所述多个凸块结构相交且在设置上相对应的多个基准轴线;
限定所述衬底上的第二坐标系以及与所述衬底的所述多个接触焊盘重叠且在设置上相对应的多个基准顶点;以及
将所述第一坐标系对准所述第二坐标系,以使得所述多个基准轴线中的每一个均与所述多个基准顶点中相应的一个基准顶点基本重叠,从而在空间上使所述多个凸块结构与所述多个接触焊盘对准。
19.一种用于封装器件的系统,包括:
用于将半导体器件和衬底设置为相对于彼此具有一定间隔距离的装置;
至少一个加热器,用于将所述半导体器件加热至第一温度,所述半导体器件包括多个凸块结构,所述多个凸块结构的每一个都包括焊料部分,所述第一温度至少是所述多个凸块结构的每一个的所述焊料部分的熔化温度,从而使所述焊料部分达到熔融状态;
至少一个加热器,用于将所述衬底加热至第二温度,所述衬底包括多个接触焊盘;
至少一个视觉透镜,便于在空间上使所述多个凸块结构与所述多个接触焊盘对准;以及
用于确定位移距离的装置,在将所述半导体器件和所述衬底分别被加热至所述第一温度和所述第二温度之后,所述半导体器件和所述衬底相对于彼此位移所述位移距离,从而使所述多个凸块结构的每一个的所述焊料部分均与所述多个接触焊盘中相应的一个接触焊盘相邻接,
其中,在将所述半导体器件和所述衬底分别加热至所述第一温度和所述第二温度期间,所述半导体器件和所述衬底以相对于彼此具有所述间隔距离设置,并且所述位移距离包括所述间隔距离。
20.如权利要求19所述的系统,用于确定所述半导体器件和所述衬底之间的所述位移距离的装置包括:用于测量半导体器件厚度和衬底厚度中的至少一个的装置。
21.如权利要求19所述的系统,其中,所述位移距离包括所述间隔距离和压缩偏移值。
22.如权利要求21所述的系统,其中,压缩偏移对应于所述半导体器件和所述衬底之间的共面差异
23.如权利要求19所述的系统,进一步包括:用于将所述半导体器件和所述衬底相对于彼此位移的装置。
24.如权利要求23所述的系统,其中,用于将所述半导体器件和所述衬底相对于彼此位移的装置便于使所述多个凸块结构的每一个的所述焊料部分与所述多个接触焊盘中相应的一个接触焊盘相邻接,由此获得半导体器件封装。
25.如权利要求23所述的系统,进一步包括:用于当所述多个凸块结构的每一个的所述焊料部分与所述多个接触焊盘中相应的一个接触焊盘相邻接时,终止所述半导体器件和所述衬底相对于彼此的位移的装置。
26.如权利要求25所述的系统,其中,对所述半导体器件和所述衬底之间的所述位移距离的确定便于使所述半导体器件和所述衬底相对于彼此的位移受控地终止,从而管理在所述半导体器件和所述衬底中的至少一个上施加压力。
27.如权利要求19所述的系统,其中所述第二温度低于所述第一温度。
28.如权利要求27所述的系统,其中,所述第二温度低于所述多个凸块结构的每一个的所述焊料部分的所述熔化温度。
29.如权利要求28所述的系统,进一步包括:
用于夹持所述半导体器件的夹持器工具,所述夹持器工具用于将所述半导体器件加热至所述第一温度。
30.如权利要求29所述的系统,进一步包括:
多个加热元件,所述多个加热元件能够被操作,以产生越过所述多个加热元件的热量曲线,所述热量曲线能够被控制,以将所述半导体器件逐渐加热至第三温度,所述第三温度低于所述多个焊接结构的每一个的所述焊料部分的所述熔化温度。
31.如权利要求30所述的系统,进一步包括:
板,用于越过所述多个加热元件设置所述半导体器件。
32.如权利要求31所述的系统,进一步包括:
用于以旋转方式或线性方式中的一种使所述半导体器件位移的装置,从而以预定方向将所述半导体器件设置在所述板上。
33.如权利要求32所述的系统,进一步包括:
用于确定所述半导体器件的高度的装置;
用于确定所述衬底的高度的装置;以及
用于在将所述衬底加热至所述第二温度后,将所述半导体器件和所述衬底的所述高度与基准做参照的装置。
34.如权利要求18所述的系统,进一步包括:
第一支架,用于将所述衬底加热至第四温度,所述第四温度低于所述第二温度;
第二支架,用于将所述衬底加热至所述第二温度;以及
用于在所述衬底达到所述第四温度后将所述衬底设置在所述第二支架上的装置。
35.如权利要求34所述的系统,进一步包括:
用于当所述衬底被设置在所述第一支架上时,将熔剂沉积在所述多个接触焊盘上的装置,所述第二温度低于所述熔剂的活化温度。
36.如权利要求35所述的系统,其中,所述第四温度低于所述熔剂的所述活化温度。
37.如权利要求35所述的系统,进一步包括:
用于当所述衬底被设置在所述第一支架上时,将底部填充材料沉积在所述多个接触焊盘上的装置,所述第二温度低于所述底部填充材料的固化温度。
38.如权利要求19所述的系统,其中用于在空间上使所述多个凸块结构与所述多个接触焊盘对准的所述至少一个视觉透镜包括:
用于限定所述半导体器件上的第一坐标系以及与所述多个凸块结构相交且在设置上相对应的多个基准轴线的装置;
用于限定所述衬底上的第二坐标系以及与所述衬底的所述多个接触焊盘重叠且在设置上相对应的多个基准顶点的装置;以及
用于将所述第一坐标系与所述第二坐标系对准的装置,使得所述多个基准轴线中的每一个均与所述多个基准顶点中相应的一个基准顶点基本重叠,从而在空间上使所述多个凸块结构与所述多个接触焊盘对准。
Claims (27)
1.一种用于器件封装的方法,包括:
将半导体器件加热至第一温度,所述半导体器件包括多个凸块结构,所述多个凸块结构的每一个都包括焊料部分,所述第一温度至少是所述多个凸块结构的每一个的所述焊料部分的熔化温度,从而使所述焊料部分达到熔融状态;
将衬底加热至第二温度,所述衬底包括多个接触焊盘;以及
在空间上使所述多个凸块结构与所述多个接触焊盘对准,
其中,在将所述半导体器件加热至所述第一温度期间,所述半导体器件被设置为距所述衬底一定距离,在加热所述半导体器件之后,所述半导体器件和所述衬底中的至少一个向另一个位移,从而使所述多个凸块结构的每一个均与所述多个接触焊盘中相应的一个接触焊盘相邻接。
2.如权利要求1所述的方法,其中加热所述衬底的步骤包括:
将所述衬底加热至第二温度,所述第二温度低于所述第一温度。
3.如权利要求2所述的方法,其中所述第二温度低于所述多个凸块结构的每一个的所述焊料部分的所述熔化温度。
4.如权利要求2所述的方法,进一步包括:
使所述半导体器件和所述衬底中的至少一个向另一个位移,从而使所述多个凸块结构的每一个均与所述多个接触焊盘中相应的一个接触焊盘相邻接,由此获得半导体器件封装。
5.如权利要求4所述的方法,其中将所述半导体器件加热至所述第一温度的步骤包括:
将所述半导体器件加热至第三温度,所述第三温度低于所述多个凸块结构的每一个的所述焊料部分的所述熔化温度;以及
利用夹持器工具夹持所述半导体器件,所述夹持器工具用于将所述半导体器件加热至所述第一温度。
6.如权利要求5所述的方法,其中将所述半导体器件加热至第三温度的步骤包括:
使所述半导体器件位移越过多个加热元件,所述加热元件被操作,以产生跨过所述加热元件的热量曲线,所述热量曲线被控制,以将所述半导体器件逐渐加热至所述第三温度。
7.如权利要求6所述的方法,其中将所述半导体器件加热至第三温度的步骤进一步包括:
将所述半导体器件设置在板上,所述板能够移动,从而使所述半导体器件位移越过所述多个加热元件。
8.如权利要求7所述的方法,其中将所述半导体器件加热至第三温度的步骤进一步包括:
以旋转方式或线性方式中的一种使所述半导体器件位移,从而以所需的方向将所述半导体器件设置在所述板上;以及
参照由所述板限定的基准确定所述半导体器件的高度。
9.如权利要求4所述的方法,其中将所述衬底加热至第二温度的步骤包括:
将所述衬底设置在第一支架上,所述第一支架用于将所述衬底加热至第四温度,所述第四温度低于所述第二温度;以及
在所述衬底达到所述第四温度后将所述衬底设置在第二支架上,所述第二支架用于将所述衬底加热至所述第二温度。
10.如权利要求9所述的方法,进一步包括:
当所述衬底被设置在所述第一支架上时,将熔剂沉积在所述多个接触焊盘上,所述第二温度低于所述熔剂的活化温度。
11.如权利要求9所述的方法,进一步包括:
当所述衬底被设置在所述第一支架上时,将至少一种底部填充材料沉积在所述多个接触焊盘上,所述第二温度低于所述底部填充材料的固化温度。
12.如权利要求9所述的方法,进一步包括:
在将所述衬底加热至所述第二温度后,参照由所述第二支架限定的基准确定器件载体的高度。
13.如权利要求4所述的方法,其中在空间上使所述多个凸块结构与所述多个接触焊盘对准的步骤包括:
限定所述半导体器件上的第一坐标系以及与所述多个凸块结构相交且在设置上相对应的多个基准轴线;
限定所述衬底上的第二坐标系以及与所述衬底的所述多个接触焊盘重叠且在设置上相对应的多个基准顶点;以及
将所述第一坐标系对准所述第二坐标系,以使得所述多个基准轴线中的每一个与所述多个基准顶点中相应的一个基准顶点基本重叠,从而在空间上使所述多个凸块结构与所述多个接触焊盘对准。
14.一种用于封装器件的系统,包括:
用于将半导体器件加热至第一温度的装置,所述半导体器件包括多个凸块结构,所述多个凸块结构的每一个都包括焊料部分,所述第一温度至少是所述多个凸块结构的每一个的所述焊料部分的熔化温度,从而使所述焊料部分达到熔融状态;
用于将衬底加热至第二温度的装置,所述衬底包括多个接触焊盘;以及
用于在空间上使所述多个凸块结构与所述多个接触焊盘对准的装置,
其中,在将所述半导体器件加热至所述第一温度期间,将所述半导体器件设置为距所述衬底一定距离,在将所述半导体器件加热至所述第一温度之后,所述半导体器件和载体器件中的至少一个向另一个位移,从而使所述多个凸块结构的每一个均与所述多个接触焊盘中相应的一个接触焊盘相邻接。
15.如权利要求14所述的系统,其中所述第二温度低于所述第一温度。
16.如权利要求15所述的系统,其中,所述第二温度低于所述多个凸块结构的每一个的所述焊料部分的所述熔化温度。
17.如权利要求15所述的系统,进一步包括:
用于使所述半导体器件和器件载体中的至少一个向另一个位移的装置,从而使所述多个凸块结构的每一个均与所述多个接触焊盘中相应的一个接触焊盘相邻接,由此获得半导体器件封装。
18.如权利要求17所述的系统,进一步包括:
用于夹持所述半导体器件的夹持器工具,所述夹持器工具用于将所述半导体器件加热至所述第一温度。
19.如权利要求18所述的系统,进一步包括:
多个加热元件,所述多个加热元件能够被操作,以产生越过所述多个加热元件的热量曲线,所述热量曲线能够被控制,以将所述半导体器件逐渐加热至第三温度,所述第三温度低于所述多个焊接结构的每一个的所述焊料部分的所述熔化温度。
20.如权利要求19所述的系统,进一步包括:
板,用于越过所述多个加热元件设置所述半导体器件。
21.如权利要求20所述的系统,进一步包括:
用于以旋转方式或线性方式中的一种使所述半导体器件位移的装置,从而以预定方向将所述半导体器件设置在所述板上;以及
用于参照由所述板限定的基准确定所述半导体器件的高度的装置。
22.如权利要求17所述的系统,进一步包括:
第一支架,用于将所述衬底加热至第四温度,所述第四温度低于所述第二温度;
第二支架,用于将所述衬底加热至所述第二温度;以及
用于在所述衬底达到所述第四温度后将所述衬底设置在所述第二支架上的装置。
23.如权利要求22所述的系统,进一步包括:
用于当所述衬底被设置在所述第一支架上时,将熔剂沉积在所述多个接触焊盘上的装置,所述第二温度低于所述熔剂的活化温度。
24.如权利要求23所述的系统,其中,所述第四温度低于所述熔剂的所述活化温度。
25.如权利要求22所述的系统,进一步包括:
用于当所述衬底被设置在所述第一支架上时,将底部填充材料沉积在所述多个接触焊盘上的装置,所述第二温度低于所述底部填充材料的固化温度。
26.如权利要求22所述的系统,进一步包括:
用于在将所述器件载体加热至所述第二温度后,参照由所述第二支架限定的基准确定所述器件载体的高度的装置。
27.如权利要求14所述的系统,其中用于在空间上使所述多个凸块结构与所述多个接触焊盘对准的装置包括:
用于限定所述半导体器件上的第一坐标系以及与所述多个凸块结构相交且在设置上相对应的多个基准轴线的装置;
用于限定所述衬底上的第二坐标系以及与所述衬底的所述多个接触焊盘重叠并且在设置上相对应的多个基准顶点的装置;以及
用于将所述第一坐标系与所述第二坐标系对准的装置,使得所述多个基准轴线中的每一个均与所述多个基准顶点中相应的一个基准顶点基本重叠,从而在空间上使所述多个凸块结构与所述多个接触焊盘对准。
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SG200808314-9A SG161134A1 (en) | 2008-11-07 | 2008-11-07 | In-situ melt and reflow process for forming flip-chip interconnections and system thereof |
SG200808314-9 | 2008-11-07 | ||
PCT/SG2009/000413 WO2010053454A1 (en) | 2008-11-07 | 2009-11-09 | In-situ melt and reflow process for forming flip-chip interconnections and system thereof |
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US (1) | US9120169B2 (zh) |
CN (1) | CN102272907B (zh) |
SG (1) | SG161134A1 (zh) |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103579413A (zh) * | 2012-08-01 | 2014-02-12 | 弗莱克斯电子有限责任公司 | 真空回流排空的返工系统 |
CN104325205A (zh) * | 2014-10-24 | 2015-02-04 | 苏州佑瑞检测技术有限公司 | 一种贴片元件的回流焊接方法 |
CN111653494A (zh) * | 2020-06-16 | 2020-09-11 | 中国电子科技集团公司第二十四研究所 | 非接触式加热的倒装焊工艺方法 |
CN112018727A (zh) * | 2019-05-29 | 2020-12-01 | 罗姆股份有限公司 | 半导体装置 |
CN113013307A (zh) * | 2021-03-01 | 2021-06-22 | 东莞市中麒光电技术有限公司 | 一种显示模块故障芯片修复方法 |
CN113140506A (zh) * | 2014-06-30 | 2021-07-20 | 库利克和索夫工业公司 | 热压结合器、及其操作方法、和密脚距倒装芯片组件的互连方法 |
CN113410148A (zh) * | 2021-05-26 | 2021-09-17 | 深圳市时代速信科技有限公司 | 一种芯片封装的焊接方法及芯片封装方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2010362421B2 (en) * | 2010-10-14 | 2015-06-25 | Digital Tags Finland Oy | Method and arrangement for attaching a chip to a printed conductive surface |
US10014272B2 (en) * | 2015-05-11 | 2018-07-03 | Asm Technology Singapore Pte Ltd | Die bonding with liquid phase solder |
TWI557831B (zh) * | 2015-05-15 | 2016-11-11 | 友達光電股份有限公司 | 微組件的傳送方法 |
EP4340006A1 (en) * | 2022-09-15 | 2024-03-20 | Nexperia B.V. | Cooling stage for cooling down a heated carrier |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001298046A (ja) * | 2000-04-14 | 2001-10-26 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004253663A (ja) * | 2003-02-20 | 2004-09-09 | Sony Corp | 半導体装置の製造方法、及び同製造方法に用いるチップボンディング装置 |
CN1759477A (zh) * | 2003-03-25 | 2006-04-12 | 富士通株式会社 | 电子部件安装基板的制造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1226966A (en) * | 1985-09-10 | 1987-09-15 | Gabriel Marcantonio | Integrated circuit chip package |
US8030752B2 (en) * | 2007-12-18 | 2011-10-04 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing semiconductor package and semiconductor plastic package using the same |
-
2008
- 2008-11-07 SG SG200808314-9A patent/SG161134A1/en unknown
-
2009
- 2009-11-09 WO PCT/SG2009/000413 patent/WO2010053454A1/en active Application Filing
- 2009-11-09 TW TW98138007A patent/TW201027644A/zh unknown
- 2009-11-09 CN CN200980153949.2A patent/CN102272907B/zh active Active
- 2009-11-09 US US13/128,141 patent/US9120169B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001298046A (ja) * | 2000-04-14 | 2001-10-26 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004253663A (ja) * | 2003-02-20 | 2004-09-09 | Sony Corp | 半導体装置の製造方法、及び同製造方法に用いるチップボンディング装置 |
CN1759477A (zh) * | 2003-03-25 | 2006-04-12 | 富士通株式会社 | 电子部件安装基板的制造方法 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103579413A (zh) * | 2012-08-01 | 2014-02-12 | 弗莱克斯电子有限责任公司 | 真空回流排空的返工系统 |
CN103579413B (zh) * | 2012-08-01 | 2017-03-01 | 弗莱克斯电子有限责任公司 | 真空回流排空的返工系统 |
CN113140506A (zh) * | 2014-06-30 | 2021-07-20 | 库利克和索夫工业公司 | 热压结合器、及其操作方法、和密脚距倒装芯片组件的互连方法 |
CN104325205A (zh) * | 2014-10-24 | 2015-02-04 | 苏州佑瑞检测技术有限公司 | 一种贴片元件的回流焊接方法 |
CN112018727A (zh) * | 2019-05-29 | 2020-12-01 | 罗姆股份有限公司 | 半导体装置 |
CN112018727B (zh) * | 2019-05-29 | 2022-12-23 | 罗姆股份有限公司 | 半导体装置 |
CN111653494A (zh) * | 2020-06-16 | 2020-09-11 | 中国电子科技集团公司第二十四研究所 | 非接触式加热的倒装焊工艺方法 |
CN111653494B (zh) * | 2020-06-16 | 2021-10-15 | 中国电子科技集团公司第二十四研究所 | 非接触式加热的倒装焊工艺方法 |
CN113013307A (zh) * | 2021-03-01 | 2021-06-22 | 东莞市中麒光电技术有限公司 | 一种显示模块故障芯片修复方法 |
CN113410148A (zh) * | 2021-05-26 | 2021-09-17 | 深圳市时代速信科技有限公司 | 一种芯片封装的焊接方法及芯片封装方法 |
CN113410148B (zh) * | 2021-05-26 | 2022-06-14 | 深圳市时代速信科技有限公司 | 一种芯片封装的焊接方法及芯片封装方法 |
Also Published As
Publication number | Publication date |
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TW201027644A (en) | 2010-07-16 |
US20110287560A1 (en) | 2011-11-24 |
CN102272907B (zh) | 2014-05-14 |
US9120169B2 (en) | 2015-09-01 |
WO2010053454A1 (en) | 2010-05-14 |
SG161134A1 (en) | 2010-05-27 |
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