CN102259820A - Cavity structure, manufacturing method of cavity structure and manufacturing method of pressure-sensitive sensor - Google Patents
Cavity structure, manufacturing method of cavity structure and manufacturing method of pressure-sensitive sensor Download PDFInfo
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- CN102259820A CN102259820A CN2010101865509A CN201010186550A CN102259820A CN 102259820 A CN102259820 A CN 102259820A CN 2010101865509 A CN2010101865509 A CN 2010101865509A CN 201010186550 A CN201010186550 A CN 201010186550A CN 102259820 A CN102259820 A CN 102259820A
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Abstract
The invention disclose a manufacturing method of a pressure-sensitive sensor. The manufacturing method comprises the following steps of: (1) etching a silicon wafer to form a cavity; (2) forming a sacrificial layer on the surface of the silicon wafer; (3) flattening the surface of the sacrificial layer; (4) etching the sacrificial layer into the silicon wafer to form a supporting column through hole; (5) depositing a pressure-sensitive sensing film on the sacrificial layer; (6) etching the pressure-sensitive sensing film to form a pressure-sensitive sensing film pattern; (7) removing the sacrificial layer by wet etching; and (8) depositing a protection layer on the surface of the silicon wafer to seal the cavity. The manufacturing method provided by the invention has good compatibility with the traditional process for processing a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) on a silicon surface. The invention also discloses a method for forming a closed cavity in a silicon surface.
Description
Technical field
The present invention relates to a kind of preparation method of MEMS voltage sensitive sensor.The invention still further relates to the method that forms cavity in a kind of silicon chip.
Background technology
Pressure sensor is a kind of device that pressure is converted to the signal of telecommunication.Usually, pressure sensor itself be embedded with resistance the micromechanics film, pressure drag is used for detected pressures.
Silicon thin film has favorable mechanical, and micromachining technology (MEMS) integrates silicon thin film and pressure drag stressometer or strain gauge.Pressure drag stressometer or strain gauge are injected simply or are diffused in the film upper surface.These pressure drags are placed on position suitable on the film, and link together with Wheatstone bridge, like this, these pressure drags just can be exported the enough strong signal of telecommunication.In addition, film also can be used as an electrode of capacitor.The stress of film and amount of deflection all depend on the differential pressure that is applied thereto, just the pressure of the pressure of film upper surface and film lower surface.If the lower surface of film is the part of certain vacuum chamber, Here it is so absolute pressure transducer.
Body micromachined (bulk micromachining) and surface micromachined (surfacemicromachining) are to make two kinds of main method of film.In the body micro-machining, optionally remove the body silicon materials on the silicon chip, until staying one deck monocrystalline silicon thin film, main use corrosion is controlled film thickness from stopping technology.Surface micro be earlier with thin-film deposition on sacrifice layer, and then selectivity wet etching sacrifice layer forms film at last.
The body micro-machining from stopping technology, forms pressure port from the silicon chip back side by the Applied Electrochemistry corrosion, uses epitaxial loayer to form micro mechanical structure.Because of the body micromachined is used electrochemical etching method, relatively poor to film thickness control, and itself and CMOS processing compatibility are poor.And the surface micromachined technology can accurately be controlled film thickness by the deposit of sacrifice layer, uses positive processing to satisfy and makes cavity and discharge micro mechanical structure, and is fine with traditional silicon Surface Machining CMOS processing compatibility.
Summary of the invention
The technical problem to be solved in the present invention provides the cavity structure in a kind of MEMS system, and this structure is positioned at silicon chip surface.
For solving the problems of the technologies described above, the cavity structure that is formed on silicon chip surface of the present invention comprises cavity, a plurality of support column, topmost thin film and protective layer; Cavity, etching is formed at silicon chip surface; The support column through hole is arranged on the cavity silicon chip all around; Topmost thin film is supported by support column, is positioned at the cavity top; Protective layer is positioned on topmost thin film and the silicon chip, the sealing structure that will be made of cavity, support column and topmost thin film.
The present invention also provides a kind of method for preparing cavity structure, comprises the steps:
1) the etching silicon chip forms cavity;
2) at described silicon chip surface deposit sacrifice layer, described sacrifice layer is filled described cavity;
3) the described sacrificial layer surface of planarization, and the sacrifice layer on the described silicon chip surface is a predetermined thickness after the planarization;
4) the described sacrifice layer of etching, desired depth to the silicon chip surface forms the support column through hole, and described support column through hole is to be arranged on all around through hole in the sacrifice layer of cavity more than two;
5) deposit topmost thin film on described sacrifice layer is filled described support column through hole in the time of deposit;
6) the described topmost thin film of etching forms the topmost thin film pattern, and described etching stopping is on described sacrifice layer;
7) wet etching is removed described sacrifice layer;
8) at described silicon chip surface deposit protective layer, to seal described cavity.
The present invention also provides a kind of preparation method of voltage sensitive sensor, comprises the steps:
1) the etching silicon chip forms cavity;
2) deposit forms sacrifice layer on described silicon chip, and described sacrifice layer is filled described cavity;
3) the described sacrificial layer surface of planarization, and the sacrifice layer on the described silicon chip surface is a predetermined thickness after the planarization;
4) the described sacrifice layer of etching in the desired depth, forms the support column through hole to the silicon chip surface, and described support column through hole is to be arranged on all around through hole in the sacrifice layer of cavity more than two;
5) deposit pressure-responsive film on described sacrifice layer is filled described support column through hole in the time of deposit;
6) the described pressure-responsive film of etching forms the pressure-responsive Thinfilm pattern, and described etching stopping is on described sacrifice layer;
7) wet etching is removed described sacrifice layer;
8) deposit protective layer on described silicon chip is to seal described cavity.
The preparation method of pressure-responsive device of the present invention is for the surface etch at silicon chip goes out the extendable room of a cavity (cavity) as sense film; After forming, cavity fills sacrifice layer, the difference of height (Step-height) between the figure that sacrifice layer depositing technics wherein can keep forming because of the cavity etching to cavity; The through hole that encloses around cavity in the sacrifice layer etching on every side that is positioned at cavity after planarization is used for filling the fixedly support column through hole of sense film; Carry out pressure-responsive film support post through hole afterwards and fill and the sense film deposit, etch the sense film shape then, clean all sacrifice layer etchings by the method for wet etching again, last deposit layer protective layer seals the pressure-responsive device.Than the body micro-machining, our bright method and traditional silicon Surface Machining CMOS processing compatibility are better.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and the specific embodiment:
Fig. 1 is a preparation method schematic flow sheet of the present invention;
Fig. 2 is for implementing the cross section structure schematic diagram behind the deposit sacrifice layer in the method for the present invention;
Fig. 3 is for implementing the cross section structure schematic diagram behind the planarization sacrifice layer in the method for the present invention;
Fig. 4 is for implementing the cross section structure schematic diagram behind the deposit pressure-responsive film in the method for the present invention;
Fig. 5 is for implementing the cross section structure schematic diagram behind the removal sacrifice layer in the method for the present invention;
Fig. 6 is for implementing the cross section structure schematic diagram behind the deposit protective layer in the method for the present invention;
Fig. 7 is the floor map of cavity structure cavity of the present invention and support column through hole.
The specific embodiment
The preparation method (see figure 1) of MEMS of the present invention (MEMS) voltage sensitive sensor, a concrete implementation step is:
1) earlier at silicon chip 10 surface etch one cavity 11.Usually this cavity is the square or rectangular with certain depth.The position of cavity can be earlier photoetching process by routine define out.
2) deposit sacrifice layer 13 (see figure 2)s on silicon chip then, the above-mentioned cavity of this sacrificial layer material complete filling.Sacrificial layer material can be pure silica, also can be boron doped silica, phosphorus doped silica and mixes in the fluorodioxy silicon any.The deposit of sacrifice layer can be undertaken by PECVD (plasma enhanced CVD method), APCVD (normal pressure chemical vapour deposition) or LPCVD (low-pressure chemical vapor phase deposition method) technology.
3) afterwards the sacrifice layer 13 of institute's deposit is carried out the planarization (see figure 3).The main CMP grinding technics that adopts carries out planarization in the reality.The sacrifice layer that requires after the planarization to be positioned on the silicon chip surface keeps a preset thickness, and this predetermined thickness can be the 100-30000 dust as this thickness in the instantiation according to concrete process design optimization.
4) etching sacrificial layer forms support column through hole 12.Concrete technology is for defining the position of support column through hole earlier on sacrifice layer with photoetching process; Then the described sacrifice layer of etching to the following certain depth of silicon chip (can be 50 to 20000 dusts), forms the support column through hole.Support column through hole 12 is the through hole (see figure 7)s in a plurality of sacrifice layers 13 that are arranged on around the cavity 11, and its main application is that sacrifice layer is removed the back and supported the pressure-responsive film that is positioned at the cavity top.The number of this support column through hole and this support column through hole to the degree of depth of silicon chip should be designed to guarantee can support the pressure-responsive film that is positioned at above the cavity after sacrifice layer is removed process and removed.
5) deposit pressure-responsive film 14 on sacrifice layer is filled above-mentioned support column through hole (see figure 4) in deposit.The pressure-responsive film is a polysilicon film in one embodiment, can be pure silicon polycrystal film, phosphorous doped polysilicon, boron-doping polysilicon or mixes the fluorine polysilicon.The thickness of pressure-responsive film can be between the 100-50000 dust, and concrete numerical value can be determined by technological design.The pressure-responsive film is preferably selected the material that has the wet etching high selectivity with sacrificial layer material for use, and is unaffected to guarantee in sacrifice layer removal process.Support column through hole after the filling is a support column after removing sacrifice layer
6) pressure-responsive film etching forms the pressure-responsive film pattern, and etching stopping is on the sacrifice layer of lower floor.The figure of pressure-responsive film is defined by photoetching process, and etching stopping is about to unwanted pressure-responsive film and removes fully on sacrifice layer.
7) wet etching is removed sacrifice layer, forms the pressure-responsive device (see figure 5) that is made of cavity 11, a plurality of support column 15 and pressure-responsive film 14.
8) at last at silicon chip surface deposit protective layer 16, to seal above-mentioned pressure-responsive device (see figure 6).Protective layer material can be: silicon nitride, and silica or silicon oxynitride etc., its senser element that is used for cavity, support column and pressure-responsive film are constituted seals.
Cavity structure of the present invention is formed on silicon chip surface, has structure as shown in Figure 6.This cavity structure comprises that etching is formed at the cavity of silicon chip surface; Be arranged at a plurality of support columns on the cavity silicon chip all around; Support by described support column, be positioned at the topmost thin film of cavity top; And protective layer, be positioned on topmost thin film and the silicon chip sealing structure that will constitute by cavity, support column and topmost thin film.
The preparation method of cavity structure of the present invention is applicable to that all are based on the device that has similar cavity structure in the MEMS of silicon substrate with voltage sensitive sensor.The method that forms cavity structure in silicon chip of the present invention comprises the steps:
1) the etching silicon chip forms cavity;
2) form sacrifice layer, sacrifice layer cavity filling at silicon chip surface;
3) planarization sacrificial layer surface, and the sacrifice layer on the silicon chip surface is a predetermined thickness after the planarization;
4) etching sacrificial layer desired depth to the silicon chip surface forms the support column through hole, and the support column through hole is to be arranged on all around through hole in the sacrifice layer of cavity more than two;
5) deposit topmost thin film on sacrifice layer, topmost thin film is filled the support column through hole in the time of deposit;
6) etching topmost thin film forms the topmost thin film pattern, and etching stopping is on sacrifice layer;
7) wet etching is removed sacrifice layer, forms the structure that is made of cavity, support column and topmost thin film;
8) at silicon chip surface deposit protective layer, make cavity airtight.
Claims (6)
1. cavity structure that is formed on silicon chip surface is characterized in that:
Described cavity structure comprises cavity, a plurality of support column, topmost thin film and protective layer;
Described cavity, etching is formed at silicon chip surface;
Described support column is arranged on the described cavity silicon chip all around;
Described topmost thin film is supported by described support column, is positioned at described cavity top;
Described protective layer is positioned on described topmost thin film and the silicon chip, the sealing structure that will be formed by described cavity, support column through hole and topmost thin film.
2. one kind prepares the method for cavity structure according to claim 1, it is characterized in that, comprises the steps:
1) the etching silicon chip forms cavity;
2) at described silicon chip surface deposit sacrifice layer, described sacrifice layer is filled described cavity;
3) the described sacrificial layer surface of planarization, and the sacrifice layer on the described silicon chip surface is a predetermined thickness after the planarization;
4) the described sacrifice layer of etching, desired depth to the silicon chip surface forms the support column through hole, and described support column through hole is to be arranged on all around through hole in the sacrifice layer of described cavity more than two;
5) deposit topmost thin film on described sacrifice layer is filled described support column through hole and is formed support column in the time of deposit;
6) the described topmost thin film of etching forms the topmost thin film pattern, and described etching stopping is on described sacrifice layer;
7) wet etching is removed described sacrifice layer;
8) deposit protective layer on described silicon chip is described cavity sealing.
3. the preparation method of a voltage sensitive sensor is characterized in that, comprises the steps:
1) the etching silicon chip forms cavity;
2) deposit forms sacrifice layer on described silicon chip, and described sacrifice layer is filled described cavity;
3) the described sacrificial layer surface of planarization, and the sacrifice layer on the described silicon chip surface is a predetermined thickness after the planarization;
4) the described sacrifice layer of etching in the desired depth, forms the support column through hole to the silicon chip surface, and described support column through hole is to be arranged on all around through hole in the sacrifice layer of cavity more than two;
5) deposit pressure-responsive film on described sacrifice layer is filled described support column through hole in the time of deposit;
6) the described pressure-responsive film of etching forms the pressure-responsive Thinfilm pattern, and described etching stopping is on described sacrifice layer;
7) wet etching is removed described sacrifice layer;
8) deposit protective layer on described silicon chip is to seal described cavity.
4. preparation method as claimed in claim 3 is characterized in that: the material of described sacrifice layer is pure silicon dioxide, boron doped silica, phosphorus doped silica or mixes fluorodioxy silicon; The depositing technics of described sacrifice layer is PECVD, APCVD or LPCVD.
5. preparation method as claimed in claim 3 is characterized in that: the thickness of sacrifice layer is 100～30000 dusts after the described step 3 planarization.
6. preparation method as claimed in claim 3 is characterized in that: described pressure-responsive film is pure silicon polycrystal film, phosphorous doped polysilicon, boron-doping polysilicon or mixes the fluorine polysilicon.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103618044A (en) * | 2013-11-29 | 2014-03-05 | 上海集成电路研发中心有限公司 | Method for manufacturing piezoelectric cantilever beam sensor structure |
| CN105092117A (en) * | 2015-08-19 | 2015-11-25 | 东南大学 | Piezoresistive pressure sensor and preparation method thereof |
| CN107339228A (en) * | 2017-06-26 | 2017-11-10 | 歌尔股份有限公司 | Miniflow pumping configuration, system and preparation method |
| CN115332061A (en) * | 2022-10-13 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | Manufacturing method of grid structure |
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| JPH0563211A (en) * | 1991-08-30 | 1993-03-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH06221945A (en) * | 1993-01-21 | 1994-08-12 | Fujikura Ltd | Semiconductor pressure sensor and manufacture thereof |
| US20030129374A1 (en) * | 2002-01-07 | 2003-07-10 | Chuang-Chia Lin | Self-aligned micro hinges |
| CN1900669A (en) * | 2005-07-21 | 2007-01-24 | 中国科学院微电子研究所 | Method for producing heat shear stress sensor device based on new sacrifice layer process |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0563211A (en) * | 1991-08-30 | 1993-03-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH06221945A (en) * | 1993-01-21 | 1994-08-12 | Fujikura Ltd | Semiconductor pressure sensor and manufacture thereof |
| US20030129374A1 (en) * | 2002-01-07 | 2003-07-10 | Chuang-Chia Lin | Self-aligned micro hinges |
| CN1900669A (en) * | 2005-07-21 | 2007-01-24 | 中国科学院微电子研究所 | Method for producing heat shear stress sensor device based on new sacrifice layer process |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103618044A (en) * | 2013-11-29 | 2014-03-05 | 上海集成电路研发中心有限公司 | Method for manufacturing piezoelectric cantilever beam sensor structure |
| CN103618044B (en) * | 2013-11-29 | 2018-12-18 | 上海集成电路研发中心有限公司 | Piezoelectric cantilever sensor structure making process |
| CN105092117A (en) * | 2015-08-19 | 2015-11-25 | 东南大学 | Piezoresistive pressure sensor and preparation method thereof |
| CN105092117B (en) * | 2015-08-19 | 2017-06-09 | 东南大学 | A kind of piezoresistive pressure sensor and preparation method thereof |
| CN107339228A (en) * | 2017-06-26 | 2017-11-10 | 歌尔股份有限公司 | Miniflow pumping configuration, system and preparation method |
| CN115332061A (en) * | 2022-10-13 | 2022-11-11 | 合肥晶合集成电路股份有限公司 | Manufacturing method of grid structure |
| CN115332061B (en) * | 2022-10-13 | 2022-12-16 | 合肥晶合集成电路股份有限公司 | Manufacturing method of grid structure |
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| CN102259820B (en) | 2013-12-18 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |