CN102259822B - Method for preparing pressure-sensitive sensor and method for forming cavity structure on silicon wafer - Google Patents
Method for preparing pressure-sensitive sensor and method for forming cavity structure on silicon wafer Download PDFInfo
- Publication number
- CN102259822B CN102259822B CN201010186541.XA CN201010186541A CN102259822B CN 102259822 B CN102259822 B CN 102259822B CN 201010186541 A CN201010186541 A CN 201010186541A CN 102259822 B CN102259822 B CN 102259822B
- Authority
- CN
- China
- Prior art keywords
- sacrifice layer
- hole
- support column
- cavity
- silicon chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Pressure Sensors (AREA)
- Measuring Fluid Pressure (AREA)
- Micromachines (AREA)
Abstract
The invention discloses a method for preparing a pressure-sensitive sensor. The method comprises the following steps of: (1), etching a silicon wafer to form a cavity; (2), forming a sacrificial layer on the surface of the silicon wafer; (3), carrying out planarization treatment on the surface of the sacrificial layer; (4) forming a support column through hole and a sensing film filling groove on the sacrificial layer by using a dual-damascene process; (5), depositing a pressure-sensitive sensing film on the sacrificial layer; (6), grinding the pressure-sensitive sensing film to the sacrificial layer by using CMP (Chemical Mechanical Planarization); (7), corroding and removing the sacrificial layer by using a wet method; and (8), depositing a protective layer on the surface of the silicon wafer so as to seal the cavity. The compatibility between the preparation method disclosed by the invention and the traditional silicon surface processing CMOS (Complementary Metal Oxide Semiconductor) process is better. The invention further discloses a method for forming a closed cavity in the silicon wafer.
Description
Technical field
The present invention relates to a kind of preparation method of voltage sensitive sensor, particularly a kind of preparation method of MEMS voltage sensitive sensor.The invention still further relates to a kind of method forming closed cavity on silicon chip.
Background technology
Pressure sensor is a kind of device pressure being converted to the signal of telecommunication.Usually, pressure sensor itself be embedded with resistance micromachined membrane, pressure drag is used for detected pressures.
Silicon thin film has good mechanicalness, and silicon thin film and pressure drag stressometer or strain gauge integrate by micromachining technology (MEMS).Pressure drag stressometer or strain gauge are injected simply or are diffused in film upper surface.These pressure drags are placed on position suitable on film, and link together with Wheatstone bridge, like this, these pressure drags just can export the enough strong signal of telecommunication.In addition, film also can as of a capacitor electrode.The stress of film and amount of deflection all depend on the differential pressure be applied thereto, namely the pressure of film upper surface and the pressure of film lower surface.If the lower surface of film is a part for certain vacuum chamber, so Here it is absolute pressure transducer.
Bulk silicon micromachining (bulk micromachining) and surface micromachined (surfacemicromachining) are the two kinds of main method manufacturing film.In bulk silicon micromachining method, optionally remove the body silicon materials on silicon chip, until leave one deck monocrystalline silicon thin film, the main etch-stop technology that uses controls film thickness.Surface micro be first by thin-film deposition on sacrifice layer, and then selective wet etching sacrifice layer, finally forms film.
Bulk silicon micromachining method, by Applied Electrochemistry etch-stop technology, from silicon chip back side mineralization pressure mouth, uses epitaxial layer to form micro mechanical structure.Because bulk silicon micromachining uses electrochemical etching method, poor to plastics thickness control, and itself and CMOS technology compatibility are poor.And surface micromachined technology, accurately can control film thickness by the deposit of sacrifice layer, use front processing to meet and manufacture cavity and release micro mechanical structure, very well compatible with traditional silicon Surface Machining CMOS technology.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of preparation method of voltage sensitive sensor, and it is adopt to prepare based on the surface micromachined technology of silicon chip.
For solving the problems of the technologies described above, the preparation method of voltage sensitive sensor of the present invention, comprises the steps:
1) etching silicon wafer forms cavity;
2) form sacrifice layer in described silicon chip surface deposit, described sacrifice layer fills described cavity;
3) sacrificial layer surface described in planarization, and the sacrifice layer on planarized rear described silicon chip surface is a predetermined thickness;
4) adopt dual damascene process in described sacrifice layer, prepare support column through hole and sense film filling slot, described support column through hole is that two or more is arranged on the through hole of cavity all around in sacrifice layer;
5) deposit pressure-responsive film on described sacrifice layer, to fill described support column through hole and described sense film filling slot;
6) CMP is adopted to grind described pressure-responsive film to described sacrifice layer;
7) wet etching removes described sacrifice layer;
8) at described silicon chip surface deposit protective layer, to seal described cavity.
Present invention also offers a kind of method forming closed cavity in silicon chip, comprise the steps:
1) etching silicon wafer forms cavity;
2) sacrifice layer is formed at silicon chip surface, sacrifice layer cavity filling;
3) sacrificial layer surface described in planarization, and the sacrifice layer on planarized rear silicon chip surface is a predetermined thickness;
4) adopt dual damascene process on sacrifice layer, prepare support column through hole and topmost thin film filling slot, described support column through hole is that two or more is arranged on the through hole of cavity all around in sacrifice layer;
5) deposit topmost thin film on sacrifice layer, to fill support column through hole and topmost thin film filling slot;
6) adopt CMP grinding topmost thin film to described sacrifice layer;
7) wet etching removes sacrifice layer;
8) at silicon chip surface deposit protective layer, cavities seals.
Voltage sensitive sensor preparation method in MEMS of the present invention, goes out the extendable room of a cavity (cavity) as sense film in the surface etch of silicon chip; Cavity formation rear to cavity fill sacrifice layer, sacrifice layer depositing technics wherein can keep because of cavity etching formed figure between difference of height (Step-height); Dual damascene process is adopted to prepare support column through hole and sense film filling slot; Then deposit pressure-responsive film on silicon chip, then carries out CMP and is ground to sacrifice layer, more all sacrifice layers is etched clean by the method for wet etching, and last deposit layer protective layer seals pressure-sensitive sensing element.Compared to bulk silicon micromachining method, the bright method of we and traditional silicon Surface Machining CMOS technology compatibility are better.Adopt dual damascene process to prepare support column through hole and sense film filling slot in the present invention simultaneously, be specially adapted to carry out in the technological process of sense film patterning with etching technics.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and detailed description of the invention, the present invention is further detailed explanation:
Fig. 1 is preparation method schematic flow sheet of the present invention;
Fig. 2 implements the cross section structure schematic diagram in method of the present invention after deposit sacrifice layer;
Fig. 3 implements the cross section structure schematic diagram in method of the present invention after cmp planarization sacrifice layer;
Fig. 4 implements the cross section structure schematic diagram after forming support column through hole and pressure-responsive film filling slot in method of the present invention;
Fig. 5 implements the cross section structure schematic diagram in method of the present invention after deposit pressure-responsive film;
Fig. 6 implements the cross section structure schematic diagram in method of the present invention after CMP grinding pressure-responsive film;
Fig. 7 implements the cross section structure schematic diagram after removing sacrifice layer in method of the present invention;
Fig. 8 implements the cross section structure schematic diagram in method of the present invention after deposit protective layer;
Fig. 9 is the schematic diagram of support column through hole in one embodiment of the invention.
Detailed description of the invention
The preparation method (see Fig. 1) of MEMS voltage sensitive sensor of the present invention, a concrete implementation step is:
1) first at silicon chip 10 surface etch one cavity.Usually this cavity can be the square or rectangular with certain depth.The position of cavity first defines out by the photoetching process of routine, then etches, and etching can adopt conventional technique.
2) then deposit sacrifice layer 13 (see Fig. 2) on silicon chip, this sacrificial layer material fills above-mentioned cavity completely.Sacrificial layer material can be pure silica, also can be boron doped silica, phosphorus doped silica and mix in fluorodioxy SiClx any one.The deposit of sacrifice layer is undertaken by PECVD (plasma enhanced CVD method), APCVD (Films Prepared by APCVD method) or LPCVD (low-pressure chemical vapor phase deposition method) technique.The thickness (thickness on silicon chip surface) of sacrifice layer can be between 100-50000 dust.
3) after, planarization (see Fig. 3) is carried out to the sacrifice layer of institute's deposit, main employing CMP grinding technics.The planarized rear requirement sacrifice layer be positioned on silicon chip surface keeps a predetermined thickness, and this predetermined thickness can be selected by concrete technology, as in an instantiation, this thickness can be 100-30000 dust.
4) adopt dual damascene process in sacrifice layer, prepare support column through hole 12 and sense film filling slot 141 (see Fig. 4).Dual damascene process is the technique of existing maturation, is mainly used in the graphical of the material that can not etch.
In concrete enforcement, dual damascene process can divide first via process and rear via process.The idiographic flow of a first via process is: the position first defining through hole by photoetching process; Then etching sacrificial layer is to next desired depth of silicon chip surface, forms through hole; Deposit antireflection material is with filling vias; Photoetching process is then adopted to define sense film filling slot; Then etching sacrificial layer forms sense film filling slot; Finally remove remaining antireflection material, form support column through hole and sense film filling slot.
After one, the idiographic flow of via process is: first barrier layer (can be silicon nitride) on sacrifice layer; Lithographic definition goes out the position of support column through hole, and etching barrier layer is to sacrifice layer afterwards, forms barrier layer opening; Deposit second layer sacrifice layer over the barrier layer; Adopt photoetching process to define the position of sense film filling slot, then etching of second layer sacrifice layer, form sense film filling slot; Under the protection on barrier layer, etching sacrificial layer, forms support column through hole.Wherein the etching of support column through hole should stop at certain thickness (can be 50 to 20000 dusts) under silicon chip surface.Support column through hole 12 is the through hole in multiple sacrifice layer being arranged on cavity 11 surrounding, and as shown in Figure 9, its main application is the pressure-responsive film that sacrifice layer removes on rear support cavity.The number of this support column through hole should be designed to the degree of depth of this support column via etch to silicon chip: can ensure the pressure-responsive film above supporting after sacrifice layer removes process and sacrifice layer is removed.
5) deposit pressure-responsive film 14 on sacrifice layer 13, to fill above-mentioned support column through hole 12 and sense film filling slot 141 (see Fig. 5).Pressure-responsive film is polysilicon film in one embodiment, can be pure silicon polycrystal film, phosphorous doped polysilicon, B-doped Polycrystalline Silicon or mixes fluorine polysilicon.The thickness of pressure-responsive film can be between 100-50000 dust, and concrete numerical value can be determined by technological design.Pressure-responsive film preferably selects the material with sacrificial layer material with wet etching high selectivity, unaffected to ensure in sacrifice layer removal process.
6) adopt CMP grinding pressure-responsive film 14 to sacrifice layer (see Fig. 6), remove by the pressure-responsive film on sacrifice layer, form pressure-responsive film pattern.
7) wet etching removes sacrifice layer 13, forms the pressure-sensitive sensing element (see Fig. 7) be made up of cavity 11, support column 15 and pressure-responsive film 14.As in rear via process, remove barrier layer simultaneously.
8) last at silicon chip surface deposit protective layer, to seal above-mentioned pressure-sensitive sensing element.Protective layer material can be: silicon nitride, silica or silicon oxynitride etc.
Preparation method of the present invention, be applicable to all devices based on having similar structures in the MEMS of silicon substrate with voltage sensitive sensor, the structure particularly preparing closed cavity on silicon chip (comprises cavity, support column through hole and sense film), in silicon chip, form the chamber with a vacuum.The method forming closed cavity in silicon chip of the present invention, comprises the steps:
1) etching silicon wafer forms cavity;
2) sacrifice layer is formed at silicon chip surface, sacrifice layer cavity filling;
3) planarization sacrificial layer surface, and the sacrifice layer on planarized rear silicon chip surface is a predetermined thickness;
4) adopt dual damascene process on sacrifice layer, manufacture support column through hole and topmost thin film filling slot, support column through hole is that two or more is arranged on the through hole of cavity all around in sacrifice layer;
5) deposit topmost thin film on sacrifice layer, to fill support column through hole and topmost thin film filling slot;
6) adopt CMP grinding topmost thin film to sacrifice layer;
7) wet etching removes sacrifice layer;
8) at silicon chip surface deposit protective layer, make the cavity in silicon chip airtight.
Claims (7)
1. a preparation method for voltage sensitive sensor, is characterized in that, comprises the steps:
1) etching silicon wafer forms cavity;
2) form sacrifice layer in described silicon chip surface deposit, described sacrifice layer fills described cavity;
3) sacrificial layer surface described in planarization, and the sacrifice layer on planarized rear described silicon chip surface is a predetermined thickness;
4) adopt dual damascene process in described sacrifice layer, prepare support column through hole and sense film filling slot, described support column through hole is that two or more is arranged on the through hole of cavity all around in sacrifice layer;
Described support column through hole formed to next desired depth of silicon chip surface by etching described sacrifice layer;
5) deposit pressure-responsive film on described sacrifice layer, fills described support column through hole and described sense film filling slot;
6) CMP is adopted to grind described pressure-responsive film to described sacrifice layer;
7) wet etching removes described sacrifice layer;
8) at described silicon chip surface deposit protective layer, to seal described cavity.
2. preparation method as claimed in claim 1, it is characterized in that: the dual damascene process in described step 4 adopts first via process, namely first prepare support column through hole, prepare sense film filling slot afterwards, prepared support column through hole gos deep into below silicon chip surface 50 to 20000 dust.
3. preparation method as claimed in claim 1, it is characterized in that: via process after the dual damascene process in described step 4 adopts, namely first prepare sense film filling slot, prepare support column through hole afterwards, prepared support column through hole gos deep into below silicon chip surface 50 to 20000 dust.
4. preparation method as claimed any one in claims 1 to 3, is characterized in that: the material of described sacrifice layer is pure silicon dioxide, boron doped silica, phosphorus doped silica or mixes fluorodioxy SiClx; The depositing technics of described sacrifice layer is PECVD, APCVD or LPCVD.
5. preparation method as claimed any one in claims 1 to 3, it is characterized in that: after described step 3 planarization, the thickness of described sacrifice layer is 100 ~ 30000 dusts.
6. as claimed any one in claims 1 to 3 preparation method, is characterized in that: described pressure-responsive film is pure silicon polycrystal film, phosphorous doped polysilicon film, B-doped Polycrystalline Silicon film or mix fluorine polysilicon membrane.
7. in silicon chip, form a method for cavity structure, it is characterized in that, comprise the steps:
1) etching silicon wafer forms cavity;
2) form sacrifice layer at described silicon chip surface, described sacrifice layer fills described cavity;
3) sacrificial layer surface described in planarization, and the sacrifice layer on planarized rear described silicon chip surface is a predetermined thickness;
4) adopt dual damascene process in described sacrifice layer, manufacture support column through hole and topmost thin film filling slot, described support column through hole is that two or more is arranged on the through hole of cavity all around in sacrifice layer;
5) deposit topmost thin film on described sacrifice layer, to fill described support column through hole and described topmost thin film filling slot;
6) CMP is adopted to grind described topmost thin film to described sacrifice layer;
7) wet etching removes described sacrifice layer;
8) at described silicon chip surface deposit protective layer, described cavities seals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010186541.XA CN102259822B (en) | 2010-05-27 | 2010-05-27 | Method for preparing pressure-sensitive sensor and method for forming cavity structure on silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010186541.XA CN102259822B (en) | 2010-05-27 | 2010-05-27 | Method for preparing pressure-sensitive sensor and method for forming cavity structure on silicon wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102259822A CN102259822A (en) | 2011-11-30 |
| CN102259822B true CN102259822B (en) | 2015-02-04 |
Family
ID=45006697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010186541.XA Active CN102259822B (en) | 2010-05-27 | 2010-05-27 | Method for preparing pressure-sensitive sensor and method for forming cavity structure on silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102259822B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003067662A1 (en) * | 2002-02-07 | 2003-08-14 | Superconductor Technologies, Inc. | Stiction alleviation using passivation layer patterning |
| CN1884040A (en) * | 2005-06-23 | 2006-12-27 | 中国科学院微电子研究所 | Method for making and releasing sacrificial layer by using salient point based on silicon substrate |
| CN1900669A (en) * | 2005-07-21 | 2007-01-24 | 中国科学院微电子研究所 | Method for producing heat shear stress sensor device based on new sacrifice layer process |
| CN101195471A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | MEMS device and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563211A (en) * | 1991-08-30 | 1993-03-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JP2006105639A (en) * | 2004-10-01 | 2006-04-20 | Hitachi Ltd | Pressure sensor system |
| WO2009079780A1 (en) * | 2007-12-21 | 2009-07-02 | The Royal Institution For The Advancement Of Learning/Mcgill University | Low temperature ceramic microelectromechanical structures |
| CN102256893B (en) * | 2008-11-07 | 2015-04-29 | 卡文迪什动力有限公司 | Method of using a plurality of smaller mems devices to replace a larger mems device |
-
2010
- 2010-05-27 CN CN201010186541.XA patent/CN102259822B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003067662A1 (en) * | 2002-02-07 | 2003-08-14 | Superconductor Technologies, Inc. | Stiction alleviation using passivation layer patterning |
| CN1884040A (en) * | 2005-06-23 | 2006-12-27 | 中国科学院微电子研究所 | Method for making and releasing sacrificial layer by using salient point based on silicon substrate |
| CN1900669A (en) * | 2005-07-21 | 2007-01-24 | 中国科学院微电子研究所 | Method for producing heat shear stress sensor device based on new sacrifice layer process |
| CN101195471A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | MEMS device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102259822A (en) | 2011-11-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1012552B1 (en) | 5 micron high acute cavity with channel by oxidizing fusion bonding of silicon substrates and stop etching | |
| US10048148B2 (en) | Process for manufacturing a MEMS pressure sensor, and corresponding MEMS pressure sensor | |
| CN101832831B (en) | Piezoresistive sensor chip and manufacture method thereof | |
| JP5891571B2 (en) | MEMS pressure sensor device and manufacturing method thereof | |
| US6445053B1 (en) | Micro-machined absolute pressure sensor | |
| EP3174825B1 (en) | Suspended membrane for capacitive pressure sensor | |
| US7972888B1 (en) | Methods for manufacturing MEMS sensor and thin film and cantilever beam thereof with epitaxial growth process | |
| US8709848B2 (en) | Method for etched cavity devices | |
| EP2499368B1 (en) | Method for producing at least one deformable membrane micropump and deformable membrane micropump | |
| US8519494B2 (en) | Method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate | |
| EP3052901B1 (en) | Inertial and pressure sensors on single chip | |
| CN106018879B (en) | A kind of MEMS acceleration transducer and manufacturing method | |
| CN103964373A (en) | Microelectromechanical system devices having crack resistant membrane structures and methods for fabricating same | |
| CN102328899A (en) | Method for manufacturing cavities of different depths | |
| CN102539033B (en) | The method for making of pressure sensor for micro electro-mechanical system | |
| CN102259820B (en) | Cavity structure, manufacturing method of cavity structure and manufacturing method of pressure-sensitive sensor | |
| CN102338681B (en) | Planar silicon pressure sensor and manufacturing method thereof | |
| CN102259823B (en) | Method for producing MEMS pressure-sensitive sensing element | |
| CN102259822B (en) | Method for preparing pressure-sensitive sensor and method for forming cavity structure on silicon wafer | |
| US10556791B2 (en) | CMOS compatible capacitive absolute pressure sensors | |
| CN105628054B (en) | Inertial sensor and preparation method thereof | |
| Wang et al. | A dual-unit pressure sensor for on-chip self-compensation of zero-point temperature drift | |
| CN102297737B (en) | Pressure sensor cavity structure and manufacturing method thereof | |
| CN111076851B (en) | Pressure sensor and manufacturing method thereof | |
| CN102336388B (en) | Preparation method of pressure-sensitive transducer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140109 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140109 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |