CN101832831B - Piezoresistive sensor chip and manufacture method thereof - Google Patents
Piezoresistive sensor chip and manufacture method thereof Download PDFInfo
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- CN101832831B CN101832831B CN201010152895.2A CN201010152895A CN101832831B CN 101832831 B CN101832831 B CN 101832831B CN 201010152895 A CN201010152895 A CN 201010152895A CN 101832831 B CN101832831 B CN 101832831B
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Abstract
The invention relates to a piezoresistive sensor chip which has convenient production, low cost and high yield and precision. The piezoresistive sensor chip comprises a pressure film layer, a substrate, a piezoresistor and a metal lead, wherein the piezoresistor and the metal lead are arranged on the upper surface of the pressure film layer; and the substrate is arranged on the lower surface of the pressure film layer. The piezoresistive sensor chip is characterized in that the substrate is specifically a silicon substrate; the pressure film layer comprises a bottom polycrystalline silicon film and an upper oxidation layer; and the lower surface of the bottom polycrystalline silicon film is arranged on the upper surface of the silicon substrate.
Description
Technical field
The present invention relates to art of pressure sensors, be specially a kind of piezoresistance sensor chip, present invention also offers the method for making making this piezoresistance sensor chip.
Background technology
MEMS(micromechanics electronics) pressure transducer is one of product the earliest in microelectromechanical systems, is divided into pressure resistance type, condenser type and piezoelectric type etc. according to principle of work.Piezoresistive pressure sensor has highly sensitive, fast response time, good reliability because of it, is easy to the advantage such as integrated and is widely applied in fields such as space flight, medicine equipment and automotive electronics.
Existing body silicon pressure sensor chip, the encapsulation that its substrate of glass need realize between the pressure sensitive film on upper strata by bonding technology, causes that the production difficulty of this structure is large, production cost is high, and easily produce waste product, yield rate is low; And do not mate due to the thermal expansivity of silicon and glass, cause the pressure transducer of temperature coefficient all more than surface micromachined of the Sensitivity in Pressure Sensors temperature coefficient of bulk silicon micromachining and zero output much larger, it uses, and real error is large, degree of accuracy is not high.
In addition, existing body silicon pressure sensor chip, in manufacturing process, must carry out anisotropic wet deep etch to silicon chip back, the demand of lower range test could be met after thinning, waste areas a large amount of on silicon chip like this, cause the waste of material, make production cost high.
Summary of the invention
For the problems referred to above, the invention provides a kind of piezoresistance sensor chip, it is convenient for production, cost is low, and yield rate is high, degree of accuracy is high.
Its technical scheme is such:
It comprises pressure rete, substrate, force sensing resistance, metal lead wire, described force sensing resistance, metal lead wire are installed on the upper surface of described pressure rete, described substrate is loaded on the lower surface of described pressure rete, it is characterized in that: described substrate is specially substrate silicon, described pressure rete comprises the polysilicon film of bottom, the oxide layer on upper strata, and the polysilicon film lower surface of described bottom is loaded on the upper surface of described substrate silicon.
It is further characterized in that: the lower surface of described polysilicon film and the upper surface of described substrate silicon are closed its centre afterwards and formed a vacuum chamber;
The polysilicon film of described bottom has through corrosion hole, is full of the material identical with described upper strata oxide layer in described corrosion hole;
Described force sensing resistance be specially coat described upper strata oxide layer polycrystalline silicon membrane through the force sensing resistance bar of dry etching;
The pressure rete position that described vacuum chamber is corresponding is specifically divided into film district, Liang Qu, and described beam district lateral arrangement is in the center on described vacuum chamber top, and described film district is symmetrically arranged in longitudinal both sides of described Liang Qu;
Described film district is lower than described Liang Qu, and the underlying polysilicon film in described film district exposes, and described Liang Qu comprises polysilicon film, the oxide layer on upper strata, the silicon nitride layer coated in the oxide layer of described upper strata of bottom;
Described force sensing resistance bar is symmetrically arranged in cross central line both sides, described beam district, and the upper strata of described force sensing resistance bar is coated with described silicon nitride layer, and described metal lead wire is communicated with described force sensing resistance bar by fairlead.
A method for making for piezoresistance sensor chip, is characterized in that:
In substrate silicon upper surface growth oxide layer, photoetching also corrodes the oxide layer in Bei great Mo district, large film regioselectivity growth PSG (mixing the cryogenic oxidation silicon of phosphorus) of the back of the body as sacrifice layer, and anti-carve the oxide layer in Fei Bei great Mo district, at substrate silicon upper surface growing polycrystalline silicon film; Photoetching also corrodes the corrosion hole of polysilicon film, and releasing sacrificial layer, with the SiO that the method deposit 2um of PECVD (plasma enhanced chemical vapor deposition) is thick
2blocking corrosion hole, and carry out densification; Depositing polysilicon film, anti-carves resistance area in its front, and forms polysilicon resistance bar after dry etching; Deposit Si
3n
4, photoetching Liang Qu, by the oxide layer in beam district carving Shi Mo district to form beam-membrane structure; Lithography fair lead, anti-carves Al lead-in wire, completes metal lead wire after alloying after steaming Al.
It is further characterized in that:
Its concrete steps are as follows:
A, standard cleaning is carried out to substrate silicon, rear deionized water rinsing, and with drier dehydration, dry, then, the silicon chip handled well is placed on thermal oxide in oxidation furnace, makes its one side form the SiO of 0.1um ~ 1um
2oxide layer;
B, photoetching Bei great Mo district, the SiO in corrosion Bei great Mo district
2oxide layer, continuation TMAH(Tetramethylammonium hydroxide) corrode the silicon 1 um ~ 5um in Bei great Mo district; With deionized water rinsing after cleaning, enter after oven dry in PECVD (plasma enhanced chemical vapor deposition) stove and grow PSG (mixing the cryogenic oxidation silicon of phosphorus), as sacrifice layer, the thickness of the PSG wherein grown is identical with the thickness of the silicon in the Bei great Mo district be corroded;
C, anti-carve Bei great Mo district, the oxide layer in corrosion Fei Bei great Mo district.With deionized water rinsing after cleaning, after oven dry, enter LPCVD(low-pressure chemical vapor deposition) grow the polysilicon film of bottom, thickness 1 ~ 5um in stove;
D, lithographic definition corrosion hole, adopt the method for dry etching to remove polysilicon in corrosion hole, then with dry method or wet process releasing sacrificial layer PSG (mixing the cryogenic oxidation silicon of phosphorus); With deionized water rinsing after cleaning, enter after oven dry in PECVD (plasma enhanced chemical vapor deposition) stove and grow SiO
2film 1 ~ 5um, puts into after oxidation furnace carries out dense oxide process and blocks corrosion hole;
E, the silicon chip completing above-mentioned operation is put into LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 0.1 ~ 1um, to be spread by boron or boron ion implantation makes polysilicon membrane adulterate, spread for activator impurity and elimination or inject the defect caused, and impurity is uniformly distributed, silicon chip is placed on annealing in process under 950 DEG C ~ 1200 DEG C nitrogen protections;
The shape of f, lithographic definition polysilicon force sensing resistance bar, adopts the method for dry etching to leave the force sensing resistance bar of polysilicon in desired location, with deionized water rinsing after cleaning; LPCVD(low-pressure chemical vapor deposition is entered after oven dry) grow Si in stove
3n
4film 0.1 ~ 1um;
G, photoetching Liang Qu, remove silicon nitride layer, the oxide layer in film district successively, forms beam-membrane structure;
H, lithography fair lead, anti-carve Al lead-in wire, complete metal lead wire after alloying after steaming Al.
In the present invention, because described substrate is specially substrate silicon, itself and the thermal expansivity of pressure rete and the temperature coefficient of zero output match, and guarantee that the degree of accuracy in use procedure is high; After using the method, it is without the need to carrying out bonding technology, and it is convenient for production and production cost is low; In addition, this invention is without the need to carrying out anisotropic wet deep etch to silicon chip back again and without the need to thinning, therefore the material of silicon chip required for it is little, and the utilization factor of silicon chip is high, greatly reduces production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of front view of the present invention;
Fig. 2 is the structural representation (force sensing resistance bar position is illustrated position, the silicon nitride omitting force sensing resistance bar upper strata) of the vertical view of Fig. 1;
Fig. 3 be fabrication processing figure of the present invention (wherein penultimate stride be Fig. 2 to should the B-B of step to cut-open view, all the other steps are that the A-A of Fig. 2 its step corresponding is respectively to cut-open view).
Embodiment
Its structure is shown in Fig. 1, Fig. 2: it comprises pressure rete, substrate, force sensing resistance, metal lead wire 2, force sensing resistance, metal lead wire 2 are installed on the upper surface of pressure rete, substrate is loaded on the lower surface of pressure rete, substrate is specially substrate silicon 3, pressure rete comprises the polysilicon film 4 of bottom, the oxide layer 5 on upper strata, and polysilicon film 4 lower surface of bottom is loaded on the upper surface of substrate silicon 3; The lower surface of polysilicon film 4 and the upper surface of substrate silicon 3 are closed its centre afterwards and are formed a vacuum chamber 6; The polysilicon film 4 of bottom has through corrosion hole 7, is full of the material identical with the oxide layer 5 on upper strata in corrosion hole 7; Force sensing resistance is specially the polycrystalline silicon membrane of the coating upper strata oxide layer force sensing resistance bar 8 through dry etching; The pressure rete position of vacuum chamber 6 correspondence is specifically divided into film district 9, beam district 10, and beam district 10 lateral arrangement is in the center on vacuum chamber 6 top, and film district 9 is symmetrically arranged in longitudinal both sides in beam district 10; Film district 9 is lower than beam district 10, and the underlying polysilicon film 4 in film district 9 exposes, and beam district 10 comprises polysilicon film 4, the oxide layer 5 on upper strata, the silicon nitride 11 coated in upper strata oxide layer 5 of bottom; Force sensing resistance bar 8 is symmetrically arranged in cross central line both sides, beam district 10, and the upper strata of force sensing resistance bar 8 is coated with silicon nitride 11, and metal lead wire 2 is communicated with force sensing resistance bar 8 by fairlead 1.
Its fabrication processing is shown in Fig. 3:
Specific embodiment is as follows:
Embodiment one:
A, standard cleaning is carried out to substrate silicon 3, rear deionized water rinsing, and with drier dehydration, dry.Then, the substrate silicon 3 handled well is placed on thermal oxide in oxidation furnace, one side forms the SiO of 0.1um
2oxide layer 13.
B, photoetching Bei great Mo district, the SiO in corrosion Bei great Mo district
2oxide layer 13, continuation TMAH(Tetramethylammonium hydroxide) corrode the silicon 1um in Bei great Mo district, with deionized water rinsing after cleaning, the PSG (mixing the cryogenic oxidation silicon of phosphorus) growing 1um in PECVD (plasma enhanced chemical vapor deposition) stove is entered, as sacrifice layer 14 after oven dry.
C, anti-carve Bei great Mo district, the oxide layer 13 in corrosion Fei Bei great Mo district, with deionized water rinsing after cleaning, enters LPCVD(low-pressure chemical vapor deposition after oven dry) grow the polysilicon film 4 of bottom, thickness 1um in stove.
D, on the polysilicon film 4 of bottom lithographic definition corrosion hole 7, the method of employing dry etching removes the polysilicon in corrosion hole 7, again with dry method or wet process releasing sacrificial layer 14, with deionized water rinsing after cleaning, enter after oven dry in PECVD (plasma enhanced chemical vapor deposition) stove and grow SiO
2film 1um, as upper strata oxide layer 5, puts into after oxidation furnace carries out dense oxide process and blocks corrosion hole 7.
E, the silicon chip completing above-mentioned operation is put into LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 0.1um; to be spread by boron or boron ion implantation makes polysilicon membrane adulterate; spread for activator impurity and elimination or inject the defect caused; and impurity is uniformly distributed; silicon chip is placed on annealing in process under 950 DEG C of nitrogen protections, generates and treat corrosion layer 12.
F, on bag corrosion layer 12 shape of lithographic definition polysilicon force sensing resistance bar 8, the method of dry etching is adopted to leave the force sensing resistance bar 8 of polysilicon in desired location, with deionized water rinsing after cleaning, LPCVD(low-pressure chemical vapor deposition is entered after oven dry) grown silicon nitride layer 11 in stove, thickness 0.1um.
G, photoetching beam district 10, remove silicon nitride layer 11, the upper strata oxide layer 5 in film district 9 successively, forms beam-membrane structure.
H, lithography fair lead 12, anti-carve Al lead-in wire, complete metal lead wire 2 after alloying after steaming Al.
Embodiment two:
A, standard cleaning is carried out to substrate silicon 3, rear deionized water rinsing, and with drier dehydration, dry.Then, the substrate silicon 3 handled well is placed on thermal oxide in oxidation furnace, one side forms the SiO of 0.5um
2oxide layer 13.
B, photoetching Bei great Mo district, the SiO in corrosion Bei great Mo district
2oxide layer 13, continuation TMAH(Tetramethylammonium hydroxide) corrode the silicon 3um in Bei great Mo district, with deionized water rinsing after cleaning, the PSG (mixing the cryogenic oxidation silicon of phosphorus) growing 3um in PECVD (plasma enhanced chemical vapor deposition) stove is entered, as sacrifice layer 14 after oven dry.
C, anti-carve Bei great Mo district, the oxide layer 13 in corrosion Fei Bei great Mo district, with deionized water rinsing after cleaning, enters LPCVD(low-pressure chemical vapor deposition after oven dry) grow the polysilicon film 4 of bottom, thickness 1um in stove.
D, on the polysilicon film 4 of bottom lithographic definition corrosion hole 7, the method of employing dry etching removes the polysilicon in corrosion hole 7, again with dry method or wet process releasing sacrificial layer 14, with deionized water rinsing after cleaning, enter after oven dry in PECVD (plasma enhanced chemical vapor deposition) stove and grow SiO
2film 3um, as upper strata oxide layer 5, puts into after oxidation furnace carries out dense oxide process and blocks corrosion hole 7.
E, the silicon chip completing above-mentioned operation is put into LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 0.5um; to be spread by boron or boron ion implantation makes polysilicon membrane adulterate; spread for activator impurity and elimination or inject the defect caused; and impurity is uniformly distributed; silicon chip is placed on annealing in process under 1100 DEG C of nitrogen protections, generates and treat corrosion layer 12.
F, on bag corrosion layer 12 shape of lithographic definition polysilicon force sensing resistance bar 8, the method of dry etching is adopted to leave the force sensing resistance bar 8 of polysilicon in desired location, with deionized water rinsing after cleaning, LPCVD(low-pressure chemical vapor deposition is entered after oven dry) grown silicon nitride layer 11 in stove, thickness 0.5um.
G, photoetching beam district 10, remove silicon nitride layer 11, the upper strata oxide layer 5 in film district 9 successively, forms beam-membrane structure.
H, lithography fair lead 12, anti-carve Al lead-in wire, complete metal lead wire 2 after alloying after steaming Al.
Embodiment three:
A, standard cleaning is carried out to substrate silicon 3, rear deionized water rinsing, and with drier dehydration, dry.Then, the substrate silicon 3 handled well is placed on thermal oxide in oxidation furnace, one side forms the SiO of 1um
2oxide layer 13.
B, photoetching Bei great Mo district, the SiO in corrosion Bei great Mo district
2oxide layer 13, continuation TMAH(Tetramethylammonium hydroxide) corrode the silicon 5um in Bei great Mo district, with deionized water rinsing after cleaning, the PSG (mixing the cryogenic oxidation silicon of phosphorus) growing 5um in PECVD (plasma enhanced chemical vapor deposition) stove is entered, as sacrifice layer 14 after oven dry.
C, anti-carve Bei great Mo district, the oxide layer 13 in corrosion Fei Bei great Mo district, with deionized water rinsing after cleaning, enters LPCVD(low-pressure chemical vapor deposition after oven dry) grow the polysilicon film 4 of bottom, thickness 5um in stove.
D, on the polysilicon film 4 of bottom lithographic definition corrosion hole 7, the method of employing dry etching removes the polysilicon in corrosion hole 7, again with dry method or wet process releasing sacrificial layer 14, with deionized water rinsing after cleaning, enter after oven dry in PECVD (plasma enhanced chemical vapor deposition) stove and grow SiO
2film 5um, as upper strata oxide layer 5, puts into after oxidation furnace carries out dense oxide process and blocks corrosion hole 7.
E, the silicon chip completing above-mentioned operation is put into LPCVD(low-pressure chemical vapor deposition) stove preparing polysilicon film 1um; to be spread by boron or boron ion implantation makes polysilicon membrane adulterate; spread for activator impurity and elimination or inject the defect caused; and impurity is uniformly distributed; silicon chip is placed on annealing in process under 1200 DEG C of nitrogen protections, generates and treat corrosion layer 12.
F, on bag corrosion layer 12 shape of lithographic definition polysilicon force sensing resistance bar 8, the method of dry etching is adopted to leave the force sensing resistance bar 8 of polysilicon in desired location, with deionized water rinsing after cleaning, LPCVD(low-pressure chemical vapor deposition is entered after oven dry) grown silicon nitride layer 11 in stove, thickness 1um.
G, photoetching beam district 10, remove silicon nitride layer 11, the upper strata oxide layer 5 in film district 9 successively, forms beam-membrane structure.
H, lithography fair lead 12, anti-carve Al lead-in wire, complete metal lead wire 2 after alloying after steaming Al.
Claims (1)
1. a method for making for piezoresistance sensor chip, is characterized in that: its concrete steps are as follows,
A, standard cleaning is carried out to substrate silicon, rear deionized water rinsing, and with drier dehydration, dry, then, the silicon chip handled well is placed on thermal oxide in oxidation furnace, makes its one side form the SiO of 0.1 ~ 1um
2oxide layer;
B, photoetching Bei great Mo district, the SiO in corrosion Bei great Mo district
2oxide layer, continuation Tetramethylammonium hydroxide (TMAH) corrodes the silicon 1 ~ 5um in Bei great Mo district; With deionized water rinsing after cleaning, enter growth in plasma enhanced chemical vapor deposition (PECVD) stove after oven dry and mix the cryogenic oxidation silicon (PSG) of phosphorus, as sacrifice layer, the thickness of the cryogenic oxidation silicon (PSG) mixing phosphorus wherein grown is identical with the thickness of the silicon in the Bei great Mo district be corroded;
C, anti-carve Bei great Mo district, the oxide layer in corrosion Fei Bei great Mo district; With deionized water rinsing after cleaning, enter the polysilicon film growing bottom in low-pressure chemical vapor deposition (LPCVD) stove after oven dry, thickness 1 ~ 5um;
D, lithographic definition corrosion hole, the method for employing dry etching removes the polysilicon in corrosion hole, then mixes the cryogenic oxidation silicon (PSG) of phosphorus with dry method or wet process releasing sacrificial layer; With deionized water rinsing after cleaning, enter after oven dry in plasma enhanced chemical vapor deposition (PECVD) stove and grow SiO
2film 1 ~ 5um, puts into after oxidation furnace carries out dense oxide process and blocks corrosion hole;
E, the silicon chip completing above-mentioned operation is put into low-pressure chemical vapor deposition (LPCVD) stove preparing polysilicon film 0.1 ~ 1um, to be spread by boron or boron ion implantation makes polysilicon membrane adulterate, spread for activator impurity and elimination or inject the defect caused, and impurity is uniformly distributed, silicon chip is placed on annealing in process under 950 DEG C ~ 1200 DEG C nitrogen protections;
F, anti-carve resistance area in polysilicon membrane front, the shape of lithographic definition polysilicon force sensing resistance bar, adopt the method for dry etching to leave the force sensing resistance bar of polysilicon in desired location; With deionized water rinsing after cleaning; Enter after oven dry in low-pressure chemical vapor deposition (LPCVD) stove and grow Si
3n
4film 0.1 ~ 1um;
G, photoetching Liang Qu, remove silicon nitride layer, the oxide layer in film district successively, forms beam-membrane structure;
H, lithography fair lead, anti-carve Al lead-in wire, complete metal lead wire after alloying after steaming Al.
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Effective date of registration: 20170421 Address after: 223300 Jiangsu City, Huaiyin province (Industrial Park), Nanchang Road, No. three, layer 605, layer Patentee after: Huaian nano sensor Co., Ltd. Address before: 214028 Changjiang Road, New District, Jiangsu, Wuxi, No. 7 Patentee before: Wuxi Nano MEMS, Inc. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150128 Termination date: 20170422 |