CN102194697B - 半导体结构的形成方法 - Google Patents
半导体结构的形成方法 Download PDFInfo
- Publication number
- CN102194697B CN102194697B CN201010224425.2A CN201010224425A CN102194697B CN 102194697 B CN102194697 B CN 102194697B CN 201010224425 A CN201010224425 A CN 201010224425A CN 102194697 B CN102194697 B CN 102194697B
- Authority
- CN
- China
- Prior art keywords
- fin
- epitaxial region
- effect transistor
- field effect
- thin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000005669 field effect Effects 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000002513 implantation Methods 0.000 claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 29
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 238000000407 epitaxy Methods 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 229910045601 alloy Inorganic materials 0.000 description 11
- 239000000956 alloy Substances 0.000 description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明提供一种半导体结构的形成方法,包含:提供一基底,上述基底在其一表面具有一鳍状物;以及形成一鳍式场效应晶体管,其还具有:在上述鳍状物上形成一栅极堆叠结构;在上述栅极堆叠结构的一侧壁上形成一薄层间隙壁;及以外延的方式从上述鳍状物生长一外延区。在上述外延区的外延生长的步骤之后,在上述薄层间隙壁的一外缘上形成一主间隙壁。在形成上述主间隙壁的步骤之后,执行一深源/漏极掺杂步骤,以形成上述鳍式场效应晶体管的一深源/漏极区。本发明会得到减低漏电流的效果,但是未牺牲短沟道特性。
Description
技术领域
本发明主要涉及半导体装置,特别涉及鳍式场效应晶体管(fin field effecttransistors;finFETs)的轻掺杂源/漏极(lightly doped source and drain;LDD)区与外延区的形成方法。
背景技术
随着集成电路尺寸的缩减,金属-氧化物-半导体(metal-oxide-semiconductor;MOS)装置的尺寸日益变小,金属-氧化物-半导体装置的结深度也随之缩减,这样的缩减导致在金属-氧化物-半导体装置的制造上面临了技术上的难题。例如,为了减少源极与漏极的电阻,较小的金属-氧化物-半导体装置需要较高的源极与漏极的掺杂物浓度及/或较大的结深度。然而,较高的掺杂物浓度,特别在轻掺杂源/漏极(lightly dopedsource and drain;LDD)区会造成漏电流的增加,而轻掺杂源/漏极区的结深度的增加,会造成所制造的金属-氧化物-半导体装置的短沟道特性的损害。
发明内容
有鉴于此,本发明提供一种半导体结构的形成方法,包含:提供一基底,上述基底在其一表面具有一鳍状物;以及形成一鳍式场效应晶体管,其还具有:在上述鳍状物上形成一栅极堆叠结构;在上述栅极堆叠结构的一侧壁上形成一薄层间隙壁;及以外延的方式从上述鳍状物生长一外延区。在上述外延区的外延生长的步骤之后,在上述薄层间隙壁的一外缘上形成一主间隙壁。在形成上述主间隙壁的步骤之后,执行一深源/漏极掺杂步骤,以形成上述鳍式场效应晶体管的一深源/漏极区。
本发明又提供一种半导体结构的形成方法,包含:提供一半导体基底,上述半导体基底在一P型金属-氧化物-半导体区内具有一第一鳍状物、在一N型金属-氧化物-半导体区内具有一第二鳍状物;在上述P型金属-氧化物-半导体区中形成一P型鳍式场效应晶体管;以及在上述N型金属-氧化物-半导体区中形成一N型鳍式场效应晶体管。上述P型鳍式场效应晶体管的形成还具有:在上述第一鳍状物上形成一第一栅极堆叠结构;在上述第一栅极堆叠结构的一侧壁上形成一第一薄层间隙壁;以上述第一薄层间隙壁为掩模,执行一第一轻掺杂源/漏极注入步骤;以上述第一薄层间隙壁为掩模,在上述第一鳍状物中形成一凹部;以外延的方式在上述凹部中生长一第一外延区;及在上述第一外延区的外延生长步骤之后,在上述第一薄层间隙壁的侧壁上形成一第一主间隙壁。上述N型鳍式场效应晶体管的形成,还具有:在上述第二鳍状物上形成一第二栅极堆叠结构;在上述第二栅极堆叠结构的一侧壁上形成一第二薄层间隙壁;以上述第二薄层间隙壁为掩模,执行一第二轻掺杂源/漏极注入步骤;以外延的方式在上述第二鳍状物的一上表面与侧壁的暴露部分上,生长一第二外延区;及在上述第二外延区的外延生长步骤之后,在上述第二薄层间隙壁的侧壁上形成一第二主间隙壁。
本发明又提供一种半导体结构的形成方法,包含:提供一基底,上述基底在其一表面具有一鳍状物;以及形成一鳍式场效应晶体管,其具有:在上述鳍状物上形成一栅极堆叠结构;在上述栅极堆叠结构的一侧壁上形成一薄层间隙壁;在上述薄层间隙壁的一外缘上形成一主间隙壁;以外延的方式生长具有一内缘的一外延区,上述内缘实质上垂直于上述薄层间隙壁与上述主间隙壁之间的一界面;及在形成上述主间隙壁的步骤之后,执行一深源/漏极掺杂步骤,以形成上述鳍式场效应晶体管的一深源/漏极区。
本发明会得到减低漏电流的效果,但是未牺牲短沟道特性(short channelcharacteristics)。
附图说明
图1~图17是一系列的剖面图,显示本发明优选实施例的鳍式场效应晶体管(fin field-effect transistors;FinFETs)的制造过程中的中间步骤。
其中,附图标记说明如下:
20~基底 22~浅沟槽隔离区
38~掩模层 41~掩模层
41_1~氧化物层 41_2~氮化硅层
48~掩模 48_1~氧化物层
48_2~氮化硅层 56~介电层
58~光致抗蚀剂 100~N型金属-氧化物-半导体区
124~半导体鳍状物 125~虚线
132~栅介电质 134~栅极
135~掩模层(硬掩模) 136~薄层间隙壁
138~薄层间隙壁 140~轻掺杂源/漏极区
144~外延区 150~光致抗蚀剂
156~主间隙壁 157~外侧壁
160~深源/漏极区 162~硅化物区
200~P型金属-氧化物-半导体区 224~半导体鳍状物
232~栅介电质 234~栅极
235~掩模层(硬掩模) 236~薄层间隙壁
238~薄层间隙壁 240~轻掺杂源/漏极区
242~光致抗蚀剂 244~外延区(SiGe应力源)
252~凹部 256~主间隙壁
257~外侧壁 260~深源/漏极区
262~硅化物区
具体实施方式
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举出优选实施例,并配合附图,作详细说明如下:
在以下实施例中,提供鳍式场效应晶体管(fin field-effect transistors;FinFETs)的形成方法,在附图中所示出的实施例的制造过程的中间阶段,一并示出一P型鳍式场效应晶体管与一N型鳍式场效应晶体管的形成。在以下的文字叙述及附图所示的实施例中,类似的元件符号用以代表类似的元件。
请参考图1,提供一基底20,其具有位于N型金属-氧化物-半导体区100中的一部分与位于P型金属-氧化物-半导体区200中的一部分。基底20可以是一块硅(bulk silicon)基底,而也可以是其他常用的结构与材料,例如绝缘体上覆硅(silicon-on-insulator;SOI)结构与硅合金。基底20可以是已掺杂P型或N型掺杂物的基底。在基底20上或基底20中,可形成有隔离区例如浅沟槽隔离(shallow trench isolation;STI)区22。半导体鳍状物124与224分别形成于N型金属-氧化物-半导体区100与P型金属-氧化物-半导体区200中,其为高于邻近的浅沟槽隔离区22的上表面的半导体区域。用以形成半导体鳍状物124与224的工艺步骤已是在本发明所属技术领域中广为人知的技术,因此在此不讨论。
一第一栅极堆叠结构形成于半导体鳍状物124的上表面与侧壁上,上述第一栅极堆叠结构具有栅介电质132与栅极134。一第二栅极堆叠结构形成于半导体鳍状物224的上表面与侧壁上,上述第二栅极堆叠结构具有栅介电质232与栅极234。栅极134与234可使用常用的导体材料来形成,例如为多晶硅、金属、金属硅化物、金属氮化物、与上述的组合。栅介电质132与232可包含常用的介电材料,例如氧化物、氮化物、氧氮化物、碳化物、与上述的组合。每一个上述的栅极堆叠结构,可分别在栅极134与234上还具有掩模层135/235,其中上述掩模层可以氮化硅来形成。
图1也示出薄层间隙壁136与236的形成。薄层间隙壁136与236的厚度可以是例如小于而也可以是其他厚度。本发明所属技术领域中的普通技术人员应可了解在整份本说明书中所公开的尺寸均仅止于举例,而在使用其他形成技术的情况下,这些尺寸会有所变动。可用于薄层间隙壁136与236的材料包含常用的间隔物材料,例如氧化物(例如氧化硅)。如本发明所属技术领域中的已知技术,薄层间隙壁136与236的形成可包含形成一间隔物层、然后图形化此间隔物层而移除其水平的部分。
请参考图2,毯覆性地形成掩模层38,掩模层3可以是以异于薄层间隙壁136与236的材料所形成。在一实施例中,以氮化硅来形成掩模层38。掩模层38的厚度,例如可为小于接下来,如图3所示,蚀刻掩模层38,而分别残留于薄层间隙壁136与236的侧壁上的掩模层38的垂直部分,则形成薄层间隙壁138与238。在整份的本说明书中,薄层间隙壁136与138的组合视为一薄层间隙壁,而薄层间隙壁236与238的组合也视为一薄层间隙壁。
图3也示出用以形成轻掺杂源/漏极(lightly doped source and drain;LDD)区的掺杂或注入步骤,其中将一N型掺杂物注入半导体鳍状物124中,而将一P型掺杂物注入半导体鳍状物224中,而分别在半导体鳍状物124与224中形成轻掺杂源/漏极区140与240。可以执行一退火步骤。因此,上述N型与P型掺杂物的扩散会使轻掺杂源/漏极区140与240分别延伸至薄层间隙壁136/138与236/238的下方。N型掺杂物与P型掺杂物的掺杂浓度均可以是5×1019/cm3~1×1020/cm3、或可以是1×1018/cm3~5×1019/cm3,但也可使用其他适用于轻掺杂源/漏极区的不同浓度。
在图4中,形成掩模层41来覆盖N型金属-氧化物-半导体区100与P型金属-氧化物-半导体区200中的结构,然后形成光致抗蚀剂242来覆盖P型金属-氧化物-半导体区200、但未覆盖N型金属-氧化物-半导体区100。掩模层41可具有氧化物层41_1与氮化硅层41_2。接下来如图5所示,移除N型金属-氧化物-半导体区100中的掩模层41的受到暴露的部分,然后移除光致抗蚀剂242。请注意在移除掩模层41的过程中,可以发生、或未发生损失一部分的半导体鳍状物124的副作用,其中图5中的虚线125显示损失了一部分的半导体鳍状物124之后的半导体鳍状物124的上表面。
请参考图6A与图6B,例如通过选择式的外延生长技术(selective epitaxialgrowth;SEG),在半导体鳍状物124的暴露表面形成外延区144。外延区144的内缘可实质上垂直于薄层间隙壁138的外侧壁157。外延区144可由硅磷(silicon phosphorous;SiP)、硅碳(silicon carbon)、或同类材料所形成。在外延生长硅碳的情况中,可以在外延生长的过程中,同步(in-situ)掺杂N型的掺杂物例如磷。在一实施例中,磷的原子百分比可大于0.2%,且在硅磷中的磷的浓度可大于1×1020/cm3。在移除部分的掩模层41的过程中半导体鳍状物124受到损失(请参考图5中的虚线125)的实施例中,外延区144的上表面会生长而结果高于半导体鳍状物124的上表面,所形成的结构示于图6A中。在一替代的实施例中,若半导体鳍状物124并未在移除掩模层41的过程中受到损失,外延区144会形成于半导体鳍状物124的暴露的上表面与侧壁上,如图6B所示。在一例示的实施例中,外延区144的厚度是在形成外延区144之后,移除掩模层41,所形成的结构如图7所示。
图8~图10示出在半导体鳍状物224上形成外延区244。在图8中,形成掩模48来覆盖N型金属-氧化物-半导体区100与P型金属-氧化物-半导体区200中的结构,然后形成光致抗蚀剂150来覆盖N型金属-氧化物-半导体区100、但未覆盖P型金属-氧化物-半导体区200。掩模层48可具有氧化物层48_1与位于氧化物层48_1上的氮化硅层48_2。接下来,如图9所示,将P型金属-氧化物-半导体区200中的掩模48的暴露的部分移除,然后移除光致抗蚀剂150。然后,以薄层间隙壁236/238为掩模,执行一凹下的工艺而在半导体鳍状物224中形成凹部252。如果从图9的左侧或右侧观察,凹部252实际上代表移除部分的半导体鳍状物224之后所留下的空间,其中以虚线来标示凹部252的边界。在一实施例中,凹部252可延伸至低于浅沟槽隔离区22的上表面之处。
请参考图10,例如通过选择式的外延生长技术(selective epitaxial growth;SEG),从半导体鳍状物224的暴露表面开始形成外延区244。外延区244的内缘可实质上垂直于薄层间隙壁238的外侧壁257。外延区244可由硅锗(silicon germanium;SiGe)、硅、或同类材料所形成。在后文中,也将外延区244称为SiGe应力源。所形成的SiGe应力源244所具有的锗的原子百分比可以是10%~40%,但也可以是其他的原子百分比。在一实施例中,在外延区244的外延生长的过程中并未掺杂P型的掺杂物。在一替代的实施例中,在外延生长的过程中,同步(in-situ)掺杂P型的掺杂物例如硼及/或铟,掺杂浓度为1×1018/cm3~1×1021/cm3。所形成的外延区244的上表面可高于原始的外延区244的上表面或与其同高。在一例示的实施例中,外延区244的厚度为在形成外延区244之后,移除掩模48,所形成的结构则示于图11。
图12与图13示出主间隙壁156与256的形成,其形成可通过毯覆性地沉积介电层56(图12),然后移除介电层56的水平部分(图13)。如图所示,主间隙壁156形成于薄层间隙壁138的外侧壁157上,而主间隙壁256则形成于薄层间隙壁238的外侧壁257上。另外,外延区144的内缘实质上垂直于主间隙壁156与薄层间隙壁138之间的界面(即标示为157之处),而外延区244的内缘实质上垂直于主间隙壁256与薄层间隙壁238之间的界面(即标示为257之处)。通过用的技术例如等离子体增益化学气相沉积法(plasmaenhanced chemical vapor deposition;PECVD)、低压化学气相沉积法(low-pressure chemical vapor deposition;LPCVD)、次大气压化学气相沉积法(sub-atmospheric chemical vapor deposition;SACVD)、及类似技术来执行介电层56的沉积。可通过执行例如干蚀刻来图形化介电层56。在一实施例中,以氮化硅来形成主间隙壁156与256;在一替代的实施例中,主间隙壁156与256包含衬垫氧化物(liner oxide)的部分及其上的氮化物的部分;在另一实施例中,主间隙壁156与256包含单层或多层,各包含氧化物、氮化硅、氧氮化硅(SiON)及/或其他介电材料。
请参考图14,涂上光致抗蚀剂58并予以回蚀,直到暴露出硬掩模135与235。然后,移除暴露的硬掩模135与235。之后,通过灰化来移除光致抗蚀剂58,所形成的结构示于图15。
接下来,如图16所示,执行掺杂或注入步骤来形成深源极与漏极区160与260(在后文称为深源/漏极区)。如本发明所属技术领域的已知技术,为了形成深源/漏极区,会先形成一第一光致抗蚀剂(未示出)以覆盖N型金属-氧化物-半导体区100。然后,执行一掺杂或注入步骤来导入P型掺杂物,而形成深源/漏极区260。然后,移除上述第一光致抗蚀剂。接下来,再形成一第二光致抗蚀剂(未示出)来覆盖P型金属-氧化物-半导体区200,接着执行一掺杂或注入步骤来导入N型掺杂物,而形成深源/漏极区160。然后,移除上述第二光致抗蚀剂。深源/漏极区160与260的掺杂浓度可以是1×1020/cm3~1×1021/cm3、或更高。
图17示出硅化物区162(可以是锗硅化(germano-silicide)区)与262的形成。如本发明所属技术领域的已知技术,可通过毯覆式地沉积一薄金属层来形成硅化物区162与262,其中上述金属例如为镍、铂、钯、钛、钴、及上述的组合。然后加热基底,以使硅、锗与其所接触的上述反应。在反应之后,则在硅(或硅锗)与上述金属之间形成一金属硅化物层。使用会侵蚀金属但不会侵蚀硅化物与锗硅化物的蚀刻剂,来选择性地移除未反应的金属。请注意硅化物区162与262的内缘实质上分别垂直于主间隙壁156与256的外侧壁。另一方面,外延区144与244则分别延伸至主间隙壁156与256的正下方。外延区144与244的内缘可分别实质上对齐于主间隙壁156与256的内缘。另外,外延区144与244的分别位于主间隙壁156与256的正下方的部位,由于分别未接受深源/漏极区相关的掺杂或注入,故可能会具有较低的掺杂浓度。
在上述实施例中,外延区144与244的形成会得到减低结漏电流的效果,但是未牺牲短沟道特性(short channel characteristics)。另外,减低了源极与漏极区的片电阻(sheet resistance)。模拟的结果显示,可使一P型金属-氧化物-半导体鳍式场效应晶体管的片电阻减少约30%。另外,通过使用硅锗来形成外延区244,施加在所形成的P型鳍式场效应晶体管的沟道区的应力会增加50MPa至100MPa,而会使P型鳍式场效应晶体管的驱动电流增加2.5%至5%(当薄层间隙壁236与238的合计厚度为15nm至20nm时)。通过外延区144与244分别延伸至主间隙壁156与256的下方、并因此近接于对应的沟道区的情况,使应力的增加所造成的驱动电流的增加所带来的效益最大化。
另一方面,外延区144的形成,会得到减低N型鳍式场效应晶体管中的漏电流的效果,但是未牺牲N型鳍式场效应晶体管的短沟道特性。
虽然本发明已以优选实施例公开如上,然其并非用以限定本发明,任何本发明所属技术领域中的普通技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。
Claims (11)
1.一种半导体结构的形成方法,包含:
提供一基底,该基底在其一表面具有一第一鳍状物;以及
形成一第一鳍式场效应晶体管,其具有:
在该第一鳍状物上形成一第一栅极堆叠结构;
在该第一栅极堆叠结构的一侧壁上形成一第一薄层间隙壁;
从该第一鳍状物以外延的方式生长一第一外延区;
在该第一外延区的外延生长步骤之前,使该第一鳍状物凹入而形成一凹部,该第一外延区则在该凹部中生长,
在该第一外延区的外延生长步骤之后,在该第一薄层间隙壁的外缘上形成一第一主间隙壁;及
在形成该第一主间隙壁的步骤之后,执行一第一深源/漏极掺杂步骤,以形成该第一鳍式场效应晶体管的一第一深源/漏极区。
2.如权利要求1所述的半导体结构的形成方法,还包含在该第一外延区的外延生长步骤之前,执行一注入步骤以在该第一鳍状物中形成一轻掺杂源/漏极区。
3.如权利要求1所述的半导体结构的形成方法,其中该第一鳍式场效应晶体管为N型的鳍式场效应晶体管,且该第一外延区包含一第一部分与一第二部分,该第一部分在该第一鳍状物的上表面上,该第二部分在该第一鳍状物的一侧壁上。
4.如权利要求1所述的半导体结构的形成方法,其中该第一鳍式场效应晶体管为P型的鳍式场效应晶体管。
5.如权利要求4所述的半导体结构的形成方法,还包含形成一第二鳍式场效应晶体管,其具有:
在一第二鳍状物上形成一第二栅极堆叠结构,其中该第二鳍状物位于该基底的该表面上;
在该第二栅极堆叠结构的一侧壁上形成一第二薄层间隙壁;
在该第二鳍状物上以外延的方式生长一第二外延区,其中该第二外延区包含一第一部分与一第二部分,该第一部分在该第二鳍状物的上表面上,该第二部分在该第二鳍状物的一侧壁上;
在该第二外延区的外延生长步骤之后,在该第二薄层间隙壁的外缘上形成一第二主间隙壁;及
在形成该第二主间隙壁的步骤之后,执行一第二深源/漏极掺杂步骤,以形成该第二鳍式场效应晶体管的一第二深源/漏极区。
6.一种半导体结构的形成方法,包含:
提供一半导体基底,该半导体基底在一P型金属-氧化物-半导体区内具有一第一鳍状物、在一N型金属-氧化物-半导体区内具有一第二鳍状物;
在该P型金属-氧化物-半导体区中形成一P型鳍式场效应晶体管,其具有:
在该第一鳍状物上形成一第一栅极堆叠结构;
在该第一栅极堆叠结构的一侧壁上形成一第一薄层间隙壁;
以该第一薄层间隙壁为掩模,执行一第一轻掺杂源/漏极注入步骤;
以该第一薄层间隙壁为掩模,在该第一鳍状物中形成一凹部;
以外延的方式在该凹部中生长一第一外延区;及
在该第一外延区的外延生长步骤之后,在该第一薄层间隙壁的侧壁上形成一第一主间隙壁;以及
在该N型金属-氧化物-半导体区中形成一N型鳍式场效应晶体管,其具有:
在该第二鳍状物上形成一第二栅极堆叠结构;
在该第二栅极堆叠结构的一侧壁上形成一第二薄层间隙壁;
以该第二薄层间隙壁为掩模,执行一第二轻掺杂源/漏极注入步骤;
以外延的方式在该第二鳍状物的一上表面与侧壁的暴露部分上,生长一第二外延区;及
在该第二外延区的外延生长步骤之后,在该第二薄层间隙壁的侧壁上形成一第二主间隙壁。
7.如权利要求6所述的半导体结构的形成方法,还包含:
在形成该第一主间隙壁之后,在该第一外延区上形成一第一硅化物区,其中该第一外延区的一内部未受到硅化,而该第一外延区的一外部受到硅化;以及
在形成该第二主间隙壁之后,在该第二外延区上形成一第二硅化物区,其中该第二外延区的一内部未受到硅化,而该第二外延区的一外部受到硅化。
8.如权利要求6所述的半导体结构的形成方法,其中该第一外延区具有一第一底部,该第一底部低于该第二外延区的一第二底部,且该第一底部低于一邻接的浅沟槽隔离区的一上表面、该第二底部则未低于该邻接的浅沟槽隔离区的该上表面。
9.一种半导体结构的形成方法,包含:
提供一基底,该基底在其一表面具有一鳍状物;以及
形成一鳍式场效应晶体管,其具有:
在该鳍状物上形成一栅极堆叠结构;
在该栅极堆叠结构的一侧壁上形成一薄层间隙壁;
在该薄层间隙壁的一外缘上形成一主间隙壁;
以外延的方式生长具有一内缘的一外延区,该内缘垂直于该薄层间隙壁与该主间隙壁之间的一界面;及
在形成该主间隙壁的步骤之后,执行一深源/漏极掺杂步骤,以形成该鳍式场效应晶体管的一深源/漏极区。
10.如权利要求9所述的半导体结构的形成方法,其中该鳍式场效应晶体管为一N型鳍式场效应晶体管,且该外延区具有一第一部分与一第二部分,该第一部分在该鳍状物的一上表面上,该第二部分在该鳍状物的一侧壁上。
11.如权利要求9所述的半导体结构的形成方法,其中该鳍式场效应晶体管为一P型鳍式场效应晶体管,且该方法还包含:在该外延区的外延生长步骤之前,使该鳍状物凹入而形成一凹部,其中该外延区具有位于该凹部中的一部分。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/720,476 US8278179B2 (en) | 2010-03-09 | 2010-03-09 | LDD epitaxy for FinFETs |
US12/720,476 | 2010-03-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102194697A CN102194697A (zh) | 2011-09-21 |
CN102194697B true CN102194697B (zh) | 2013-05-08 |
Family
ID=44560386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010224425.2A Active CN102194697B (zh) | 2010-03-09 | 2010-07-06 | 半导体结构的形成方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8278179B2 (zh) |
CN (1) | CN102194697B (zh) |
Families Citing this family (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101815527B1 (ko) * | 2010-10-07 | 2018-01-05 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8502288B2 (en) * | 2011-04-01 | 2013-08-06 | United Microelectronics Corp. | Semiconductor structure and method for slimming spacer |
US8420464B2 (en) * | 2011-05-04 | 2013-04-16 | International Business Machines Corporation | Spacer as hard mask scheme for in-situ doping in CMOS finFETs |
US9537004B2 (en) | 2011-05-24 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain formation and structure |
US8871626B2 (en) | 2011-12-20 | 2014-10-28 | International Business Machines Corporation | FinFET with vertical silicide structure |
US8445334B1 (en) | 2011-12-20 | 2013-05-21 | International Business Machines Corporation | SOI FinFET with recessed merged Fins and liner for enhanced stress coupling |
US9466696B2 (en) | 2012-01-24 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
US9171925B2 (en) | 2012-01-24 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate devices with replaced-channels and methods for forming the same |
US9281378B2 (en) | 2012-01-24 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin recess last process for FinFET fabrication |
CN103515283B (zh) * | 2012-06-25 | 2016-03-30 | 中国科学院微电子研究所 | 半导体器件制造方法 |
US8946791B2 (en) | 2012-08-31 | 2015-02-03 | International Business Machines Corporation | Finfet with reduced parasitic capacitance |
EP2704199B1 (en) * | 2012-09-03 | 2020-01-01 | IMEC vzw | Method of manufacturing a semiconductor device |
US9564367B2 (en) * | 2012-09-13 | 2017-02-07 | Globalfoundries Inc. | Methods of forming different FinFET devices with different threshold voltages and integrated circuit products containing such devices |
US9443962B2 (en) | 2012-11-09 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessing STI to increase fin height in fin-first process |
US9349837B2 (en) | 2012-11-09 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessing STI to increase Fin height in Fin-first process |
US9536792B2 (en) | 2013-01-10 | 2017-01-03 | United Microelectronics Corp. | Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof |
US9029226B2 (en) * | 2013-03-13 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for doping lightly-doped-drain (LDD) regions of finFET devices |
US9331176B2 (en) * | 2013-04-25 | 2016-05-03 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors, including forming source and drain regions in recesses of semiconductor fins |
US9006066B2 (en) | 2013-04-26 | 2015-04-14 | Globalfoundries Inc. | FinFET with active region shaped structures and channel separation |
US9034741B2 (en) | 2013-05-31 | 2015-05-19 | International Business Machines Corporation | Halo region formation by epitaxial growth |
US9293534B2 (en) | 2014-03-21 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of dislocations in source and drain regions of FinFET devices |
US10147793B2 (en) | 2013-07-30 | 2018-12-04 | Samsung Electronics Co., Ltd. | FinFET devices including recessed source/drain regions having optimized depths |
US9685509B2 (en) | 2013-07-30 | 2017-06-20 | Samsung Electronics Co., Ltd. | Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions |
US10157995B2 (en) * | 2013-08-09 | 2018-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating junction formation of transistors with contact formation |
US9391202B2 (en) | 2013-09-24 | 2016-07-12 | Samsung Electronics Co., Ltd. | Semiconductor device |
US9166044B2 (en) * | 2013-09-27 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Raised epitaxial LDD in MuGFETs |
US20150118832A1 (en) * | 2013-10-24 | 2015-04-30 | Applied Materials, Inc. | Methods for patterning a hardmask layer for an ion implantation process |
US9673194B2 (en) * | 2013-10-31 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement and formation thereof |
US10032911B2 (en) * | 2013-12-23 | 2018-07-24 | Intel Corporation | Wide band gap transistor on non-native semiconductor substrate |
KR102167518B1 (ko) * | 2013-12-23 | 2020-10-19 | 인텔 코포레이션 | 비고유 반도체 기판들 상의 넓은 밴드 갭 트랜지스터들 및 그 제조 방법들 |
KR102193493B1 (ko) * | 2014-02-03 | 2020-12-21 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN104851775A (zh) * | 2014-02-13 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | 一种修复位于有源区衬底上损伤的方法 |
KR102160100B1 (ko) | 2014-05-27 | 2020-09-25 | 삼성전자 주식회사 | 반도체 장치 제조 방법 |
US9659827B2 (en) | 2014-07-21 | 2017-05-23 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices by forming source/drain regions before gate electrode separation |
US10056462B2 (en) * | 2014-08-13 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Metal gate structure and manufacturing method thereof |
US10347766B2 (en) * | 2014-09-02 | 2019-07-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of fabricating the same |
US9818877B2 (en) | 2014-09-18 | 2017-11-14 | International Business Machines Corporation | Embedded source/drain structure for tall finFET and method of formation |
US10559690B2 (en) | 2014-09-18 | 2020-02-11 | International Business Machines Corporation | Embedded source/drain structure for tall FinFET and method of formation |
US9502418B2 (en) | 2014-10-02 | 2016-11-22 | International Business Machines Corporation | Semiconductor devices with sidewall spacers of equal thickness |
US9385191B2 (en) * | 2014-11-20 | 2016-07-05 | United Microelectronics Corporation | FINFET structure |
US9437445B1 (en) * | 2015-02-24 | 2016-09-06 | International Business Machines Corporation | Dual fin integration for electron and hole mobility enhancement |
US9525036B2 (en) * | 2015-03-19 | 2016-12-20 | Samsung Electronics Co., Ltd. | Semiconductor device having gate electrode with spacers on fin structure and silicide layer filling the recess |
KR102328564B1 (ko) | 2015-04-14 | 2021-11-18 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9437496B1 (en) | 2015-06-01 | 2016-09-06 | Globalfoundries Inc. | Merged source drain epitaxy |
US9620644B2 (en) | 2015-09-02 | 2017-04-11 | International Business Machines Corporation | Composite spacer enabling uniform doping in recessed fin devices |
US9679978B2 (en) | 2015-09-24 | 2017-06-13 | Samsung Electronics Co., Ltd. | Semiconductor device and method for fabricating the same |
CN106601677B (zh) * | 2015-10-14 | 2019-09-03 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法、电子装置 |
KR102375583B1 (ko) * | 2015-12-21 | 2022-03-16 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
US10043903B2 (en) * | 2015-12-21 | 2018-08-07 | Samsung Electronics Co., Ltd. | Semiconductor devices with source/drain stress liner |
CN106910739B (zh) * | 2015-12-21 | 2022-01-11 | 三星电子株式会社 | 半导体器件 |
KR102422158B1 (ko) * | 2015-12-23 | 2022-07-20 | 에스케이하이닉스 주식회사 | 반도체장치 및 그 제조 방법 |
KR102481427B1 (ko) | 2016-01-13 | 2022-12-27 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9722081B1 (en) * | 2016-01-29 | 2017-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device and method of forming the same |
US9634084B1 (en) | 2016-02-10 | 2017-04-25 | Globalfoundries Inc. | Conformal buffer layer in source and drain regions of fin-type transistors |
US10147649B2 (en) | 2016-05-27 | 2018-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with gate stack and method for forming the same |
KR102524806B1 (ko) | 2016-08-11 | 2023-04-25 | 삼성전자주식회사 | 콘택 구조체를 포함하는 반도체 소자 |
CN107799472B (zh) * | 2016-09-07 | 2020-04-10 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
US10008603B2 (en) * | 2016-11-18 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-gate device and method of fabrication thereof |
US9991165B1 (en) | 2016-11-29 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Asymmetric source/drain epitaxy |
US10084081B2 (en) | 2017-01-23 | 2018-09-25 | International Business Machines Corporation | Vertical transistor with enhanced drive current |
US10468530B2 (en) * | 2017-11-15 | 2019-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with source/drain multi-layer structure and method for forming the same |
US11037924B2 (en) * | 2017-11-21 | 2021-06-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming source/drain contacts |
KR102449608B1 (ko) | 2017-12-21 | 2022-10-04 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
US10763363B2 (en) * | 2018-04-10 | 2020-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gradient doped region of recessed fin forming a FinFET device |
US10867860B2 (en) * | 2018-08-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming FinFET device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6372589B1 (en) * | 2000-04-19 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer |
US6958512B1 (en) * | 2004-02-03 | 2005-10-25 | Advanced Micro Devices, Inc. | Non-volatile memory device |
US7268024B2 (en) * | 2003-04-30 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US7667271B2 (en) * | 2007-04-27 | 2010-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7358121B2 (en) | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
JP4546021B2 (ja) * | 2002-10-02 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型電界効果型トランジスタ及び半導体装置 |
US6706571B1 (en) | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
US7176522B2 (en) * | 2003-11-25 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having high drive current and method of manufacturing thereof |
KR100513405B1 (ko) | 2003-12-16 | 2005-09-09 | 삼성전자주식회사 | 핀 트랜지스터의 형성 방법 |
US7564105B2 (en) | 2004-04-24 | 2009-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quasi-plannar and FinFET-like transistors on bulk silicon |
US20080121932A1 (en) * | 2006-09-18 | 2008-05-29 | Pushkar Ranade | Active regions with compatible dielectric layers |
US7873322B2 (en) * | 2005-06-14 | 2011-01-18 | Acterna Llc | Ingress susceptibility on return path |
US7508031B2 (en) | 2005-07-01 | 2009-03-24 | Synopsys, Inc. | Enhanced segmented channel MOS transistor with narrowed base regions |
US7807523B2 (en) | 2005-07-01 | 2010-10-05 | Synopsys, Inc. | Sequential selective epitaxial growth |
US7265008B2 (en) | 2005-07-01 | 2007-09-04 | Synopsys, Inc. | Method of IC production using corrugated substrate |
US7190050B2 (en) | 2005-07-01 | 2007-03-13 | Synopsys, Inc. | Integrated circuit on corrugated substrate |
US7247887B2 (en) | 2005-07-01 | 2007-07-24 | Synopsys, Inc. | Segmented channel MOS transistor |
US8466490B2 (en) | 2005-07-01 | 2013-06-18 | Synopsys, Inc. | Enhanced segmented channel MOS transistor with multi layer regions |
US7605449B2 (en) | 2005-07-01 | 2009-10-20 | Synopsys, Inc. | Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material |
US7531423B2 (en) | 2005-12-22 | 2009-05-12 | International Business Machines Corporation | Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same |
US7525160B2 (en) * | 2005-12-27 | 2009-04-28 | Intel Corporation | Multigate device with recessed strain regions |
US7435639B2 (en) * | 2006-05-31 | 2008-10-14 | Freescale Semiconductor, Inc. | Dual surface SOI by lateral epitaxial overgrowth |
KR100751803B1 (ko) * | 2006-08-22 | 2007-08-23 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
US7939862B2 (en) | 2007-05-30 | 2011-05-10 | Synopsys, Inc. | Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers |
US8012817B2 (en) * | 2008-09-26 | 2011-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor performance improving method with metal gate |
-
2010
- 2010-03-09 US US12/720,476 patent/US8278179B2/en active Active
- 2010-07-06 CN CN201010224425.2A patent/CN102194697B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6372589B1 (en) * | 2000-04-19 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer |
US7268024B2 (en) * | 2003-04-30 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US6958512B1 (en) * | 2004-02-03 | 2005-10-25 | Advanced Micro Devices, Inc. | Non-volatile memory device |
US7667271B2 (en) * | 2007-04-27 | 2010-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field-effect transistors |
Also Published As
Publication number | Publication date |
---|---|
US20110223736A1 (en) | 2011-09-15 |
US8278179B2 (en) | 2012-10-02 |
CN102194697A (zh) | 2011-09-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102194697B (zh) | 半导体结构的形成方法 | |
US10510884B2 (en) | Method for fabricating a semiconductor device | |
US9219152B2 (en) | Semiconductor device with a buried stressor | |
US7605407B2 (en) | Composite stressors with variable element atomic concentrations in MOS devices | |
TWI545761B (zh) | 半導體元件與其形成方法及p型金氧半電晶體 | |
US8106456B2 (en) | SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics | |
US8802533B1 (en) | Semiconductor device and method of manufacturing the same | |
US8502301B2 (en) | Semiconductor device and method for fabricating the same | |
US7045432B2 (en) | Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) | |
US7700452B2 (en) | Strained channel transistor | |
US7504292B2 (en) | Short channel effect engineering in MOS device using epitaxially carbon-doped silicon | |
US7772676B2 (en) | Strained semiconductor device and method of making same | |
JP5559547B2 (ja) | 半導体デバイスを作る方法 | |
US9660035B2 (en) | Semiconductor device including superlattice SiGe/Si fin structure | |
US9240454B1 (en) | Integrated circuit including a liner silicide with low contact resistance | |
US20160322264A1 (en) | Fin field effect transistor including a strained epitaxial semiconductor shell | |
US20190035892A1 (en) | Semiconductor structure and fabrication method thereof | |
US9673295B2 (en) | Contact resistance optimization via EPI growth engineering | |
US9437694B1 (en) | Transistor with a low-k sidewall spacer and method of making same | |
US10763328B2 (en) | Epitaxial semiconductor material grown with enhanced local isotropy | |
US20110306170A1 (en) | Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process | |
JP2007227721A (ja) | 半導体装置およびその製造方法 | |
US8928047B2 (en) | MOSFET with source side only stress | |
CN103594420B (zh) | 半导体器件制造方法 | |
US9608064B2 (en) | MOSFET structure and method for manufacturing same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |