CN1020991C - 半导体器件的隔离方法 - Google Patents
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Abstract
半导体器件隔离法包括:形成多层结构;刻出有源区隔离区;形成沟道阻挡区;除去氮化层上的多层结构形成覆盖氧化层;除去氮化层多晶硅层上的多层结构形成隔离层,并在侧壁形成分隔层;形成控制极氧化层和控制极;形成第二导电扩散区。形成隔离层采用CVD和光刻法,不致因应力产生鸟嘴现象和位错。分隔层防止沟道阻挡区与离子注入杂质形成的扩散区接触。本发明的隔离极限达正微米范围,避免沟道狭窄效应,提高击穿电压。
Description
本发明涉及半导体器件的一种隔离方法,这种方法通过避免鸟嘴现象的形成能将隔离区减小到最小程度。
近来,由于半导体器件趋向于高集成度的方向发展,对各毗邻有源区起绝缘作用的隔离区应随芯片尺寸的减小成比例地缩小。尤其是,隔离区的大小是确定存储器件尺寸的一个主要因素,因而迄今对如何减小隔离区开展了许多研究工作。
通常,这类隔离方法采用硅局部氧化法(LOCOS)、沟道屏蔽和场屏蔽法等;其中LOCOS法广泛用以在硅衬底的表面上形成氧化层和氮化层之后,通过高温氧化形成隔离区,然后依次从隔离区除去氮化层。
但在隔离狭窄的有源区时就有问题,这是由于高温氧化过程中从隔离区延伸到有源区中的鸟嘴现象引起的。此外氧化过程中的应力还会引起位错,从而导致以后P-N结的漏泄电流。
因此LOCOS法不适宜隔离亚微米器件。因而历来对这类亚微米器件都建议采用沟道屏蔽法和场屏蔽法。沟道屏蔽法能完美地隔离亚微米器件。可是还存在诸如结和晶体管的特性变坏等之类的这种问题。为消除形成沟道过程中蚀刻衬底所产生的结晶缺陷,还需要特殊的设备和技术。
另一方面,场屏蔽隔离在互连各元件时很费事,因为要往场极板上加偏压。此外还要适当消除场极板与其它电极之间的漏泄电流。
综上所述,可见要有效地进行隔离是很困难的。为避免上述问题而提出的各种方法因特别的工艺和设备而不适用于实际产品。
本发明的目的是提供一种不会产生鸟嘴现象的半导体器件隔离方法。
本发明的另一个目的是提供一种用传统工艺能形成亚微米隔离区而不致使器件的特性变坏的半导体器件隔离方法。
本发明提供的半导体器件的隔离方法包括下列步骤:形成多层结构,它包括在第一导电半导体衬底上生长氧化物层之后,形成至少一层多晶硅层和接着是一层氮化物层;从多层结构(不包括多晶硅层)中除去预定的各部分,由此刻划出有源区和隔离区;以离子注入方式在衬底的整个表面上注入第一导电杂质,以便在隔离区形成沟道阻挡区;除去氮化物层上的多层结构,然后将预定厚度的多晶硅层氧化,形成覆盖氧化物层;除去隔离区上的氮化物层和多晶硅层,然后除去覆盖氧化物层和有源区上的氧化物层,以此来形成隔离层;在结构的整个表面淀积氧化层,并再次将其在各向异性地加以蚀刻,以此在隔离区侧壁形成分隔层;在有源区的衬底上形成控制极氧化物层;在控制极氧化物层上形成控制极电极;然后在各控制极电极底下的沟道区两侧分别形成第二导电扩散区。
从下面结合附图对本发明的一些最佳实施例的说明中可以更清楚地了解本发明的上述和其它目的、特点和优点。附图中:
图1(A)-(D)是说明本发明半导体器件隔离方法的各制造工序的剖面示意图;
图2则是图1(D)所示的控制电极的剖面示意图。
现在参看附图更详细地说明本发明的内容。
图1(A)-(D)示出了本发明半导体器件隔离方法的一个实施例。如图1(A)所示,用一般化学汽相淀积法(CVD)依次在P型硅衬底上形成多层结构。多层结构由3000~4000埃的氧化物层3、1000~2000埃的多晶硅层5、1000~2000埃的氮化物层7和3000~4000埃的氧化物层9构成。
隔离区是用一般光刻工艺从氮化物层7和氧化物层9除去预定的部分刻划出来的。隔离区可刻划到亚微米级的范围,即小到光刻工艺的极限值,其余未除去的氮化物层7和氧化物层9部分就成了有源区。
参看图1(B),沟道阻挡区11是通过在200千电子伏特下注入1×1012~1×1013/厘米2剂量的P型杂质离子在衬底表面上形成的,此时有源区上的氧化物层9系用作杂质阻挡层。接着,借助湿法腐蚀除去有源区上的氧化物层9。500~1000埃厚的覆盖氧化物层13是通过使暴露着的隔离区上的多晶硅层5热氧化形成的,此时有源区上的氮化物层7用作氧化阻挡层。多晶硅层5被氧化到预定的厚度。下一步工序是借助于湿法腐蚀除去氮化物层7,并用常规方法除去有源区的多晶硅,此时复盖氧化物层13用作腐蚀阻挡层。
参看图1(C),结构表面上的氧化物层3和13是用RIE法同时除去的。在蚀刻隔离区上的氧化物层3和有源区上的覆盖氧化物层13的过程中,多晶硅层5形成作为保护层的隔离氧化物层15。经蚀刻剩下的氧化物层用作隔离层15。在上述工艺中,由于隔离层15不是借热氧化形成的,因而可以消除因局部氧化物热生长而产生的鸟嘴现象和位错。此外还抑制了在沟道阻挡区离子注入的杂质扩散入衬底1。
参看图1(D),分隔层17是在结构整个表面上淀积氧化层之后用反复腐蚀(etching back)法在隔离层15的侧壁上形成的。隔离层15上的多晶硅层5是在反复腐蚀过程和以后的氧化过程中除去的。接着,在衬底1暴露的表面上形成控制极氧化物层19,并在控制极氧化物层19预定的位置上形成控制极电极21。扩散区23是以离子注入方式注入象磷或砷之类n型杂质形成的,用作源极和漏极。
控制极电极21底下的衬底1表面用作沟道区25,供电连接各扩散区之用。扩散区23与沟道阻挡区11不重叠,从而提高了击穿电压。
图2是图1(D)的纵剖图,它示出了图1(D)的控制极电极21。与图
1(D)中同样的部分用同样的编号表示。图2中,沟道狭窄效应是这样避免的,因为隔离层不是通过热氧化形成的,使得用作为沟道阻挡区的区域11中注入的杂质不致扩散入有源区,从而防止沟道区25变窄。多层结构由氮化物层和氧化物层构成,但也可以采用其它组成方式而仍在本发明的真实范围内,只要其中先后包括有氮化物层和氧化物层即可。
如到此为止所谈到的那样,隔离层仅仅是用CVD(化学汽相淀积)法和光刻蚀法形成,这样可以避免应力所引起的鸟嘴现象和位错,而且用作沟道阻挡区的离子注入区的杂质不致扩散入有源区中。此外,在隔离层侧壁形成的分隔层还可以防止注入离子所形成的扩散区与沟道阻挡区接触。因为在形成隔离层的过程中不采用热氧化,因此,本发明具有很大的优点。
按照本发明,不仅可以通过防止鸟嘴现象的形成将隔离极限扩大到亚微米范围,而且还可以避免因应力引起的位错而产生漏泄电流。此外由于离子注入区的杂质不会扩散入有源区,因而可以有效地防止沟道狭窄效应。于是由于分隔层避免了扩散区与离子注入区之间的接触,因而可以提高击穿电压。
本发明决不受上述实施例的限制。显然,熟悉本技术领域的人士参考本发明的说明书是可以对本发明上述公开的和其它实施例进行种种修改的。由于这些修改或实施例都属于本发明的精神范围,因而本说明书所附的权利要求书理所当然地包括任何这类修改或实施例。
Claims (3)
1、一种制造具有隔离区的半导体器件的方法,其特征在于,它包括下列步骤:
在第一导电型的半导体衬底上形成第一氧化层;
形成一多层结构,它包括一层覆盖所说第一氧化层的多晶硅层,一层覆盖所说多晶硅层的氮化物层,和一层阻挡杂质离子的氧化物层;
除去一部分多层结构中所说氮化物层上的各层以露出一部分所说多晶硅层,该露出的部分所说多晶硅层覆盖在所说衬底的隔离区上,而一部分未露出的所说多晶硅层覆盖在所说衬底的有源区;
通过露出的所说多晶硅层出注入适当剂量的杂质离子以在衬底形成沟道阻挡区;
氧化该露出的所说多晶硅层,以提供一层覆盖在所说隔离区上的覆盖氧化物层;
从所说衬底的有源区上除去所说多层结构,以形成一已刻图的包括所说第一氧化层的隔离层,和一部分覆盖在所说有源区上的所说第一氧化层;
在该衬底的整个表面上淀积一第二氧化层,并选择性地刻蚀所说第二氧化层,以在所说隔离层的侧壁处形成分隔层;
在所说衬底的有源区上形成栅氧化层;
在所说栅氧化层上形成栅电极;以及
在所说衬底里的下伏栅电极形成第二导电类型区。
2、根据权利要求1所述的方法,其特征在于,它包括氧化所说露出的多晶硅层,该氧化层的厚度小于所说多晶硅层的总厚度,以便在覆盖在所说隔离区上留下一部分所说多晶硅层。
3、根据权利要求2所述的方法,其特征在于,它包括,使用一种反应离子刻蚀法以除去覆盖所说有源区的那部分所说第一氧化层,但不除去覆盖在所说隔离区上的所说多晶硅层的留下部分。
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US5879994A (en) * | 1997-04-15 | 1999-03-09 | National Semiconductor Corporation | Self-aligned method of fabricating terrace gate DMOS transistor |
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JPS5679446A (en) * | 1979-12-04 | 1981-06-30 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Production of semiconductor device |
DE3176909D1 (en) * | 1980-03-06 | 1988-11-17 | Toshiba Kk | Semiconductor device using component insulation and method of manufacturing the same |
JPS56158447A (en) * | 1980-05-12 | 1981-12-07 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit and its manufacture |
JPS6211273A (ja) * | 1985-07-08 | 1987-01-20 | Nec Corp | Mos集積回路装置の製造方法 |
US4762805A (en) * | 1985-12-17 | 1988-08-09 | Advanced Micro Devices, Inc. | Nitride-less process for VLSI circuit device isolation |
US4818235A (en) * | 1987-02-10 | 1989-04-04 | Industry Technology Research Institute | Isolation structures for integrated circuits |
DD268336A1 (de) * | 1987-12-30 | 1989-05-24 | Dresden Forschzentr Mikroelek | Verfahren zur herstellung von isolationsgebieten |
KR930000197B1 (ko) * | 1990-03-06 | 1993-01-11 | 현대전자산업 주식회사 | 필드산화막 형성방법 |
-
1990
- 1990-08-18 KR KR1019900012905A patent/KR930004125B1/ko not_active IP Right Cessation
- 1990-11-13 US US07/612,559 patent/US5141884A/en not_active Expired - Lifetime
- 1990-11-16 NL NL9002505A patent/NL194107C/nl not_active IP Right Cessation
- 1990-11-19 RU SU904831797A patent/RU2053586C1/ru not_active IP Right Cessation
- 1990-11-19 JP JP2311697A patent/JPH0783049B2/ja not_active Expired - Fee Related
- 1990-11-20 IT IT02211090A patent/IT1243916B/it active IP Right Grant
- 1990-11-20 FR FR9014436A patent/FR2665981B1/fr not_active Expired - Fee Related
- 1990-11-20 DE DE4036999A patent/DE4036999A1/de active Granted
- 1990-11-20 GB GB9025253A patent/GB2247106B/en not_active Expired - Fee Related
- 1990-11-20 CN CN90109410A patent/CN1020991C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0783049B2 (ja) | 1995-09-06 |
US5141884A (en) | 1992-08-25 |
GB2247106B (en) | 1995-01-18 |
KR920005296A (ko) | 1992-03-28 |
GB9025253D0 (en) | 1991-01-02 |
IT9022110A0 (it) | 1990-11-20 |
GB2247106A (en) | 1992-02-19 |
NL9002505A (nl) | 1992-03-16 |
RU2053586C1 (ru) | 1996-01-27 |
NL194107C (nl) | 2001-06-05 |
IT9022110A1 (it) | 1992-05-20 |
CN1059424A (zh) | 1992-03-11 |
DE4036999C2 (zh) | 1993-07-15 |
FR2665981A1 (fr) | 1992-02-21 |
DE4036999A1 (de) | 1992-02-20 |
FR2665981B1 (fr) | 1995-12-22 |
NL194107B (nl) | 2001-02-01 |
JPH04103127A (ja) | 1992-04-06 |
IT1243916B (it) | 1994-06-28 |
KR930004125B1 (ko) | 1993-05-20 |
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Granted publication date: 19930526 Termination date: 20091221 |