CN102084029A - 用于钝化硅晶片的沉积方法 - Google Patents

用于钝化硅晶片的沉积方法 Download PDF

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CN102084029A
CN102084029A CN2009801256629A CN200980125662A CN102084029A CN 102084029 A CN102084029 A CN 102084029A CN 2009801256629 A CN2009801256629 A CN 2009801256629A CN 200980125662 A CN200980125662 A CN 200980125662A CN 102084029 A CN102084029 A CN 102084029A
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substrate support
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CN102084029B (zh
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K·阿库拉蒂
M·库诺
R·杰维斯
A·齐默曼
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Hitachi Energy Co ltd
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Abstract

衬底(4)装配到衬底载板(3)的高架衬底支撑件(31)上。具有衬底的衬底载板然后放置于等离子体反应器(8)中。由于高架衬底支撑件，衬底的两个相反侧暴露于等离子体(6)并且因此涂覆有电钝化层(7)。

Description

用于钝化硅晶片的沉积方法
技术领域
这里公开的主题内容主要地涉及高电压高功率半导体技术领域，并且具体地涉及一种用于在用于功率半导体的半导体晶片上单步双面沉积电钝化层的方法和装置。
背景技术
一般而言，双极功率半导体如二极管、闸流管、GTO和GCT由硅晶片制成。在这些硅晶片已经经历不同注入、扩散、光刻和金属化工艺之后，将它们切割成圆盘并且在高电压阻挡pn结上研磨负或者正斜面。这些斜面通常需要由电钝化层保护。目前使用的现有技术的钝化材料之一是通常在平行板等离子体反应器内在等离子体增强化学气相沉积(PECVD)中沉积、但是一般可以在其它几何形状的PECVD反应器中或者通过离子束、溅射、阴极电弧、脉冲激光沉积或者低压CVD来沉积的非晶态氢化碳(a-C:H，也称为钻石状碳DLC)。
在图1中给出一般PECVD工艺的简化画面。硅晶片经由衬底载板与反应室内的第二下电极接触。烃前体气体(例如甲烷、乙炔)经过第一上电极中的开孔进入等离子体反应器的反应室、由射频电离并且形成块等离子体。边缘等离子体层是如下空间，其中等离子体离子由于在两个电极之间施加的直流偏置电压而获得向衬底和衬底载板的方向上加速。
常用工艺是如图1中所示在铝衬底载板上的凹陷内放置硅晶片。这一衬底载板不仅充当用于硅晶片(衬底)的保持器，而且它建立盘与反应室中的有源冷却的第二(下)电极的热接触和电接触。在硅晶片上的与第一(上)电极相向的斜面暴露于a-C:H沉积等离子体，而硅晶片的其余上表面由铝阴影掩模(shadow mask)覆盖。为了避免电性质无法令人满意的钝化层，硅晶片在沉积工艺期间的有源冷却是必需的。在J.Robertson的“Diamond-like amorphous carbon”中(Materials Science and Engineering：R：Report 37(2002)129)报导了a-C:H的热降解。
具有两个高电压阻挡pn结(例如闸流管)的硅晶片可以具有在它的相反侧中的各侧上研磨的一个负斜面。利用上述常用工艺，仅上斜面在运行的单个工艺中涂覆有a-C:H。因而需要手工翻动硅晶片并运行第二a-C:H沉积工艺。由于在第二工艺步骤中涂覆的斜面在第一工艺步骤期间是在未保护和很敏感的状态中倒置地放入凹陷中，所以所述斜面受污染的风险高，从而导致阻挡收益降低。
发明内容
本发明的目的在于揭示一种用于在晶片的两侧上沉积双面沉积为电钝化层(比如匀质a-C:H层)的单步方法。本发明的又一目的在于改进现有沉积装置以允许用于在半导体晶片上沉积电钝化层的单步工艺。
本发明方法基于与改进的衬底保持器装置组合的等离子体增强化学气相沉积(PECVD)。具体而言，本发明方法包括以下步骤：在衬底载板的高架衬底支撑件上装配硅晶片；以及将具有硅晶片的衬底载板放置在等离子体反应器中。形成衬底支撑件使得晶片放置于衬底支撑件上而仅它的第二主侧的中心区与衬底支撑件接触。由于这样的高架衬底支撑件，硅晶片的两个相反侧暴露于等离子体并且因此涂覆有电钝化层。通过电钝化层，晶片在电钝化层的区域中被电去激活(本发明的钝化层并非完全为电去激活，而是它部分地导电)。
本发明方法比先前方法有利，因为a-C:H层在一个工艺步骤中沉积于晶片(例如硅晶片)的两侧上(在一个硅晶片的两侧上或者在背对背堆叠的两个硅晶片上)。晶片包括：第一主侧，在第一主侧的边界上具有第一斜面；以及第二主侧，具有中心区和在第二主侧的包围中心区的边界上的第二斜面，第二主侧与第一主侧相反布置。晶片装配于衬底载板的衬底支撑件上，该衬底支撑件被形成为使得晶片放置于衬底支撑件上而仅它的第二主侧的中心区与衬底支撑件接触。然后衬底载板与晶片一起放置于等离子体反应器的反应室中。由此，第一斜面和第二斜面同时暴露于等离子体以便产生电钝化层。在一个示例实施例中，非晶态氢化碳用作等离子体以在晶片上形成电钝化层。
为了避免可能由于增加在承载于衬底载板的高架衬底支撑件上的硅晶片与有源冷却的下电极之间的距离而出现的传热退化，本发明也涉及所述新颖衬底载板设计与改进的硅晶片冷却机制的组合。这允许对于沉积工艺而言关键的合理散热，因为在近似200℃以上的衬底温度可能沉积电性质无法令人满意的更多石墨状碳层。
代替凹陷，所述本发明强调基座状衬底载板的重要性。因此硅晶片的两侧均暴露于等离子体。然而匀质沉积尤其对于与下电极相邻的斜面而言至关重要。由于均匀等离子体流速和匀质电场对于沉积均匀a-C:H层而言都是必需的，所以高架衬底支撑件的蘑菇形(例如凹形、颠倒截锥形等)设计往往比纯圆柱形设计有利。
在又一实施例中，本发明也涉及直流偏置电压的经调节的沉积工艺参数。
附图说明
通过参照结合以下附图的下文具体描述可以获得对本发明的更完整理解，其中：
图1示意地示出了在现有技术的单面沉积工艺中在平行板反应器内具有硅晶片的组件；
图2示意地示出了在平行板反应器内在本发明的高架衬底支撑件上具有硅晶片的组件；
图3具体示出了具有本发明的高架衬底支撑件的第一实施例(圆柱形)的图2的组件；
图4具体示出了具有本发明的高架衬底支撑件的第二实施例(截锥形)的图2的组件；以及
图5示意地示出了在平行板反应器内在本发明的高架衬底支撑件上具有堆叠硅晶片的组件。
具体实施方式
图1提供在现有技术的PECVD工艺中使用的平行板反应器的示意图，该反应器具有成对平行板电极1和2、反应室8、块等离子体6、边缘等离子体层7、硅晶片4、阴影掩模5和具有凹陷33的衬底载板3。电子能量(等离子体)用作激活方法以在硅晶片上实现a-C:H沉积。烃前体气体(例如甲烷、乙炔)经过上电极1中的开孔11进入反应室8。它由射频电离并且形成块等离子体6。边缘等离子体层7是反应室8中的如下空间，其中等离子体由于已经在两个电极1与2之间施加的直流偏置电压而获得向硅晶片或者衬底载板加速。作为衬底的硅晶片4放入衬底载板3上的凹陷33内。这一衬底载板3不仅充当机械衬底保持器，而且它也在硅晶片与等离子体反应器的反应室8中的下电极2之间建立热接触和电接触。在硅晶片上的待钝化的一个斜面面向上电极1。这一斜面暴露于a-C:H沉积等离子体6和/或7。在硅晶片的顶表面上的未受到钝化的区域由阴影掩模5覆盖。在当前工艺中，仅上斜面在运行的单个工艺中涂覆有a-C:H。因而对于具有两个高电压阻挡pn结的硅晶片(该硅晶片在各相反侧上具有一个斜面(即闸流管))，需要手工翻动硅晶片并运行第二a-C:H沉积工艺。如上文提到的那样，在第二工艺步骤中涂覆的斜面在第一工艺步骤期间倒置地(在未保护并且因此很敏感的状态下)放入凹陷33中，因此受污染的风险高，从而导致阻挡收益降低。
图2提供在本发明的单步双面PECVD工艺中使用的平行板反应器的改进版的示意图。该装置与图1中所用装置不同之处在于，使用新开发的衬底载板3。此板优选地由电和热传导材料如铝或者另一金属制成。为了克服仅单面a-C:H沉积的限制，硅晶片(衬底)不再放置于衬底载板3中的凹陷内。取而代之，硅晶片放置于称为高架衬底支撑件31的“蘑菇状”或者“底座状”突出物顶上。晶片放置于具有如下设计的接触区的衬底载板3上，该接触区使得晶片的第二主侧与衬底载板31接触并且第一斜面和第二斜面未由衬底载板31覆盖或者包围或者封闭。
所述高架衬底支撑件31布置于衬底载板3顶上、集成于衬底载板3中或者可选地作为单独部分。这一衬底载板不仅充当用于硅晶片的机械衬底保持器，而且它还在硅晶片与反应室8中的下电极2之间建立热接触和电接触。通过升高硅晶片的位置，同样由经过平行板电极1流入反应室8中的前体气体产生的等离子体流不再限于硅晶片衬底的上斜面41。a-C:H沉积同时出现在硅晶片的上斜面41和下斜面42上。硅晶片的不可涂覆的上表面区同样由阴影掩模5覆盖。为了使硅晶片的温度间接地限于近似200℃以下的水平，底部电极2例如由在约15℃至20℃的温度运行的水冷却设备22有源地冷却。
图3提供晶片(例如硅晶片)在上面的衬底载板3的本发明“底座状”高架衬底支撑件31的第一实施例的具体视图。来自块等离子体6的离子在电连接到底部电极2的表面附近在边缘等离子体层7中获得向硅晶片4加速。在不同区域A和B在硅晶片4上的匀质a-C:H沉积尤其对于硅晶片上的下斜面而言至关重要。原因在于均匀分布的等离子体流速和匀质电场是均匀a-C:H层的沉积所必需的。然而除了极小的等离子体边缘层厚度之外，等离子体通量密度以及加速电场可能对于区域A和B而言不同，从而导致在这些区域中的略微不匀质的a-C:H沉积。在某一程度上，工艺参数的略微调节可以补偿这样的不匀质，因为等离子体边缘层厚度随着直流偏置电压的平方根成比例改变，该偏置电压可以减少至近似500伏的最小值。这一最小直流偏置电压对于一些反应器而言可能变化，因为它依赖于许多不同参数。
图4提供本发明的衬底载板3、具体为高架衬底支撑件31的第二实施例的具体视图。取代仅使用圆柱形突出物作为衬底载板3的高架衬底支撑件31，在基部的附加旋转切割造成高架衬底支撑件31的凹形横截面。关于这一类几何形状轮廓，这些高架衬底支撑件在这里称为“蘑菇状”。可能的几何形状切割的蘑菇形轮廓并不限于直线。在原理上，可以使用高架衬底支撑件31的任何几何形状轮廓，例如凹形、颠倒截锥形等，只要等离子体流速充分地高并且在硅晶片的底部斜面上的电/磁场使得提供尽可能匀质的沉积速率。在这些情况下，有助于在不同区域A和B在硅晶片4上的匀质a-C:H沉积。工艺参数的略微调节同样可以补偿其余可能的不匀质，因为等离子体边缘层厚度随着直流偏置电压的平方根成比例改变，该偏置电压可以减少至近似500伏的最小值。硅晶片的改进和更直接冷却可选地由冷却设备32的有源冷却实现，该冷却设备布置于衬底载板3中或与之相邻，或者布置于衬底载板的高架衬底支撑件31中或与之相邻。作为冷却设备，可以使用例如在15℃至20℃的温度操作的水冷却。与硅晶片和/或衬底载板的可选预先冷却过程组合的这一优化原位冷却策略实现硅晶片的在200℃以下的最大工艺温度。为了进一步降低硅晶片在沉积工艺期间的温度，冷却装置可选地布置于覆盖硅晶片上表面的阴影掩模中。如上文提到的那样，令人满意的散热对于沉积工艺而言是关键的，因为在200℃以上的硅晶片温度可能导致沉积电性质无法令人满意的石墨状碳层。
为了恰当地对准(即同心地对准)硅晶片4和衬底载板3的高架衬底支撑件31，可以在向等离子体反应器的反应室中加载组件之前使用对准或者定心装置。
可选地，如图5中示意地所示，附加硅晶片4’可以堆叠于在高架衬底支撑件31上承载的一个硅晶片4顶上。在堆叠中的相邻硅晶片4与4’之间布置高架衬底支撑件31’以便允许在相邻硅晶片上的匀质a-C:H沉积。可选地，可以省略这一附加高架衬底支撑件以允许两个硅晶片的背对背堆叠，而各硅晶片仅有一个高电压阻挡pn结(比如二极管、GTO和GCT)并且因此仅有一个斜面待钝化。
可选地，冷却装置可以布置于在堆叠上面布置的阴影掩模5和/或附加高架衬底支撑件31’内。可选地，有布置于附加高架衬底支撑件31’与电连接到下电极2的一个或者多个或者所有部件(即高架衬底支撑件31、衬底载板3或者下电极2本身)之间的导电连接34。
附图标号列表
1、2 电极
22 冷却器
3 衬底载板
31、31’ 高架衬底支撑件
32 冷却器
33 凹陷
34 导电连接
4、4’ Si盘/衬底
41 上斜面
42 下斜面
5 阴影掩模
6 块等离子体
7 边缘等离子体层
8 等离子体反应器的反应室

Claims (16)

1.一种用于向硅晶片(4)上施加非晶态氢化碳的双面沉积(7)的方法，所述晶片(4)包括第一主侧和第二主侧，所述第一主侧具有在所述第一主侧的边界上的第一斜面，所述第二主侧具有中心区和在所述第二主侧的包围所述中心区的边界上的第二斜面，所述第二主侧与所述第一主侧相反布置，所述方法包括以下步骤：在衬底载板(3)的衬底支撑件(31)上装配所述晶片(4)，所述衬底支撑件(31)被形成为使得所述晶片(4)放置于所述衬底支撑件(31)上而仅它的所述第二主侧的中心区与所述衬底支撑件(31)接触；并且在等离子体反应器的反应室(8)中放置具有所述晶片(4)的所述衬底载板，其中所述第一斜面和所述第二斜面同时暴露于等离子体(6)以便产生所述沉积(7)，其中非晶态氢化碳用作所述等离子体。
2.如权利要求1所述的方法，其中在所述晶片内的温度在所述沉积工艺期间保持于200℃以下。
3.如权利要求1所述的方法，其中所述晶片(4)在装配于所述衬底载板(3)上之前被冷却，或者其中所述衬底载板(3)在放置于所述反应室(8)之前被冷却，或者其中所述晶片(4)和所述衬底载板(3)被放置于所述反应室(8)中。
4.如权利要求1所述的方法，其中所述反应室(8)包括两个平行板电极(1，2)，并且其中所述晶片(4)在所述沉积工艺期间由布置于所述反应室(8)的所述电极(2)中的冷却装置(22)有源地冷却或者其中所述晶片(4)在所述沉积工艺期间由布置于所述衬底载板(3)或者所述衬底载板(3)的所述衬底支撑件(31)中的冷却装置(32)有源地冷却。
5.一种用于承载硅晶片(4)的衬底载板(3)，所述硅晶片(4)用于在沉积工艺期间制造半导体器件，所述沉积工艺用于在等离子体反应器室(8)中在所述晶片(4)的表面上沉积双面沉积(7)，所述晶片(4)包括第一主侧和第二主侧，所述第一主侧具有在所述第一主侧的边界上的第一斜面，所述第二主侧具有中心区和在所述第二主侧的包围所述中心区的边界上的第二斜面，所述第二主侧与所述第一主侧相反布置，其特征在于所述衬底载板(3)包括用于承载所述晶片(4)的衬底支撑件(31)，所述衬底支撑件(31)被形成为使得所述晶片(4)可以放置于所述衬底支撑件(31)上而仅它的所述第二主侧的中心区与所述衬底支撑件(31)接触。
6.如权利要求5所述的衬底载板，包括圆柱形衬底支撑件(31)，或者包括如下的衬底支撑件(31)，所述衬底支撑件在表面平面中具有所述晶片的所述中心区可以放置于其上的表面区并且所述衬底载板(3)具有随着与所述表面平面的距离而减少至少直至第一深度的横截面。
7.如权利要求5或者6之一所述的衬底载板，包括各自用于承载晶片(4)的若干衬底支撑件(31)。
8.如权利要求5至7之一所述的衬底载板，所述衬底支撑件(31)为附着到所述衬底载板(3)的单独部分。
9.如权利要求5至8之一所述的衬底载板，其中所述衬底载板(3)包括第一晶片可以承载于其上的衬底支撑件(31)，并且至少一个另外的晶片可以堆叠于所述第一晶片上。
10.如权利要求9所述的衬底载板，其中附加衬底支撑件(31’)可以布置于所述堆叠中的相邻晶片(4，4’)之间，来自各对相邻晶片的所述晶片被附加衬底支撑件(31’)相互分离。
11.如权利要求10所述的衬底载板，其中冷却装置(32)布置于所述附加衬底支撑件(31’)中。
12.如权利要求10或者11之一所述的衬底载板，其中导电连接(34)布置于所述附加衬底支撑件(31’)与所述衬底支撑件(31)和/或所述衬底载板(3)和/或承载电极(2)的所述衬底载板(3)之间。
13.一种用于在硅晶片(4)上沉积双面沉积(7)的沉积装置，包括在等离子体反应器的反应室(8)内的两个平行板电极(1，2)、根据权利要求3至6中的任一权利要求所述的衬底载板(3)，其中至少一个晶片(4)放置于所述衬底支撑件(31)上，所述衬底载板(3)可以放置于所述电极之一(2)上。
14.如权利要求13所述的沉积装置，包括用于在所述沉积工艺期间冷却所述晶片(4)的冷却装置(22，32)。
15.如权利要求14所述的沉积装置，所述冷却装置(22)布置于承载电极(2)的所述衬底载板(3)中或者与之相邻。
16.如权利要求14或者15之一所述的沉积装置，其中所述冷却装置(32)布置于所述衬底载板(3)中或者所述衬底载板(3)的所述衬底支撑件(31)中，或者其中所述冷却装置(32)布置于在与所述两个板电极中的另一个电极(1)相向的表面上覆盖所述晶片(4)的阴影掩模(5)中。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108475665A (zh) * 2015-11-05 2018-08-31 Abb瑞士股份有限公司 功率半导体器件和用于生产功率半导体器件的方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016080235A1 (ja) * 2014-11-17 2016-05-26 シャープ株式会社 蒸着装置、蒸着方法、及び、有機エレクトロルミネッセンス素子の製造方法
RU2607110C1 (ru) * 2015-07-09 2017-01-10 Общество с ограниченной ответственностью "СВД.Спарк" Держатель подложки
RU2614080C1 (ru) * 2015-12-16 2017-03-22 Общество с ограниченной ответственностью "НТЦ тонкопленочных технологий в энергетике при ФТИ им. А.Ф. Иоффе", ООО "НТЦ ТПТ" Пассивация поверхности кремниевых пластин методом магнетронного распыления

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US623405A (en) * 1899-04-18 Vehicle-wheel
JPH043926A (ja) * 1990-04-20 1992-01-08 Sony Corp 半導体装置の製造方法
JPH06283500A (ja) * 1993-03-30 1994-10-07 Hitachi Ltd 半導体製造装置および半導体装置
JPH06333916A (ja) * 1993-05-21 1994-12-02 Fuji Electric Co Ltd 非晶質カーボン膜の硬化方法
US5384008A (en) * 1993-06-18 1995-01-24 Applied Materials, Inc. Process and apparatus for full wafer deposition
US5822171A (en) 1994-02-22 1998-10-13 Applied Materials, Inc. Electrostatic chuck with improved erosion resistance
US5883778A (en) * 1994-02-28 1999-03-16 Applied Materials, Inc. Electrostatic chuck with fluid flow regulator
JPH08209352A (ja) * 1995-02-06 1996-08-13 Hitachi Ltd プラズマ処理装置および方法
US6641673B2 (en) * 2000-12-20 2003-11-04 General Electric Company Fluid injector for and method of prolonged delivery and distribution of reagents into plasma
NL1017849C2 (nl) * 2001-04-16 2002-10-30 Univ Eindhoven Tech Werkwijze en inrichting voor het deponeren van een althans ten dele kristallijne siliciumlaag op een substraat.
JP4714384B2 (ja) * 2001-08-23 2011-06-29 株式会社アルバック ウエハエッジ部分の処理方法及びプラズマ処理装置
US20030072639A1 (en) * 2001-10-17 2003-04-17 Applied Materials, Inc. Substrate support
US20040112544A1 (en) * 2002-12-16 2004-06-17 Hongwen Yan Magnetic mirror for preventing wafer edge damage during dry etching
US20050284371A1 (en) * 2004-06-29 2005-12-29 Mcfadden Robert S Deposition apparatus for providing uniform low-k dielectric
US20070068623A1 (en) * 2005-09-27 2007-03-29 Yunsang Kim Apparatus for the removal of a set of byproducts from a substrate edge and methods therefor
US7575982B2 (en) * 2006-04-14 2009-08-18 Applied Materials, Inc. Stacked-substrate processes for production of nitride semiconductor structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108475665A (zh) * 2015-11-05 2018-08-31 Abb瑞士股份有限公司 功率半导体器件和用于生产功率半导体器件的方法

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