CN102064189A - Metal-semiconductor electrode structure and preparation method thereof - Google Patents
Metal-semiconductor electrode structure and preparation method thereof Download PDFInfo
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Abstract
The invention relates to a metal-semiconductor electrode structure which comprises a semiconductor layer and a metal electrode, and a graphene layer is further arranged between the semiconductor layer and the metal electrode to reduce the contact resistance between the metal electrode and the semiconductor layer. The metal-semiconductor electrode structure provided by the invention has the advantages of improving the energy band state of metal-semiconductor contact by inserting the graphene layer between the metal and the semiconductor layer, being widely applicable to metals with different work functions and semiconductors with different doping types and doping concentrations, and reducing the contact potential barrier, thereby playing the function of reducing the contact resistance. The metal-semiconductor electrode structure provided by the invention has simple preparation method, stable performance, good repeatability and low cost and plays an important role in realizing micro nano semiconductor electronic devices with high performance and low cost.
Description
Technical field
The present invention relates to semiconductor device and technology field, relate in particular to a kind of metal-semiconductor electrode structure and preparation method thereof.
Background technology
An important process in the semiconductor device research is to utilize metal or alloy to make low-resistance contact electrode.As everyone knows, traditional semiconductor interface touched electrode is made to be needed to handle semiconductor surface through chemical solvent, sputtered metal film then, operation such as anneal again.The natural oxidizing layer of sample surfaces and device technology are polluted contact performance is significantly degenerated.In addition, also there is capture effect in the deep energy level trap to charge carrier.These factors have increased the manufacture difficulty and the contact performance of contact electrode.
Generally be divided into two classes about semi-conductive contact electrode, promptly
nContact electrode on the N-type semiconductor N and
pContact electrode on the N-type semiconductor N.
For
nN-type semiconductor N, with
nMolded breadth bandgap semiconductor gallium nitride (GaN) is an example because its electron affinity is 4.2ev, select for use when therefore making Ohm contact electrode usually work function near the metal of 4.2ev as contact electrode, as indium (In), aluminium (Al), titanium (Ti), tungsten (W) etc.Early stage research is to utilize Ti/Al or the such double-decker of Al/Ti, earlier at GaN film surface plated metal successively, and short annealing under nitrogen atmosphere then.Along with development of technology, on the basis of Ti/Al or Al/Ti structure, improve again, developed as sandwich constructions such as Ti/A1/Ti/Au, Ti/A1/Pt/Au, Ti/A1/Ni/Au.In addition, the narrower epitaxial loayer (InN) of growth one deck band gap in crystal growing process is arranged also, also can reduce contact resistance effectively.
For
pN-type semiconductor N still is example with GaN, need with work function up to the metal of 6.5eV forming low-resistance contact electrode, but the highest barrier height of actual metal surpasses 6eV's, can only select for use high-work-function metals such as Pt, Ni, Au, Pd to constitute combination electrode.For example, in GaN LED and LD device,
pNi/Au commonly used makes contact electrode on the type GaN crystal, and needs short annealing at a certain temperature equally.
At present, though metal (alloy) as the Study of Ohmic Contact of the n N-type semiconductor N of electrode relatively than system, deeply, and contact resistivity can reach 10
-5~ 10
-8Ω cm
-2But preparation technology is still complicated, evaporation multiple layer metal electrode, and technologies such as annealing are difficult to avoid.And for
pN-type semiconductor N, one side can't find the suitable contacting metal of big work function, and
pThe heavy doping difficulty of N-type semiconductor N own makes to prepare reliable, high-quality, low resistance
pThe type contact electrode is still a great challenge.
The stratified material as thin as a wafer that Graphene is made up of carbon atom, the thinnest monoatomic layer that arrives can utilize chemical vapour deposition (CVD), and specified conditions such as mechanical cleavage make, and are a kind of zero band gap, semimetallic two-dimensional material.Carrier moving speed in the Graphene can reach 1/300 of the light velocity, and its electron mobility experiment measuring value surpasses 15000cm
2/ vs(carrier concentration n ≈ 10
13Cm
-2), in 10～100K scope, mobility is almost temperature independent.In addition, the Fermi surface of Graphene can be with discharging and recharging and regulate, and has lower charge carrier injection barrier, the material softness, and thermodynamic stability is strong.These character are to utilize it to form the physical basis of low contact resistance electrode.
Summary of the invention
Technical problem to be solved by this invention is, a kind of metal-semiconductor electrode structure and preparation method thereof is provided, and under the situation that is not changing existing metal material, can obtain the electrode structure of low contact resistance on p type, n type and intrinsic semiconductor.
In order to address the above problem, the invention provides a kind of metal-semiconductor electrode structure, comprise semiconductor layer and metal electrode, it is characterized in that, one graphene layer further is set, to reduce the contact resistance between metal electrode and the semiconductor layer between semiconductor layer and metal electrode.
The present invention further provides a kind of preparation method of metal-semiconductor electrode structure, comprised the steps: to select for use the method for chemical vapour deposition (CVD) on growth substrates, to prepare the graphene film layer; In solution, utilize chemical method corrosion Graphene substrate, the graphene film layer is peeled off from growth substrates; Clean the surface of semiconductor layer.With semiconductor graphene film is picked up from solution, surface tension makes graphene film layer uniform spreading and be adsorbed on the surface of semiconductor layer, thereby forms graphene layer in semiconductor layer surface; Surface at graphene layer forms metal level; Form etching barrier layer at layer on surface of metal; Etching sheet metal and graphene layer to semiconductor layer stops, and forms electrode structure.
The present invention further provides a kind of preparation method of metal-semiconductor electrode structure, comprised the steps: to select for use the method for chemical vapour deposition (CVD) on growth substrates, to prepare the graphene film layer; On the graphene film layer, apply adhesion layer, form the THIN COMPOSITE rete of adhesion layer and Graphene; Utilize chemical method corrosion Graphene substrate in solution, graphene film and adhesion layer are peeled off from growth substrates it are swum on the liquid level; Clean the surface of semiconductor layer; The laminated film lamination of graphene film and adhesion layer is imprinted on the surface of semiconductor layer; Adhesion layer is removed, thereby formed graphene layer in semiconductor layer surface; Surface at graphene layer forms metal level; Form etching barrier layer at layer on surface of metal; Etching sheet metal and graphene layer to semiconductor layer stops, and forms electrode structure.
The present invention further provides a kind of preparation method of metal-semiconductor electrode structure, comprised the steps: to adopt the method for graphite oxidation reduction to prepare the graphene powder material; Clean the surface of semiconductor layer; At the surface applied graphene powder material of semiconductor layer, form graphene layer; Surface at graphene layer forms metal level; Form etching barrier layer at layer on surface of metal; Etching sheet metal and graphene layer to semiconductor layer stops, and forms electrode structure.
The material of described semiconductor layer is selected from a kind of in III-V compounds of group, II-VI compounds of group and IV compounds of group and the element semiconductor.The conduction type of described semiconductor layer is selected from a kind of in N type semiconductor, P type semiconductor and the intrinsic semiconductor.The material of described graphene layer is selected from a kind of in monoatomic layer Graphene and the polyatom layer graphene.From the narration of following principle as can be seen, no matter be the semiconductor layer which kind of material constitutes, no matter be the semiconductor layer of which kind of conduction type also, so long as have typical semiconductor energy band structure, grapheme material just can embody the advantage that reduces contact resistance.And grapheme material is not restricted to monoatomic layer or polyatom layer material yet.
Realization principle of the present invention as shown in Figure 1.Fig. 1 with
nThe type doped semiconductor is an example, compared common metal and Graphene respectively with the heterogeneity that contacts of its formation:
(a) among Fig. 1 and (b) be common metal with semiconductor between contact: (a) for being with schematic diagram before the contact, semiconductor work function W at this moment
sWith metal work function W
mThere is some difference; (b) be
nN-type semiconductor N with can be with schematic diagram after metal directly contacts.Because the semiconductor Fermi surface is higher than the metal Fermi surface, electronic carrier flows to metal from semiconductor and produces the space charge region.Because metal has very high carrier concentration and Parabolic band structure (as shown in the square frame of (a) right side) near Fermi surface, the Fermi surface of metal remains unchanged substantially, and the space charge region concentrates on semiconductor one side, make semiconductor produce crooked being with of near interface, form a higher contact berrier, make that finally both Fermi surfaces are equal.The height qV of this contact berrier
DEqualing the poor of both work functions, is the key factor of decision metal and semiconductor contact resistance.
Compare with The above results, (c) of Fig. 1 with (d) be respectively
nEnergy band diagram before and after N-type semiconductor N contacts with Graphene.For this new material of Graphene, though it has with the similar carrier concentration of metal (can reach 10
23~ 10
26Cm
-3), far above the carrier concentration in the semiconductor (10
17~ 10
21Cm
-3), has metallicity, but the essential distinction of it and common metal is: common metal has the very high density of states and the paraboloidal band structure of class at Fermi surface, therefore the transfer of a little electrons can not cause moving of its Fermi surface, and the band structure of Graphene is linear near Fermi surface, and band gap is zero (as shown in the square frame of (c) right side), therefore a little electrons is moved to Graphene, fill being with, will cause the rapid variation of its work function: the Graphene work function can reduce with the immigration of electronics, raises with the outflow of electronics.Shown in (d), when semiconductor contacts with Graphene, no matter there is great difference between semiconductor work function and Graphene work function, after through a little electrons migration, the Fermi level of Graphene can be adaptively realized coupling with semiconductor, and this makes the width of net charge quantity in the semiconductor and space charge region much smaller than contacting that the metal of identical work function forms, thereby makes semiconductor energy gap only produce a small amount of bending, form lower contact berrier, reduce contact resistance greatly.
Though Fig. 1 is exemplified as
nThe situation of type contact, but
pThe situation that contacts and its basically identical of N-type semiconductor N and Graphene.Because
pThe work function of N-type semiconductor N is than Graphene height, therefore what shift to Graphene is holoe carrier, the same minority carrier that shifts just can make the Fermi surface of Graphene reduce (work function rising), thereby mates with the semiconductor Fermi surface, thereby produces the effect that contact resistance reduces.
The invention has the advantages that, by between metal and semiconductor layer, inserting graphene layer, improved the energy carrier state of gold half contact, can be widely used in the metal of different work functions and the semiconductor of different doping types and doping content, reduce the potential barrier that contact can be with, thereby played the effect that reduces contact resistance.Method preparation provided by the invention is simple, stable performance, and good reproducibility, with low cost, have important function for the micro-nano semi-conductor electronic device of realizing various high-performance and low-costs.
Description of drawings
Accompanying drawing 1 is the energy band diagram that the present invention realizes principle.
Accompanying drawing 2A is the process schematic representation of the embodiment of the invention one to accompanying drawing 2G.
Accompanying drawing 3 is test structure schematic diagrames of the embodiment of the invention one and two.
Embodiment
Elaborate below in conjunction with the embodiment of accompanying drawing to metal-semiconductor electrode structure provided by the invention and preparation method thereof.
Embodiment one, is that example is narrated with intrinsic GaN crystal as semiconductor layer.
Step 11,2A with reference to the accompanying drawings, Graphene preparation: select the surface preparation graphene film 110 of the method for chemical vapour deposition (CVD) for use, belong to known technology, no longer be described in detail herein about the embodiment of chemical vapour deposition technique in growth substrates 100.This step need provide independent growth substrates 100 for the chemical gaseous phase substrate processing.The technology of chemical vapour deposition technique can form graphene film on growth substrates 100 surfaces, and this technology is very wide in range to the requirement of growth substrates 100 materials, a lot of common backing materials, for example monocrystalline silicon, sapphire, glass even metal substrate can meet the demands.Described graphene film 110 also can adopt the wet chemistry method growth.Graphene film 110 is without the p type or the n type mixes or the Graphene of finishing.
Step 12,2B with reference to the accompanying drawings, spin coating dimethyl silicone polymer (PDMS) layer 130 on graphene film 110, because PDMS has certain viscosity, can adhere to the graphene film layer, and utilize chemical method corrosion Graphene substrate, thereby the graphene film layer is peeled off from growth substrates.For example growth substrates 100 is placed the chemical corrosion liquid that can corrode growth substrates, make graphene film 110 and dimethyl siloxane (PDMS) layer 130 peel off and swim on the liquid level from growth substrates 100.
Step 13, the cleaning of intrinsic GaN crystal: with organic solvent clean surface such as acetone, alcohol.
Step 14,2C is imprinted on intrinsic GaN crystal 120 surfaces with graphene film 110 and the laminated film lamination that PDMS layer 130 constitutes with reference to the accompanying drawings.In this step, graphene film 110 fits tightly with intrinsic GaN crystal 120.
Above step S12 to S15 also can replace following steps: after enforcement finishes step S11, the growth substrates 100 that directly will have graphene film 110 places the chemical corrosion liquid that can corrode growth substrates 100, makes graphene film 110 peel off and swim on the liquid level from growth substrates 100; Clean the surface of intrinsic GaN crystal 120; With intrinsic GaN crystal 120 graphene film 110 is picked up from solution, the surface tension of grapheme material makes graphene film 110 sprawl and be adsorbed on the surface of intrinsic GaN crystal 120, thereby forms graphene film 110 on intrinsic GaN crystal 120 surfaces.More than two kinds of methods can form graphene film at semiconductor substrate surface.
Step 16,2E with reference to the accompanying drawings, evaporation metal: select for use the method for vacuum evaporation that conductive metal layer 140 is covered on the graphene film 110.
Step 17,2F forms patterned etching barrier layer 150 on metal level 140 surfaces with reference to the accompanying drawings.This is common photoetching process.
Step 18,2G utilizes inductively coupled plasma (ICP) method etching sheet metal 140 and graphene film 110 to intrinsic GaN crystal 120 to stop with reference to the accompanying drawings, forms electrode structure.
Structure shown in the accompanying drawing 3 is the test structure of making for the validity that shows said method, comprises two electrodes 310 and 320 on intrinsic GaN layer 300 and surface thereof, and each electrode includes graphene layer 311 and 321, and metal level 312 and 322.Accompanying drawing 4 is electrode performance testing results of this structure.Electrode performance detects and to have utilized conducting atomic force microscopy, test probe is contacted with as shown in Figure 3 electrode respectively, thereby obtained between test electrode the IV curve as shown in Figure 4.This result is directly contacted the result who is surveyed the back with probe compare with n type GaN, as shown in Figure 4, obviously reduced contact resistance as can be known.
Embodiment two: is that example is narrated with P type GaN crystal as semiconductor layer.
Step 21, Graphene preparation: select for use the method for graphite oxidation reduction to prepare the graphene powder material.Embodiment about the graphite reduction method belongs to known technology, no longer is described in detail herein.
Step 22, the cleaning of p type GaN crystal: with organic solvent clean surface such as acetone, alcohol.
Step 23 is covering graphene layer: the graphene powder material is spin-coated on the p type GaN crystal on the p type GaN crystal.
Step 24, evaporation metal: select for use the method for vacuum evaporation that conductive metal layer is covered on the graphene layer.
Step 25 forms etching barrier layer at layer on surface of metal.
Step 26 utilizes inductively coupled plasma (ICP) method etching sheet metal and graphene layer to p type GaN crystal to stop, and forms electrode structure.
Be to adopt said method to make the structure identical shown in the accompanying drawing 5, and adopt the test result after identical method is carried out electrical testing with accompanying drawing 3.This result directly contacts the result who is surveyed the back with probe and compares with p type GaN, obviously reduced contact resistance as can be known.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (14)
1. a metal-semiconductor electrode structure comprises semiconductor layer and metal electrode, it is characterized in that, a graphene layer further is set between semiconductor layer and metal electrode, to reduce the contact resistance between metal electrode and the semiconductor layer.
2. metal-semiconductor electrode structure according to claim 1 is characterized in that, the material of described semiconductor layer is selected from a kind of in III-V compounds of group, II-VI compounds of group and IV compounds of group and the element semiconductor.
3. metal-semiconductor electrode structure according to claim 1 is characterized in that, the conduction type of described semiconductor layer is selected from a kind of in N type semiconductor, P type semiconductor and the intrinsic semiconductor.
4. metal-semiconductor electrode structure according to claim 3 is characterized in that, the material of described semiconductor layer is a semiconductor material with wide forbidden band.
5. metal-semiconductor electrode structure according to claim 4 is characterized in that, described semiconductor material with wide forbidden band is selected from a kind of in GaN, AlN, ZnO, SiC and ZnTe and the alloy thereof.
6. metal-semiconductor electrode structure according to claim 1 is characterized in that, the material of described graphene layer is selected from a kind of in monoatomic layer Graphene and the polyatom layer graphene.
7. metal-semiconductor electrode structure according to claim 6 is characterized in that, described Graphene is without the p type or the n type mixes or the Graphene of finishing.
8. metal-semiconductor electrode structure according to claim 1 is characterized in that, the material of described metal electrode is selected from a kind of in gold, silver, platinum, nickel, copper, cobalt, palladium and the aluminium.
9. the preparation method of a metal-semiconductor electrode structure is characterized in that, comprises the steps:
Adopt the method for chemical vapour deposition (CVD) on growth substrates, to prepare the graphene film layer;
Growth substrates is placed the chemical corrosion liquid that can corrode growth substrates, make the graphene film layer peel off and swim on the liquid level from growth substrates;
Clean the surface of Semiconductor substrate;
With Semiconductor substrate graphene film is picked up from solution, the surface tension of grapheme material makes the graphene film layer sprawl and be adsorbed on the surface of semiconductor layer, thereby forms graphene layer at semiconductor substrate surface;
Surface at graphene layer forms metal level;
Form etching barrier layer at layer on surface of metal;
Etching sheet metal and graphene layer to Semiconductor substrate stops, to form electrode structure.
10. the preparation method of a metal-semiconductor electrode structure is characterized in that, comprises the steps:
Select for use the method for chemical vapour deposition (CVD) on growth substrates, to prepare the graphene film layer;
On the graphene film layer, apply adhesion layer, form the THIN COMPOSITE rete of adhesion layer and Graphene;
Growth substrates is placed the chemical corrosion liquid that can corrode growth substrates, make graphene film and adhesion layer peel off and swim on the liquid level from growth substrates;
Clean Semiconductor substrate;
The laminated film lamination of graphene film and adhesion layer is imprinted on the surface of Semiconductor substrate;
Adhesion layer is removed, thereby formed graphene layer at semiconductor substrate surface;
Surface at graphene layer forms metal level;
Form etching barrier layer at layer on surface of metal;
Etching sheet metal and graphene layer to Semiconductor substrate stops, to form electrode structure.
11. the preparation method of metal-semiconductor electrode structure according to claim 10 is characterized in that, the material of described adhesion layer is a dimethyl silicone polymer, and the described step that adhesion layer is removed adopts dissolution method.
12. the preparation method of metal-semiconductor electrode structure according to claim 10 is characterized in that, in the step of described etching sheet metal and graphene layer, employing be the inductively coupled plasma lithographic method.
13. the preparation method of a metal-semiconductor electrode structure is characterized in that, comprises the steps:
Adopt the method for graphite oxidation reduction to prepare the graphene powder material;
Clean the surface of Semiconductor substrate;
At the surface applied graphene powder material of Semiconductor substrate, form graphene layer;
Surface at graphene layer forms metal level;
Form etching barrier layer at layer on surface of metal;
Etching sheet metal and graphene layer to Semiconductor substrate stops, and forms electrode structure.
14. the preparation method of metal-semiconductor electrode structure according to claim 13 is characterized in that, in the step of described etching sheet metal and graphene layer, employing be the inductively coupled plasma lithographic method.
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