CN101977482B - Method for etching outer circuit of PCB product with high aspect ratio - Google Patents
Method for etching outer circuit of PCB product with high aspect ratio Download PDFInfo
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- CN101977482B CN101977482B CN2010105373448A CN201010537344A CN101977482B CN 101977482 B CN101977482 B CN 101977482B CN 2010105373448 A CN2010105373448 A CN 2010105373448A CN 201010537344 A CN201010537344 A CN 201010537344A CN 101977482 B CN101977482 B CN 101977482B
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Abstract
The invention discloses a method for etching an outer circuit of a PCB (printed circuit board) product with high aspect ratio, which comprises the following steps of: A) cutting a circuit board substrate, sticking a dry film, browning the inner layer, treating a pressing board, and then drilling the circuit board substrate; B) performing copper deposition plating on the full board or adding a board for plating; C) performing first film removal treatment on the pattern plated board; D) performing alkali etching treatment on the outer circuit after development; and E) performing tin removal treatment on the PCB obtained in the step D), inspecting qualification, and obtaining a finished product. The method for etching the outer circuit of the PCB product with the high aspect ratio can manufacture the product with aspect ratio of 15:1 to 30:1 or over by sticking the film again after the pattern plating is finished, using hole covering film exposure, covering the dry film on the hole for protection, adopting alkali etching and then removing the film and the tin; and the method has no defect of the PCB with high aspect ratio manufactured by prolonging the tin plating time or increasing the tin plating current density in the prior art.
Description
Technical field
The invention belongs to PCB manufacturing process field, especially relate to a kind of PCB product outer-layer circuit engraving method of high aspect ratio.
Background technology
When the thickness of slab of wiring board greater than 6mm, aspect ratio used negative film etching (acid liquid medicine) to cause closure plate, circuit etching excessively to scrap because plate is too thick easily more than or equal to 15: 1 o'clock at skin; And if the etching of use positive is easy because hole, the hole mid portion tin of zinc-plated time≤0.4mm approaches and causes etch-hole not have copper and scrap.In the prior art, employing prolongs the zinc-plated time or strengthens zinc-plated current density and solve the high multi-layer sheet of aspect ratio usually.But, adopt to prolong zinc-plated time method, be easy to generate outer-layer circuit folder film, cause between circuit short circuit to be scrapped; And time expand and increasing electric current still can not be electroplated onto more than the 7.6 μ m tin in the hole of aperture is thick.
Summary of the invention
The present invention provides a kind of PCB product outer-layer circuit engraving method of high aspect ratio; After accomplishing graphic plating, pad pasting, and use once more covers hole film exposure; On the hole, covering dry film protects; Adopt alkali etching to move back film then, move back tin, can make aspect ratio 15: 1 to 30: 1 and above product, and do not exist prior art through prolonging the zinc-plated time or strengthening the defective of the pcb board existence of the high aspect ratio that zinc-plated current density makes.
For realizing above-mentioned purpose, the present invention adopts following technical scheme:
A kind of PCB product outer-layer circuit engraving method of high aspect ratio comprises step:
A) the wiring board substrate is opened material, pasted dry film (internal layer graphic making), after internal layer brown and pressing plate handle, it holed;
B) the heavy copper of plate is electroplated or the splice plating entirely, and the force fit plate after the heavy copper plating is carried out outer graphics shift, and pattern plating copper and tin;
C) plate behind the graphic plating is carried out moving back the first time film and handle, and paste dry film again, outer-layer circuit is used covered the hole film and make public and development treatment;
D) outer-layer circuit after developing is carried out alkali etching and handle, and carry out moving back the second time film and handle, the dry film that covers on the hole is returned;
E) with step D) the gained pcb board moves back tin and handles, and the pcb board that moves back after tin is handled is detected through flying probe tester, and it is qualified to detect, and makes finished product.
Described steps A) boring aperture is the hole of 0.2-0.6mm diameter, main shaft drilling speed 20krpm-180krpm, and control hole is thick≤20 μ m.
Described step B) heavy copper plating of full plate or splice are electroplated in the hole, to do the last layer metal level, and thickness is 0.25 μ m-10 μ m, and making it add the plate electricity is 3-10 μ m with the metapore copper thickness.
Described step B) the thick 20-50 μ of the electroplating hole copper copper m of graphic plating; Electrotinning uses the current density of 1.0-1.6ASD, electroplates 10-25min, the thick control of tin 5-20 μ m.
Described step C) build that pastes dry film again is 40-50 μ m, control pad pasting speed 1.5-3m/min, and the dry film width of coverage hole is than the big 0.15-0.3mm in hole, and promptly each limit need cover 0.075mm-0.3mm.
Said step e) is that four line flying needles detect when detecting,, uses resistance to judge the thickness situation of copper in the hole through the copper resistance in the instrument connection through flying probe tester; It is qualified that the resistance of 0-4mohm is judged, 4-6mohm does section and analyzes, and it is thick with the thick plating of copper to readjust parameter more than the 6mohm.
Under the situation of close gap development, the aperture that product designed is more and more littler at product; General, the aperture is more little, and the speed of boring under requiring is slow more, but accent jogging speed simply will influence the efficient of making, at this time, needs to consider to strengthen the drilling speed of main shaft, raising line cutting speed.So in order to satisfy the efficient of making, we need use the higher speed of mainshaft on the one hand; On the other hand, roughness is to weigh the important indicator of drilling quality, and he has directly influenced the quality of hole wall copper, the quality of wave-soldering when having influenced surface encapsulation simultaneously.
The PCB product outer-layer circuit engraving method of high aspect ratio of the present invention; After accomplishing graphic plating, pad pasting, and use once more covers hole film exposure; On the hole, covering dry film protects; Adopt alkali etching to move back film then, move back tin, can make aspect ratio 15: 1 to 30: 1 and above product, and do not exist prior art through prolonging the zinc-plated time or strengthening the defective of the pcb board existence of the high aspect ratio that zinc-plated current density makes.The thickness of slab that makes can be between 6-12mm, and can satisfy the thick control of copper of hole copper 20-50 μ m and the accurate circuit of making 3/3mil; Be particularly suitable for double sided board and multiple-plate making, have vast market prospect.
Embodiment
Below in conjunction with specific embodiment the present invention is explained further details.
Embodiment 1
Parameter request:
Core material: 0.089mm l/l (not cupric) number of plies: 32L
Internal layer live width spacing: Min 3.0/3.0miL
Outer live width spacing: Min 4.0/4.0miL
Plate Tg:170 °
Outer copper foil: HOZ
Hole copper thickness: Min 25 μ m
Resistance weldering: green oil
Surface treatment: turmeric
Accomplish thickness of slab: 4.5mm+/-10%
Minimum-value aperture: 0.3mm
Work PNL size: 830mm*412mm
Mask-making technology:
1, opening material---830mm*412mm leaves central layer by the jigsaw size, central layer thickness 0.089mm l/l (not cupric);
2, internal layer---accomplish the internal layer circuit exposure with 5-7 lattice exposure guide rule (21 lattice exposure guide rule), the development after etching goes out inner line figure, and it is 2.4miL that the internal layer live width measures minimum;
3, the opening defective such as short circuit and make correction of internal layer AOI---inspection internal layer;
4, pressing---behind the brown lamination, select for use suitable lamination to carry out pressing according to plate Tg, plate thickness is measured as 4.3mm after the pressing;
5, boring---utilize the borehole data processing of holing;
6, heavy copper---hole metallization, 9.5 grades of tests backlight;
7, electric plating of whole board---with the current density electric plating of whole board 30min of 15ASF, hole copper thickness 5-8 μ m;
8, outer graphics shifts---and paste dry film, accomplish the outer-layer circuit exposure with 5-7 rank exposure guide rule (21 rank exposure guide rule), and develop;
9, graphic plating---the current density with 10ASF is electroplated 180min, finally accomplishes hole copper at 25-30 μ m, face copper 40-46 μ m, and copper facing is zinc-plated after accomplishing, the thick 8-13 μ m that is controlled at of tin;
10, film was moved back in etching in the past, pasted dry film again, again exposure; Only cross washing before pasting dry film, use pad pasting pressure 4kg/cm
2, only with the exposure of hole bit position, the making lid hole size of the film and the Xi Quan in hole etc. are big during exposure;
11, etching---directly etching is moved back film more earlier after etching is accomplished and is retreated tin;
12, outer AOI---check and outer fieldly open defectives such as short circuit and make correction;
13, resistance weldering---silk-screen resistance weldering and literal, this plate resistance weldering is green oil, detects the minimum 8 μ m of resist thickness line angle, character silk printing;
14, turmeric---the heavy nickel gold of full plate, the thick 5 μ m of nickel, golden thick 2uinch;
15, external form---gong external form, the external form tolerance+/-0.10mm;
16, electrical testing---the electric property of test-based examination production board;
17, inspection eventually---the aesthetic appearance of inspection production board is bad;
18, shipment.
Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (7)
1. the PCB product outer-layer circuit engraving method of a high aspect ratio comprises step:
A) the wiring board substrate is opened material, is pasted dry film, internal layer brown and the pressing plate be used to make inner line figure and handle after, it is holed;
B) the heavy copper of full plate is electroplated, and the force fit plate after the heavy copper plating is carried out outer graphics shift, and pattern plating copper and tin;
C) plate behind the graphic plating is carried out moving back the first time film and handle, and paste dry film again, outer-layer circuit is used covered the hole film and make public and development treatment;
D) outer-layer circuit after developing is carried out alkali etching and handle, and carry out moving back the second time film and handle, the dry film that covers on the hole is returned;
E) with step D) the gained pcb board moves back tin and handles, and the pcb board that moves back after tin is handled is detected through flying probe tester, and it is qualified to detect, and makes finished product.
2. the PCB product outer-layer circuit engraving method of high aspect ratio as claimed in claim 1, it is characterized in that: described steps A) boring aperture is the hole of 0.2-0.6mm diameter, main shaft drilling speed 20krpm-180krpm, control hole thickness≤20 μ m.
3. the PCB product outer-layer circuit engraving method of high aspect ratio as claimed in claim 2; It is characterized in that: described step B) heavy copper plating of full plate or splice are electroplated in the hole, doing the last layer metal level; Thickness is 0.25 μ m-10 μ m, and making it add the plate electricity is 3-10 μ m with the metapore copper thickness.
4. the PCB product outer-layer circuit engraving method of high aspect ratio as claimed in claim 2 is characterized in that: the thick 20-50 μ of the electroplating hole copper copper m of graphic plating described step B); Electrotinning uses the current density of 1.0-1.6ASD, electroplates 10-25min, the thick control of tin 5-20 μ m.
5. like the PCB product outer-layer circuit engraving method of claim 3 or 4 described high aspect ratios; It is characterized in that: the build that described step C) pastes dry film again is 40-50 μ m; Control pad pasting speed 1.5-3m/min; The dry film width of coverage hole is than the big 0.15-0.3mm in hole, and promptly each limit need cover 0.075mm-0.3mm.
6. the PCB product outer-layer circuit engraving method of high aspect ratio as claimed in claim 5; It is characterized in that: said step e) be that four line flying needles detect when detecting through flying probe tester; Through the copper resistance in the instrument connection, use resistance to judge the thickness situation of copper in the hole; It is qualified that the resistance of 0-4mohm is judged, 4-6mohm does section and analyzes, and it is thick with the thick plating of copper to readjust parameter more than the 6mohm.
7. the PCB product outer-layer circuit engraving method of high aspect ratio as claimed in claim 6, it is characterized in that: the high aspect ratio PCB PRODUCTS FIELD that said method makes is than 15: 1-30: 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105373448A CN101977482B (en) | 2010-11-09 | 2010-11-09 | Method for etching outer circuit of PCB product with high aspect ratio |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105373448A CN101977482B (en) | 2010-11-09 | 2010-11-09 | Method for etching outer circuit of PCB product with high aspect ratio |
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| CN101977482A CN101977482A (en) | 2011-02-16 |
| CN101977482B true CN101977482B (en) | 2012-03-28 |
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| CN2010105373448A Expired - Fee Related CN101977482B (en) | 2010-11-09 | 2010-11-09 | Method for etching outer circuit of PCB product with high aspect ratio |
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| CN102883541B (en) * | 2012-10-17 | 2015-02-11 | 无锡江南计算技术研究所 | Plasma sandwiched film removing method |
| CN104105350B (en) * | 2013-04-02 | 2017-10-10 | 深南电路有限公司 | The method and pcb board of selectivity electricity nickel gold |
| CN103327746B (en) * | 2013-05-02 | 2016-01-13 | 深圳崇达多层线路板有限公司 | A kind of PCB outer layer engraving method of fine-line |
| CN104602452B (en) * | 2013-10-31 | 2017-11-10 | 北大方正集团有限公司 | A kind of preparation method of circuit board |
| CN104363704B (en) * | 2014-10-30 | 2017-12-29 | 江门崇达电路技术有限公司 | A kind of thick hole copper PCB preparation method |
| CN104883823A (en) * | 2015-05-22 | 2015-09-02 | 胜宏科技（惠州）股份有限公司 | Processing method of alkaline etching collapser |
| CN104952376B (en) * | 2015-06-12 | 2017-07-28 | 信丰福昌发电子有限公司 | It is a kind of to improve the technique that dot oozes golden short circuit away from LED lamp panel |
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| CN105282977A (en) * | 2015-10-15 | 2016-01-27 | 深圳崇达多层线路板有限公司 | Method for improving copper missing of metalized back drilling hole of circuit board with high thickness-to-diameter ratio |
| CN105392288A (en) * | 2015-11-18 | 2016-03-09 | 江门崇达电路技术有限公司 | Method for manufacturing metalized blind holes on PCB |
| CN105682376B (en) * | 2016-03-17 | 2018-10-19 | 惠州市星之光科技有限公司 | A kind of thickness copper high aspect ratio small-bore mainboard manufacture craft |
| CN106341949B (en) * | 2016-09-22 | 2020-12-04 | 惠州市永隆电路有限公司 | Circuit board drilling and etching process |
| CN106757182A (en) * | 2017-01-19 | 2017-05-31 | 昆山元天电子有限公司 | A kind of recycling technique of PCB surface metallic copper |
| CN107241867B (en) * | 2017-06-21 | 2019-11-22 | 深圳崇达多层线路板有限公司 | Occurs the process of plating folder film when a kind of reduction alkali etching |
| CN108617095B (en) * | 2018-05-09 | 2020-06-30 | 珠海精路电子有限公司 | Manufacturing process of double-layer single-side copper-based circuit board |
| CN111225509B (en) * | 2019-12-06 | 2021-08-06 | 中国电子科技集团公司第四十三研究所 | Etching method |
| CN110996566B (en) * | 2019-12-27 | 2023-09-12 | 大连崇达电路有限公司 | Manufacturing method of high-definition multilayer circuit board |
| CN111278228A (en) * | 2020-02-12 | 2020-06-12 | 大连崇达电子有限公司 | Method for improving local tin stripping unclean of outer layer etching |
| CN114554726A (en) * | 2022-03-29 | 2022-05-27 | 广东骏亚电子科技股份有限公司 | Electroplating method of circuit board with high aspect ratio |
| CN117042338B (en) * | 2023-10-09 | 2024-01-12 | 深圳明阳电路科技股份有限公司 | Printed circuit board production process for high-end server and printed circuit board |
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Owner name: DALIAN SUNTAK CIRCUIT TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: SHENZHEN SUNTAK MULTILAYER PCB CO., LTD. Effective date: 20120522 |
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Effective date of registration: 20120522 Address after: 116000 No. 3 middle Huaihe Road, Dalian economic and Technological Development Zone, Liaoning Patentee after: Dalian Chongda Circuit Co.,Ltd. Address before: 518000, Shenzhen, Guangdong, Baoan District province Henggang Industrial Zone, lower village, Chong Da Industrial Park Patentee before: Shenzhen Suntak Multilayer PCB Co., Ltd. |
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Granted publication date: 20120328 Termination date: 20191109 |