CN101958390A - Light-emitting chip packaging structure - Google Patents

Light-emitting chip packaging structure Download PDF

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Publication number
CN101958390A
CN101958390A CN2010102607557A CN201010260755A CN101958390A CN 101958390 A CN101958390 A CN 101958390A CN 2010102607557 A CN2010102607557 A CN 2010102607557A CN 201010260755 A CN201010260755 A CN 201010260755A CN 101958390 A CN101958390 A CN 101958390A
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submounts
substrate
bonding area
crystal bonding
package structure
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李刚
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Individual
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

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Abstract

The invention relates to a light-emitting chip packaging structure which comprises at least one substrate unit, at least one wafer-bonding region arranged on the substrate unit, at least one light-emitting chip installed on the wafer-bonding region and at least two mutually insulated substrate electrodes arranged on the substrate unit and capable of realizing electric connection with the outside, wherein the substrate unit comprise at least two mutually insulated sub substrates; and the light-emitting chip is electrically connected with the substrate electrodes through the substrate unit. Because the substrate unit formed from the at least two mutually insulated sub substrates is used as an installing support of the light-emitting chip, the light-emitting chip packaging structure has simple structure and good heat dissipation effect; moreover, only an insulating layer is needed or even the insulating layer is not needed between the sub substrates, then entire structure does not contain any high polymer material, and thus, the light-emitting chip packaging structure has the advantages of heat resistance and ultraviolet resistance.

Description

Luminous chip package structure
Technical field
The present invention relates to chip-packaging structure, more particularly, relate to a kind of encapsulating structure of luminescence chip.
Background technology
Along with luminescence chip, diode (LED) chip for example, the lifting of luminous efficiency, LED just from traditional point-line-surface be the indication of feature and show the class application to large scale liquid crystal backlight and indoor and outdoor general lighting class application expand.
Existing a kind of common encapsulating structure that is used for LED encapsulation as shown in Figure 1, this encapsulating structure comprises an electrode suppor 101, led chip 102, metal lead wire 103a and 103b, another electrode suppor 104 and support brace 105.Above-mentioned led chip 102 is placed in the cup that is subjected to electrode suppor 101 and 104 supports.Wherein, electrode suppor 101 and 104 is that heat-sinking capability is limited with the silver-plated material manufacturing of elongated iron-based.The LED of above-mentioned encapsulating structure can only adopt insulating cement (as epoxy resin) as solid brilliant material usually.Because the non-constant of heat conductivility of insulating cement, therefore, this encapsulating structure mainly is used in little electric current application scenario.
The common encapsulating structure that another kind is used for high-power LED encapsulation as shown in Figure 2, this encapsulating structure comprises led chip pedestal 201, led chip 202, metal lead wire 203a and 203b, electrode slice 204a and 204b and insulation plastic cement reflector 205.Above-mentioned high-power LED encapsulation structure adopts block led chip pedestal 201, and is heat sink bigger, and its lower surface generally can contact with other cooling mechanism or device formation face, promotes heat-sinking capability.Yet, above-mentioned high-power LED encapsulation structure more complicated, cost is than higher.
Above-mentioned high-power LED encapsulation structure adopts metallic based structures to add the technology manufacturing of macromolecule organic material injection molded usually.Usually adopt in the macromolecular materials thermal endurance thermoplasticity polyester relatively preferably as the insulation plastic cement reflector among Fig. 2 205, as polybutylene terephthalate (PBT) (PBT) and high temperature plastic cement, as poly-terephthalate p-phenylenediamine (PPD) (PPA).About 300 ℃ of the heat distortion temperature of the poly-terephthalate p-phenylenediamine (PPD) plastic cement of modification, serviceability temperature is about 170 ℃ continuously.Obviously, the heat resisting temperature of macromolecular material will determine the maximum withstand temperature and the highest sustainable working temperature of above-mentioned support.
Yet common eutectic weldering temperature is at 285 ℃-320 ℃.Because the maximum withstand temperature of the above-mentioned support of above-mentioned high molecular weight plastic of employing or polyester insulating material is only about 300 ℃, make the selection of eutectic material be subjected to great limitation, it is very harsh that the eutectic condition also becomes, must be very accurate as temperature control, the eutectic time can not be oversize etc., causes eutectic solid welding crystal technique requirement height, cost height and yield low.At present, most of great power LED still adopts conventional solid crystal type, as using the improved silica gel of heat conductivility, elargol, tin cream etc., but the obvious alloying interface not as producing with the eutectic mode of the heat conductivility of its solid crystal boundary face.Big electric current or high-powerly because interface resistance causes the heat localization in the led support, the temperature of chip is raise down, thus have influence on the anti-attenuation and the reliability of led chip.Because the poor ability that macromolecular material uvioresistant and anti-high and low-temp impact, can accelerate to wear out when making insulation plastic cement reflector 205 among above-mentioned support such as Fig. 2 under the comparatively abominable open-air occasion of UV-irradiation and high/low-temperature impact, use, cause the useful life of LED very short, the reliability of application product is also just very poor.
To adopting metal-cored or ceramic core printed circuit board (PCB) (MCPCB) though the high-power LED bracket of making can provide bigger basal surface to be connected with other cooling mechanism as thermal conductive surface, but the macromolecule resin material that is used for insulating between electrode on the printed circuit board (PCB) has limited the serviceability temperature of above-mentioned high-power LED bracket, can not adopt eutectic solid welding crystal type usually.The ability of above-mentioned resin antagonism UV-irradiation and high/low-temperature impact is also very poor, make and to accelerate to wear out when above-mentioned high-power LED bracket uses under the comparatively abominable open-air occasion of UV-irradiation and high/low-temperature impact, cause the useful life of LED very short, the reliability of application product is also just very poor.The above-mentioned macromolecule resin material that plays the insulating barrier effect, normally 50～200um.If too thick, can play insulating effect, prevent effective with the Metal Substrate short circuit, but can influence distributing of heat; If too thin, can better dispel the heat, but easily cause metal-cored and the package lead short circuit.
To adopting ceramic heat-dissipating substrate, comprise the thick film ceramic substrate, low temperature co-fired multi-layer ceramics, with the thin-film ceramics substrate, though the high-power LED bracket of making can provide bigger basal surface to be connected with other cooling mechanism as thermal conductive surface, the heat dispersion of ceramic material also is better than other organic material, and its non-conductive property requirement is passed through wire mark or sputter at substrate surface, electricity/electrochemical deposition, technology manufacturings such as gold-tinted processing procedure and low-temperature sintering conduction connects the metallic circuit layer.The circuit that the wire mark mode is made is because the half tone problem of throwing the net, and is easy to generate that circuit is coarse, contraposition phenomenon accurately not, sputter, electricity/electrochemical deposition, gold-tinted making technology complexity, metal wire Louis shortcoming such as come off.
All kinds of LED encapsulating structures that above-mentioned quilt extensively makes realize that except that the bottom has sheet metal to link to each other with the support of fixed L ED support itself does not possess heat sinking function usually the heat conduction, and this has also limited to the scope of application and the self-protection function of LED greatly.Obviously, there is defective in essence in the support that is used for the LED encapsulation that is widely used now.
Summary of the invention
The technical problem to be solved in the present invention is, a kind of simple in structure, high temperature resistant, luminous chip package structure that radiating effect is good is provided.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of luminous chip package structure, comprise at least one base board unit, at least one at the crystal bonding area that is provided with on the described base board unit, be installed at least one luminescence chip on the described crystal bonding area and on described base board unit, be provided with mutually isolated at least two and can realize the electrode of substrate that conduction be connected with the external world; Described base board unit comprises at least two submounts insulated from each other; Described luminescence chip is electrically connected with described electrode of substrate by described base board unit.
In luminous chip package structure of the present invention, described submounts is provided with insulating barrier or insulating tape for the conduction submounts between adjacent described conduction submounts, perhaps, between adjacent described conduction submounts, leave the space, perhaps, in described space, fill insulating encapsulating material; Perhaps,
Described submounts is non-conductive submounts, is provided with the conductive metal film that described luminescence chip is electrically connected to corresponding described electrode of substrate on described non-conductive submounts; Perhaps,
Described submounts comprises conduction submounts and non-conductive submounts, is provided with the conductive metal film that described luminescence chip is electrically connected to corresponding described electrode of substrate on described non-conductive submounts.
In luminous chip package structure of the present invention, described base board unit is the single layer substrate unit, comprises at least two described submounts insulated from each other and that splice mutually in the horizontal direction; Perhaps,
Described base board unit is the multilager base plate unit, comprise at least two insulated from each other and at the described submounts of vertical direction mutual superposition; Perhaps,
Described base board unit is the MULTILAYER COMPOSITE base board unit, comprises at least one described submounts and at least one described single layer substrate unit, and described submounts and described single layer substrate unit are insulated from each other and in the vertical direction mutual superposition; Described single layer substrate unit comprises at least two described submounts insulated from each other and that splice mutually in the horizontal direction.
In luminous chip package structure of the present invention, described crystal bonding area all is arranged on the same described submounts that constitutes described single layer substrate unit, or is separately positioned on the different described submounts that constitutes described single layer substrate unit.
In luminous chip package structure of the present invention, described crystal bonding area all is arranged on the same described submounts that constitutes described multilager base plate unit, or is separately positioned on the different described submounts that constitutes described multilager base plate unit; Perhaps,
Described crystal bonding area all is arranged on the same described submounts that constitutes described MULTILAYER COMPOSITE base board unit, or is separately positioned on the different described submounts that constitutes described MULTILAYER COMPOSITE base board unit.
In luminous chip package structure of the present invention, described crystal bonding area is arranged on the described submounts of non-top layer, the described submounts that is positioned at the described submounts upper strata that described crystal bonding area is set is provided with and the corresponding opening of described crystal bonding area, and the madial wall of described opening constitutes embedding bright dipping space and the reflective sidewall that is placed on described luminescence chip in the described crystal bonding area.
In luminous chip package structure of the present invention, described crystal bonding area is arranged on the upper surface of described submounts; Perhaps, be positioned at the pit that described submounts surface is provided with, the madial wall of described pit constitutes embedding bright dipping space and the reflective sidewall that is placed on described luminescence chip in the described crystal bonding area.
In luminous chip package structure of the present invention, be provided with the cofferdam of projection around the described crystal bonding area; The madial wall in described cofferdam constitutes embedding bright dipping space and the reflective sidewall that is placed on described luminescence chip in the described crystal bonding area.
In luminous chip package structure of the present invention, the madial wall in described crystal bonding area surface, described embedding bright dipping space can apply the metallic reflective coating and/or the nonmetal reflectance coating of single or multiple lift.
In luminous chip package structure of the present invention, the madial wall in described embedding bright dipping space comprise become with the smooth surface of described crystal bonding area Surface Vertical and/or with described crystal bonding area surface greater than the smooth bevel of 90 degree angles and/or from described crystal bonding area surface to the smooth cambered surfaces of described base board unit surface extension.
In luminous chip package structure of the present invention, the madial wall in described embedding bright dipping space comprises at least one ladder, and the horizontal segment surface of described ladder is arranged on the described submounts surface with described crystal bonding area or has on the described submounts of described submounts top of described crystal bonding area.
In luminous chip package structure of the present invention, described luminescence chip is placed on the central authorities of described crystal bonding area, and conduction is connected to corresponding electrode of substrate respectively; Perhaps, described luminescence chip is a plurality of, conducts electricity respectively after some described luminescence chip serial or parallel connections or the connection in series-parallel to be connected to corresponding electrode of substrate again.
In luminous chip package structure of the present invention, be provided with respectively the wire welding area that conduction is connected to corresponding described electrode of substrate near the described crystal bonding area, described luminescence chip conducts electricity respectively and is connected to corresponding described wire welding area, or after wherein some described luminescence chip serial or parallel connections or the connection in series-parallel more respectively conduction be connected to corresponding wire welding area.
In luminous chip package structure of the present invention, the exposed surface of described base board unit is provided with the radiator structure that increases cooling surface area and/or is coated with heat sink material, and described heat sink material has the surface heat radianting capacity of increasing and/or capacity of heat transmission.
In luminous chip package structure of the present invention, described insulating barrier is one or more layers compound inslation film; Be provided with one or more layers transiting metal film and/or alloy firm between described insulating barrier and the described submounts.
Implement the present invention and have following beneficial effect: the base board unit that the present invention is made up of at least two submounts insulated from each other is as the mounting bracket of luminescence chip, and is simple in structure, and has better heat radiating effect; And between submounts, only need adopt insulating barrier or at all need not insulating barrier, total does not contain any macromolecule material, has high temperature resistant, uvioresistant advantage.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1: existing a kind of common support and connected mode that is used for the LED encapsulation.
Fig. 2: existing another kind is used for the common support and the connected mode of high-power LED encapsulation.
Fig. 3 a, 3b: the schematic diagram of first embodiment of luminous chip package structure of the present invention.
Fig. 4 a, 4b: the schematic diagram of second embodiment of luminous chip package structure of the present invention.
Fig. 5 a, 5b: the schematic diagram of the 3rd embodiment of luminous chip package structure of the present invention.
Fig. 6 a, 6b: the schematic diagram of the 4th embodiment of luminous chip package structure of the present invention.
Fig. 7 a, 7b: the schematic diagram of the 5th embodiment of luminous chip package structure of the present invention.
Fig. 8 a, 8b: the schematic diagram of the 6th embodiment of luminous chip package structure of the present invention.
Fig. 9 a, 9b: the schematic diagram of the 7th embodiment of luminous chip package structure of the present invention.
Embodiment
The embodiment of the luminous chip package structure of the present invention and the various LED of being used for encapsulation of the present invention can be fully understood that by the description of following preferred version following preferred version also can be considered the example of claim of the present invention.Obviously, should be fully understood that the content that is contained by the defined the present invention of claim of the present invention is more extensive than preferred embodiment described below.Under the situation that does not depart from spirit and scope of the invention, can produce more embodiment through change and modification by means of usual technical ability.So, embodiment described below only be illustrate for example rather than be used for the limitation by the defined covering scope of the present invention of claim of the present invention.
Shown in Fig. 3 a, 3b, be first embodiment of luminous chip package structure of the present invention, it comprises insulating bottom layer submounts 305, two layers of conduction submounts 301 and 302, crystal bonding area, metal lead wire 303 and 304, electrode of substrate 308a, 308b that are provided with and be provided with insulating tape 307 between submounts 301 and 302 on this insulating bottom layer submounts.
In the present embodiment, bottom submounts 305 can adopt insulating material to make, for example ceramic material or other Inorganic Non-metallic Materials, can be for single layer structure, also can be sandwich construction, also can be an insulation film, for example, mode by evaporation or sputter is with the inorganic insulation film, for example, silicon dioxide or silicon nitride are coated on the back side of described substrate.
Two layers of conduction submounts 301 and 302 are arranged on the bottom submounts 305, can adopt electric conducting material to make, and for example metal, alloy etc. can be for single layer structures, also can be sandwich construction.
Insulating tape 307 is set in conduction between the submounts 301 and 302, thereby will conduct electricity submounts 301 and 302 insulate and separates.This insulating tape 307 can adopt oxide-base, nitride based or other inorganic insulating material base single thin film material or be made by the multi-layer compound film material that above-mentioned material is formed, and with conduction submounts 301 and 302 between form contacting of close and firm.The shape of this insulating tape 307 can have any shape.
The base board unit of being made up of conduction submounts 301,302 and bottom submounts 305 is the MULTILAYER COMPOSITE base board unit.Wherein, the conduction submounts 301,302 of insulation splicing in the horizontal direction be the single layer substrate unit, and bottom submounts 305 and single layer substrate unit are insulated from each other and in the vertical direction mutual superposition.
This crystal bonding area can be arranged on conduction submounts 301 and/or the conduction submounts 302, as the installation site of luminescence chip 306.Certainly, the size of crystal bonding area, position etc. can be adjusted according to the quantity of luminescence chip 306, size etc.
Electrode of substrate 308a, 308b are separately positioned on the both sides of conduction submounts 301 and 302, can realize that conduction is connected with the external world, for luminescence chip 306 provides working power.
As shown in the figure, present embodiment has only schematically provided the encapsulation of a luminescence chip 306, this luminescence chip 306 is arranged on the conduction submounts 302 by solid brilliant method, the positive and negative electrode of luminescence chip 306 is connected on the conduction submounts 301 and 302 by metal lead wire 303 and 304 conductions respectively, and because conduction submounts 301 and 302 conductions own, therefore just the positive and negative electrode of luminescence chip 306 is connected with electrode of substrate 308a, 308b conduction respectively, introduces extraneous power supply by electrode of substrate 308a, 308b.
Certainly, shown in Fig. 3 c, luminescence chip also can be for a plurality of, can be arranged on electrically- conductive backing plate 301 and 302 by solid crystalline substance respectively, a plurality of luminescence chips can be in parallel and/or series connection after be connected with electrode of substrate 308a, 308b conduction respectively again.
Further, shown in Fig. 3 d, can also add embedding cofferdam 309 in the periphery of chip, form embedding bright dipping space, the shape in this embedding cofferdam 309 can be shape arbitrarily, as different shapes such as square annular, annular, oval rings, to play the effect that Embedding Material is fenced up.Certainly, also the embedding cofferdam can be set, the surface tension of directly utilizing Embedding Material is from moulding.
Further, shown in Fig. 3 e, it is a kind of distortion of Fig. 3 a, by increasing insulating tape 307a, the conduction submounts is separated into four conduction submounts unit insulated from each other, and corresponding luminescence chip can be set on each independently conducts electricity the submounts unit, thereby make things convenient for the layout of luminescence chip, the allotment of color etc.Its electrode pair should be divided into four independently electrode 308a, 308b, 308c, 308d, and independently conduct electricity the submounts unit with each respectively and link to each other, and insulated from each other.Understandable, can increase more insulation and bring the more conduction of separation submounts unit, thereby adapt to the requirement of different occasions.
As Fig. 4 a, shown in the 4b, it is second embodiment of the present invention, a kind of luminous chip package structure that the double layer substrate structure is arranged of the LED of being used for encapsulation, comprise bottom substrate 401, insulating barrier 402, bilevel substrate 403, the crystal bonding area that on bottom substrate 401, is provided with, be arranged on led chip 406 on the crystal bonding area by solid crystalline substance, bottom wire welding area 404a that is connected with chip and top layer wire welding area 404b, metal lead wire 405a and 405b, bottom electrode 407a that links to each other with extraneous power supply or/and signaling interface and top layer electrode 407b, fixed via 408a, 408b, 408c and 408d, embedding bright dipping space 409, bilevel substrate lower wall 410a and upper side wall 410b.This bottom substrate 401 and bilevel substrate 403 have been formed the electrically-conductive backing plate unit as submounts, and these 409 whiles of embedding bright dipping space are as the bright dipping space and the embedding space of led chip 406.
The embodiment of Fig. 4 a, 4b is to have the bilevel substrate 403 of a stepped opening to be placed on the bottom substrate 401 central authorities, is provided with an insulating barrier 402 between two substrates.Bottom substrate 401 and bilevel substrate 403 adopt good heat conduction of tool and good conductive metallic material usually, as copper, aluminium, tungsten and other metal material or their alloy; Certainly can also adopt ceramic base or other inorganic non-metallic sills and form conductive film and form, generally be superimposed in the form of sheets on the surface.Usually the thickness of single substrate is between between hundreds of micron and several millimeters.Single substrate also can adopt the sandwich construction that is made of above-mentioned material.Bottom substrate and two substrates can be selected identical or different material, identical or different thickness, identical or different size, identical or different shape etc. for use, can adjust according to designing requirement.
This bottom substrate 401 and bilevel substrate 403 superpose in vertical direction, be electrically-conductive backing plate, and insulating barrier 402 are arranged between bottom substrate 401 and the bilevel substrate 403, and it is isolated that both are insulated.This insulating barrier 402 adopts the individual layer or the composite multi-layer thin-film material of oxide-base or nitride based or other inorganic insulating material base usually, as silica and silicon nitride etc.Usually its thickness is between between several microns and the hundreds of micron.Be the adhesion strength between reinforced insulation layer 402 and bottom substrate 401 and the bilevel substrate 403, between insulating barrier 402 and bottom substrate 401 and bilevel substrate 403, be provided with the film that improves adhesion strength usually, usually adopt such as titanium, nickel, the alloy-layer of forming with metal materials such as tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.
Bottom substrate 401 in Fig. 4 a, the 4b embodiment provides again and chip and one group of extraneous electric connection point not only as the basis of luminous chip package structure simultaneously, and substrate 401 itself has the function of conductive electrode concurrently.This bottom substrate 401 comprises bottom electrically-conductive backing plate main body, and the crystal bonding area, bottom wire welding area 404b and the bottom electrode 407a that install for luminescence chip (led chip 406) are set on bottom electrically-conductive backing plate main body.
The center through hole sidewall of bilevel substrate 403 not only provides optical channel for the chip 406 that is placed on the bottom substrate 401, and reflective side surfaces also provides and chip and one group of extraneous electric connection point, and bilevel substrate 403 itself has the function of conductive electrode concurrently.This bilevel substrate 403 comprises top layer electrically-conductive backing plate main body as the top layer electrically-conductive backing plate, is provided with the top layer wire welding area 404b and the top layer electrode 407b of conductive communication on the top layer electrically-conductive backing plate.
The positive and negative electrode of this led chip 406 is electrically connected to bottom wire welding area 404a and top layer wire welding area 404b by metal lead wire 405a and 405b respectively, is connected with extraneous with bottom electrode 407a by top layer electrode 407b, promptly as power supply and control signal again.
Further, the stepped opening of these bilevel substrate 403 central authorities is corresponding with crystal bonding area, has formed embedding bright dipping space 409.Identical or different light transmission encapsulating material can pour in two districts up and down that lower wall 410a and upper side wall 410b surround.The following embedding district perfusion that surrounds as lower wall 410a contains the silica gel of fluorescent material and silica gel is poured in last embedding district that upper side wall 410b surrounds or epoxy resin then can be prepared common described white light LEDs.By the surface structure of improvement bottom substrate 401 and bilevel substrate 403, but above embedding district 409 other light transmission encapsulating material of embedding and/or place all kinds of preformed lens or other optics also.The profile of bottom substrate 401 and bilevel substrate 403 can be identical or different, and size can be the same or different.Usually employing is square, rectangle or circle.
The embedding district, two districts up and down that lower wall 410a in Fig. 4 a, the 4b embodiment and upper side wall 410b surround can be that symmetry is or/and asymmetric, different or/and identical shape, thus realize different light shape and light intensity distributions, adopt square usually, rectangle, oval or circular.Can become vertical or bevel between lower wall 410a and bottom substrate 401 surfaces and between the ledge surface of upper side wall 410b and bilevel substrate 403, lower wall 410a and upper side wall 410b itself can be smooth flat or smooth cambered surface, in order to the distribution of light in the control embedding district 409, then change light extraction efficiency, light shape and light intensity distributions.
Common above-mentioned sidewall 410a and 410b internal face scribble high reflecting material, as Ag or nonmetal reflecting material, form single or multiple lift metallic reflective coating and/or nonmetal reflectance coating.The exposed part (being the crystal bonding area surface) that bottom substrate 401 and bilevel substrate 403 are not laid electrode or wire welding area also scribbles high reflecting material usually, as Ag, absorbs to reduce.For avoiding short circuit, the exposed part of not laying electrode or wire welding area around the aforesaid substrate unit also can apply one deck dielectric film, as silica and silicon nitride etc.
As Fig. 5 a, shown in the 5b, it is another embodiment of the present invention, a kind of luminous chip package structure that convex double layer substrate structure is arranged of the LED of being used for encapsulation, comprise bottom substrate 501, insulating barrier 502, bilevel substrate 503, cofferdam, embedding district 509, the bilevel substrate cofferdam 503a concordant with cofferdam, embedding district 509, crystal bonding area, be arranged on led chip 506 on the crystal bonding area by solid crystalline substance, substrate wire welding area 504a that is connected with led chip 506 and substrate wire welding area 504b, metal lead wire 505a and 505b, the electrode of substrate 507a and the 507b that link to each other with extraneous power supply or/and signaling interface, fixed via 508a, 508b, 508c and 508d.
Led chip 506 in Fig. 5 a, the 5b embodiment is a plurality of, a kind of electrode of all led chips 506 (positive electrode or negative electrode) links to each other with the wire welding area 504b of metallic substrates laminar substrate 501 by metal lead wire 505b respectively, and the another kind of electrode of above-mentioned led chip 506 links to each other with the wire welding area 504a of metal bilevel substrate 503 by metal lead wire 505a respectively, forms the parallel connection method that is placed on the above-mentioned led chip 506 on the bottom substrate 501.
The upper surface of crystal bonding area, the oblique side wall surface 510 of bilevel substrate, bilevel substrate upper surface 510a, the inboard upper side wall 511a in cofferdam, embedding district and lower wall 511b surround embedding bright dipping space jointly.Identical or different light transmission encapsulating material can pour in two districts up and down that upper side wall 511a and lower wall 511b surround.The following embedding district perfusion that surrounds as lower wall 511b contains the silica gel of fluorescent material and silica gel is poured in last embedding district that upper side wall 511a surrounds or epoxy resin then can be prepared common described white light LEDs.In addition, can be by the surface structure in improvement bottom substrate 501 and cofferdam, embedding district 509, but above the embedding district other light transmission encapsulating material of embedding and/or place all kinds of preformed lens or other optics also.
Cofferdam, embedding district 509 can be conduction or electrically non-conductive material, and its profile and size can be identical or different with bottom substrate 501, for example adopts square, rectangle, circle or other different shape.
The embedding district, two districts up and down that upper side wall 511a in Fig. 5 a, the 5b embodiment and lower wall 511b surround can be that symmetry is or/and asymmetric, different or/and identical shape, thereby realize different light shape and light intensity distributions, for example adopt square, rectangle, ellipse, circle or other different shape.Can become vertical between upper side wall 511a, lower wall 511b and bottom substrate 501 surfaces or bevel or become arcuation, upper side wall 511a and lower wall 511b itself can be smooth flat or smooth cambered surface, in order to the distribution of light in the control embedding district 509, then change light extraction efficiency, light shape and light intensity distributions.Usually upper side wall 511a and lower wall 511b surface scribble high reflecting material, as Ag.The exposed part that bottom substrate 501 and bilevel substrate 503 are not laid electrode or wire welding area also scribbles high reflecting material usually, as Ag, absorbs to reduce, and improves light extraction efficiency.
As Fig. 6 a, shown in the 6b, it is the execution mode of the luminous chip package structure of the another kind of the present invention fluted double layer substrate that is used for LED encapsulation, comprise bottom substrate 601, insulating barrier 602, bilevel substrate 603a and 603b, insulation between the bilevel substrate cuts off band 603c and 603d, be arranged on the crystal bonding area on the bottom substrate 601, be arranged on led chip 606 on the crystal bonding area by solid crystalline substance, the wire welding area 604a and the 604b that are connected with led chip 606, metal lead wire 605a, 605b, 605c and 605b, and the line between the led chip 606 605, the bilevel substrate electrode 607a and the 607b that link to each other with extraneous power supply or/and signaling interface, fixed via 608a, 608b, 608c and 608d, by bilevel substrate lower wall 610a, the embedding bright dipping space 609 that the crystal bonding area upper surface of upper side wall 610b and bottom substrate 601 surrounds jointly.
Crystal bonding area in Fig. 6 a, the 6b embodiment has two groups of led chips 606, every group of 6 chips.First chip, first electrode of every core assembly sheet is connected with substrate wire welding area 604b, second electroplax of the 6th chip links to each other with substrate wire welding area 604a, second electrode of first chip links to each other with first electrode of second chip, by that analogy, realizes that 6 chips are connected in series.Chip is realized 6 strings two connection mode also in the whole LED support.Understandable, the quantity of led chip, group number etc. can be adjusted as required.
The embodiment of Fig. 6 a, 6b is that bilevel substrate 603a and the 603b butt joint that two plate shapes, size and thickness is identical is placed on the bottom substrate 601, and be provided with insulation between bilevel substrate 603a and the 603b and cut off band 603c and 603d, form the single layer substrate unit; And bilevel substrate 603a and 603b and bottom substrate 601 superpose in vertical direction, and are provided with an insulating barrier 602 between bilevel substrate 603a and 603b and bottom substrate 601, form the multilager base plate unit.Bottom substrate 601 and bilevel substrate 603a and 603b adopt good heat conduction of tool and good conductive metallic material usually, as copper, aluminium, tungsten, molybdenum and other metal material or their alloy, generally are superimposed in the form of sheets.Usually the thickness of single substrate is between between hundreds of micron and several millimeters.Single substrate can adopt single layer structure or the sandwich construction that is made of above-mentioned material.
Insulating barrier 602 adopts oxide or nitride film material usually, as silica and silicon nitride etc.Usually its thickness is between between several microns and the hundreds of micron.Be the adhesion strength between reinforced insulation layer 602 and bottom substrate 601 and bilevel substrate 603a and the 603b, between insulating barrier 602 and bottom substrate 601 and bilevel substrate 603a and 603b, be provided with the film that improves adhesion strength usually, usually adopt the alloy-layer formed such as metal material such as titanium, nickel and tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.
Insulation cuts off band 603c and 603d to be adopted usually a space is set between bilevel substrate 603a and 603b, embeds the inorganic non-metallic insulating material by the light transmission encapsulating material of inserting common insulation in the follow-up embedding process automatically or at bilevel substrate 603a and 603b opposing end faces coating one deck inorganic non-metallic insulating material or in the space.
Bottom substrate 601 in Fig. 6 a, the 6b embodiment is mainly as the basis and the passage of heat of encapsulating structure, the madial wall of bilevel substrate 603a and 603b not only provides optical channel for the chip 606 that is placed on the bottom substrate 601, reflective side surfaces, also provide and chip and extraneous electric connection point, bilevel substrate 603a and 603b itself have the function of conductive electrode concurrently.The stepped inwall of bilevel substrate 603a and 603b has formed embedding bright dipping space 609.Identical or different light transmission encapsulating material can pour in two districts up and down that upper side wall 610b and lower wall 610a surround.The following embedding district perfusion that surrounds as lower wall 610a contains the silica gel of fluorescent material and silica gel is poured in last embedding district that upper side wall 610b surrounds or epoxy resin then can be prepared common white light LEDs.By the surface structure of improvement bilevel substrate 603a and 603b, but above embedding district 609 other light transmission encapsulating material of embedding and/or place all kinds of preformed lens or other optics also.The profile of bottom substrate 601 and bilevel substrate 603a and 603b can be identical or different, and size can be the same or different, and for example adopts square, rectangle, circle or other arbitrary shape.
The embedding district, two districts up and down that upper side wall 610b in Fig. 6 a, the 6b embodiment and lower wall 610a surround can be symmetrical or asymmetric, have a similar and different shape, thereby realize different light shape and light intensity distributions, for example adopt square, rectangle, ellipse, circle or other shape.Can become vertical or bevel between lower wall 610a and bottom substrate 601 surfaces and between the ledge surface of upper side wall 610b and bilevel substrate 603a and 603b, upper side wall 610b and lower wall 610a itself can be smooth flat or smooth cambered surface, in order to the distribution of light in the control embedding district 609, then change light extraction efficiency, light shape and light intensity distributions.Common above-mentioned upper side wall 610b and lower wall 610a surface scribble high reflecting material, as Ag.The exposed part that bottom substrate 601 and bilevel substrate 603a and 603b do not lay electrode or wire welding area also scribbles high reflecting material usually, as Ag, absorbs to reduce.For avoiding short circuit, the exposed part of not laying electrode or wire welding area around the above-mentioned support also can apply one deck dielectric film, as silica and silicon nitride etc.
As Fig. 7 a, shown in the 7b, it is the execution mode of the luminous chip package structure of the another kind of the present invention band radiator structure that is used for LED encapsulation, comprise bottom substrate 701, insulating barrier 702a and 702b, bilevel substrate 703, the crystal bonding area that on bottom substrate 701, is provided with, be arranged on led chip 706 on the crystal bonding area by solid crystalline substance, the substrate wire welding area 704a and the 704b that are connected with led chip 706, metal lead wire 705a and 705b, the electrode of substrate 707a that links to each other with extraneous power supply or/and signaling interface, 707b, 707c, 707d, 707e, and 707f, fixed via 708a, 708b, 708c and 708d, top thermal column array 711, thermal column array base palte 711a, the inboard embedding district cofferdam 711b of thermal column array, heat radiation groove 712 in the 701 periphery settings of bottom substrate, the heat radiation groove array 713 that bottom substrate 701 bottom surfaces are provided with, with led chip below heat sink 714.The madial wall 710a of bilevel substrate 703, the madial wall 711c of cofferdam 711b, the upper surface of crystal bonding area etc. have surrounded embedding bright dipping space 709 jointly.
The embodiment of Fig. 7 a, 7b is to have the bilevel substrate 703 of a through hole to be placed on the bottom substrate 701 central authorities, is provided with an insulating barrier 702a between the two.Bottom substrate 701 and bilevel substrate 703 adopt good heat conduction of tool and good conductive metallic material usually, as copper, aluminium, tungsten, molybdenum and other metal material or their alloy, generally are superimposed in the form of sheets; Certainly, also can adopt insulating material to make, get final product and make conductive film on the surface of insulated substrate.Usually the thickness of single substrate is between between hundreds of micron and several millimeters.Single substrate also can adopt the sandwich construction that is made of above-mentioned material.
Insulating barrier 702a adopts oxide or nitride film material usually, as silica and silicon nitride etc.Usually its thickness is between between several microns and the hundreds of micron.Be the adhesion strength between reinforced insulation layer 702a and bottom substrate 701 and the bilevel substrate 703, between insulating barrier 702a and bottom substrate 701 and bilevel substrate 703, be provided with the metallic film that improves adhesion strength usually, for example adopt the alloy-layer formed such as metal materials such as titanium, nickel and tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.
Heat-radiating substrate 711a in Fig. 7 a, the 7b embodiment is placed on the bilevel substrate 703, is provided with an insulating barrier 702b between two substrates.Heat-radiating substrate 711a is provided with thermal column array 711 (the thermal column array in upper right 1/4th districts wherein of only having illustrated picture among Fig. 7 b, omitted the thermal column array of remainder), it is inboard to be embedding district cofferdam 711b, and there is cofferdam madial wall 711c the inboard, cofferdam.Heat-radiating substrate 711a, thermal column array 711 and embedding district cofferdam 711b adopt good heat conductive metal material of tool or nonmetallic materials to make, and form radiator structure, dispel the heat.The diameter of common single thermal column, height and thermal column spacing are between between hundreds of micron and several millimeters.If heat-radiating substrate is an insulating material, insulating barrier 702b just can omit.
Insulating barrier 702b is arranged between heat-radiating substrate 711a and the bilevel substrate 703, adopts oxide or nitride film material usually, and as silica and silicon nitride etc., its thickness is between between several microns and the hundreds of micron usually.Be the adhesion strength between reinforced insulation layer 702b and heat-radiating substrate 711a and the bilevel substrate 703, between insulating barrier 702b and heat-radiating substrate 711a and bilevel substrate 703, be provided with the metallic film that improves adhesion strength usually, usually adopt the alloy-layer formed such as metal material such as titanium, nickel and tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.
Understandable, also insulating barrier 702b can be set in Fig. 7 a, the 7b embodiment, with top thermal column array 711, thermal column array base palte 711a, the inboard embedding district cofferdam 711b of thermal column array, the inboard embedding district cofferdam inwall 711c of thermal column array are set directly on the bilevel substrate 703, also can directly prepare a top of the trellis thermal column array 711, thermal column array base palte 711a, the inboard embedding district cofferdam 711b of thermal column array, the inboard embedding district cofferdam madial wall 711c of thermal column array on the bilevel substrate 703 of thickening.Thermal column array base palte 711a also can stick on the bilevel substrate 703 by the way of pasting.
Bottom substrate 701 in Fig. 7 a, the 7b embodiment provides again and chip and an extraneous group substrate electrode 707a and a 707b not only as the basis of luminous chip package structure simultaneously, and bottom substrate 701 itself has the function of conductive electrode concurrently.The center through hole sidewall of bilevel substrate 703 not only provides optical channel, reflective side surfaces for the chip 706 that is placed on the bottom substrate 701, also provide and a led chip and an extraneous group substrate electrode 707e, 707f, 707c and 707d, bilevel substrate 703 itself has the function of conductive electrode concurrently.Two electrodes of led chip are electrically connected with the electrode of substrate of bottom substrate 701 and bilevel substrate 703 respectively by metal lead wire.
The endoporus of bilevel substrate 703 central authorities has formed the bottom in embedding bright dipping space 709, and the inboard embedding district cofferdam madial wall 711c of thermal column array has formed the top in embedding bright dipping space 709.Embedding bright dipping space about in the of 709 two ones can pour into identical or different light transmission encapsulating material.The perfusion of following embedding district contains the silica gel of fluorescent material and silica gel is poured in last embedding district or epoxy resin then can be prepared common described white light LEDs.By the surface structure of the inboard embedding district cofferdam 711b of improvement bottom substrate 701 bilevel substrates 703 and thermal column array, but above embedding district 709 other light transmission encapsulating material of embedding and/or place all kinds of preformed lens or other optics also.Bottom substrate 701, bilevel substrate 703 and thermal column array base palte 711a can have identical or different profile, and size, and thickness are for example up-small and down-big usually, adopt square, rectangle or circle, and thickness in monolayer is between the hundreds of micron is to several millimeters.
The bottom that the top, embedding district that the inboard embedding district cofferdam madial wall 711c of thermal column array in Fig. 7 a, the 7b embodiment forms and the center through hole sidewall 710a of bilevel substrate 703 form can be symmetrical or asymmetric, similar and different shape, thereby realize different light shape and light intensity distributions, for example adopt square, rectangle, ellipse, circle or other shape.Between center through hole sidewall 710a and bottom substrate 701 surfaces, can become vertical or bevel between the ledge surface of the inboard embedding district cofferdam madial wall 711c of thermal column array and bilevel substrate 703, the inboard embedding district cofferdam madial wall 711c of center through hole sidewall 710a and thermal column array itself can be smooth flat or smooth cambered surface, in order to the distribution of light in the control embedding district 709, then change light extraction efficiency, light shape and light intensity distributions.Usually, madial wall 711c surface, cofferdam, the inboard embedding district of center through hole sidewall 710a and thermal column array scribbles high reflecting material, as Ag.The exposed part that bottom substrate 701 and bilevel substrate 703 are not laid electrode or wire welding area also scribbles high reflecting material usually, as Ag, absorbs to reduce.For avoiding short circuit, the exposed part of not laying electrode or wire welding area around the above-mentioned support also can apply one deck dielectric film, as silica and silicon nitride etc.
Further, the bottom of bottom substrate 701 is provided with heat radiation groove array 713, and is positioned at led chip 706 belows and is provided with good heat conduction as heat sink 714.Width, the degree of depth and the flute pitch of heat radiation groove array 713 is between between hundreds of micron and several millimeters.The heat radiation groove array of cross arrangement can form the thermal column array, further increases area of dissipation.Be the contact area of enhancing, avoid in the contact zone, forming the cavity that above-mentioned heat radiation groove array 713 can be arranged on the bottom base lower surface that does not contact with other parts or cooling mechanism with other parts or cooling mechanism; And heat radiation groove array 713 can be arranged in different shape.With bottom substrate that other parts or cooling mechanism contact under can add heat sink 714 of tool good heat conductive performance usually.
As Fig. 8 a, shown in the 8b, it is the integrated luminous chip package structure of band radiator structure multicore sheet of a kind of LED of being used for encapsulation of the present invention, comprise bottom substrate 801, the crystal bonding area 801a that base plate central authorities are provided with, insulating barrier 802a, 802b, 802c, 802d, 802e and 802f, four bilevel substrate 803a, 803b, 803c and 803d, be arranged on led chip 806a on the crystal bonding area by solid crystalline substance, 806b, 806c and 806d, metal lead wire 805, the electrode of substrate 807a that links to each other with extraneous power supply or/and signaling interface, 807b, 807c, 807d, 807e, 807f, 807g and 807h, fixed via 808a, 808b, 808c and 808d, cofferdam, top, embedding district 812.On four bilevel substrates, be respectively equipped with exposed wire welding area 811a, 811b, 811c and 811d.The upper surface of crystal bonding area, four corresponding oblique sidewall 810a of bilevel substrate, 810b, 810c and 810d and cofferdam, top, embedding district madial wall 813 surround embedding bright dipping space 809 jointly, for the led chip bright dipping that is arranged on crystal bonding area.On cofferdam, top, embedding district 812, be provided with thermal column array 814, thereby improve radiating efficiency.
The embodiment of Fig. 8 a, 8b is with four square bilevel substrate 803a, and 803b, 803c and 803d are placed on the circular bottom substrate 801, are provided with an insulating barrier 802a between two substrates.Bottom substrate 801 and bilevel substrate 803a, 803b, 803c and 803d adopt good heat conduction of tool and good conductive metallic material usually, as copper, aluminium, tungsten, molybdenum and other metal material or their alloy, generally be superimposed in the form of sheets, usually the thickness of single substrate is between between hundreds of micron and several millimeters.Single substrate also can adopt the sandwich construction that is made of above-mentioned material.
Insulating barrier 802a is arranged on bottom substrate 801 and bilevel substrate 803a, and 803b between 803c and the 803d, adopts oxide or nitride film material, usually as silica and silicon nitride etc.Usually its thickness is between between several microns and the hundreds of micron.Be reinforced insulation layer 802a and bottom substrate 801 and bilevel substrate 803a, 803b, adhesion strength between 803c and the 803d, at insulating barrier 802a and bottom substrate 801 and bilevel substrate 803a, 803b, usually be provided with the metallic film that improves adhesion strength between 803c and the 803d, usually adopt the alloy-layer formed such as metal material such as titanium, nickel and tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.
Four bilevel substrate 803a, 803b is provided with insulating tape 802c, 802d, 802e and a 802f between 803c and the 803d.Insulating barrier 802c, 802d, 802e and 802f adopt oxide film material or nitride film material or inorganic non-metallic insulating material usually or are provided with that the light transmission encapsulating material of common insulation is inserted in a space automatically in by follow-up embedding process or embed the inorganic non-metallic insulating material in the space.Usually its thickness or space are between between several microns and the hundreds of micron.Be reinforced insulation layer 802c, 802d, 802e and 802f and bilevel substrate 803a, 803b, the adhesion strength between 803c and the 803d is at insulating barrier 802a and bilevel substrate 803a, 803b, usually be provided with the metallic film that improves adhesion strength between 803c and the 803d, usually adopt the alloy-layer formed such as metal material such as titanium, nickel and tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.
Four bilevel substrate 803a, 803b, 803c and 803d inboard are provided with oblique sidewall 810a, 810b, 810c and 810d and exposed wire welding area 811a, 811b, 811c and 811d. Oblique sidewall 810a, 810b, 810c and 810d surround 809 bottoms, embedding bright dipping space.Bottom substrate 801 and bilevel substrate 803a, 803b, 803c has the electrode of substrate 807a that links to each other with extraneous power supply or/and signaling interface, 807b with the 803d arranged outside, 807c, 807d, 807e, 807f, 807g and 807h, bottom substrate 801 arranged outside fixed via 808a, 808b, 808c and 808d.
Cofferdam, top, embedding district 812 is arranged on bilevel substrate 803a, and 803b is on 803c and the 803d.Cofferdam, top, embedding district 812 is adopted good heat conductive metal material of tool or ceramic material usually, and wherein metal material can be copper, aluminium, tungsten, molybdenum and other metal material or their alloy.Cofferdam, top, embedding district 812 and bilevel substrate 803a, 803b, 803c and 803d generally are superimposed in the form of sheets.Usually the thickness in cofferdam, top, embedding district 812 is between between hundreds of micron and several millimeters.If cofferdam, top, embedding district 812 is a conductive material, cofferdam, top, embedding district 812 and bilevel substrate 803a, 803b is provided with an insulating barrier 802b between 803c and the 803d.Insulating barrier 802b adopts oxide or nitride film material usually, as silica and silicon nitride etc.Usually its thickness is between between several microns and the hundreds of micron.Be reinforced insulation floor 802b and cofferdam, top, embedding district 812 and bilevel substrate 803a, 803b, adhesion strength between 803c and the 803d, at insulating barrier 802b and cofferdam, top, embedding district 812 and bilevel substrate 803a, 803b, usually be provided with the film that improves adhesion strength between 803c and the 803d, usually adopt the alloy-layer formed such as metal material such as titanium, nickel and tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.If cofferdam, top, embedding district 812 is non-conductive material, cofferdam, top, embedding district 812 and bilevel substrate 803a, 803b, be provided with the metallic film that improves adhesion strength between 803c and the 803d, usually adopt the alloy-layer formed such as metal material such as titanium, nickel and tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.Cofferdam, top, embedding district 812 also can stick on bilevel substrate 803a by the way of pasting, and 803b is on 803c and the 803d.
Cofferdam, top, embedding district 812 madial walls 813 surround the top in embedding bright dipping space 809.812 tops, cofferdam, top, embedding district also are provided with thermal column array 814, to increase area of dissipation.The diameter of common single thermal column, height and thermal column spacing are between between hundreds of micron and several millimeters.
Four groups of led chip 806a, 806b, 806c and 806d (two every group) are placed on the crystal bonding area 801a of bottom substrate 801, and wherein the crystal bonding area 801a surface of bottom substrate 801 is provided with solid brilliant material.Led chip 806a, 806b, the wherein electrode of 806c and 806d all are connected with wire welding area on the crystal bonding area 801a of bottom substrate 801, another electrode respectively with bilevel substrate 803a, 803b, the exposed wire welding area 811a of 803c and 803d, 811b, 811c and 811d join, form four groups of led chip 806a, 806b, 806c and 806d be male or female altogether, but the connected mode of different negative electrode or anode.Chip is for being connected in parallel in the group.Every group of chip that a different number can be arranged of practical application, chip also can be gone here and there or and or string and combination in the group.Four groups of chipsets can identically also can be different chips.If adopt one red one green one a red Huang, then can produce the full-color display dot of high-quality.
Oblique sidewall 810a in the bilevel substrate in Fig. 8 a, the 8b embodiment, 810b, 810c and 810d have formed 809 bottoms, embedding bright dipping space, and cofferdam, top, embedding district madial wall 813 has formed top, 809 bottom, embedding bright dipping space.Identical or different light transmission encapsulating material can be poured in two districts about in the of 809 in embedding bright dipping space.Contain the silica gel of fluorescent material and silica gel is poured in 809 Shang Er districts, embedding bright dipping space or epoxy resin then can be prepared common described white light LEDs as 809 Xia Er districts, embedding bright dipping space perfusions.By the surface structure in improvement cofferdam, top, embedding district 812, but above embedding district 809 other light transmission encapsulating material of embedding and/or place all kinds of preformed lens or other optics also.801, four bilevel substrate 803a of bottom substrate, 803b, the profile that 803c and 803d surround, the profile in cofferdam, top, embedding district 812 can be identical or different, and size can be the same or different.For example adopt square, rectangle, circle or other shape.
Oblique sidewall 810a in the bilevel substrate in Fig. 8 a, the 8b embodiment, 810b, 810c and 810d have formed 809 bottoms, embedding bright dipping space, it can be symmetrical or asymmetric, similar and different shape that cofferdam, top, embedding district madial wall 813 has formed 809 tops, embedding bright dipping space, thereby realize different light shape and light intensity distributions, for example adopt square, rectangle, ellipse, circle or other shape.Oblique sidewall 810a in the bilevel substrate, 810b, between 810c and 810d and bottom substrate 801 surfaces and cofferdam, top, embedding district madial wall 813 and bilevel substrate 803a, 803b, the exposed wire welding area 811a of 803c and 803d, 811b, can become vertical or bevel between 811c and the 811d surface, oblique sidewall 810a in the bilevel substrate, 810b, 810c and 810d and cofferdam, top, embedding district madial wall 813 itself can be smooth flat or smooth cambered surface, in order to the distribution of light in the control embedding district 809, then change light extraction efficiency, light shape and light intensity distributions.Oblique sidewall 810a in the common above-mentioned bilevel substrate, 810b, 810c and 810d and madial wall 813 surfaces, cofferdam, top, embedding district scribble high reflecting material, as Ag.Bottom substrate 801, bilevel substrate 803a, 803b, the exposed part that electrode or wire welding area are not laid in 803c and 803d and cofferdam, top, embedding district 812 also scribbles high reflecting material usually, as Ag, absorbs to reduce.For avoiding short circuit, the exposed part of not laying electrode or wire welding area around the above-mentioned support also can apply one deck dielectric film, as silica and silicon nitride etc.
Shown in Fig. 9 a, 9b, be the execution mode that another kind of the present invention is used for the chip-packaging structure of LED encapsulation, the crystal bonding area that comprises submounts 901 and 902, on submounts 901 and/or 902, is provided with, be arranged on led chip 906 on the crystal bonding area, at submounts 901 and 902 wire welding area and electrode of substrate 904a and 904b, metal lead wire 905a and 905b be set respectively by solid crystalline substance.
In the present embodiment, submounts 901 and 902 is non-conductive submounts, for example adopts ceramic substrate etc., forms the single layer substrate unit by splicing mutually in the horizontal direction.Simultaneously, realize between wire welding area and electrode of substrate 904a and the 904b that in order to make conduction is connected, can make conductive metal film at the upper surface of submounts 901 and 902, for example adopt the alloy-layer formed such as metal materials such as titanium, nickel and tungsten or by above-mentioned metal or by the sandwich construction of above-mentioned metal and alloy composition, its thickness is between tens nanometers and hundreds of nanometer usually.
Further, crystal bonding area can be as required be provided with arbitrarily on submounts 901 and 902, the pit that is provided with at the submounts upper surface etc. for example, and pit itself has constituted the embedding bright dipping space of luminescence chip.Certainly, the cofferdam of projection can also be set around pit, form better embedding bright dipping space.
Understandable, the architectural feature of the foregoing description can be carried out combination in any as required and be formed new execution mode, and protection scope of the present invention is not limited to above-mentioned execution mode, should be the combination in any of said structure feature.
Owing to do not comprise any macromolecular material in the above-mentioned luminous chip package structure, its ultraviolet light irradiation and high/low-temperature impact are very capable, substantially be not subjected to the influence of environment, improved the reliability of LED greatly, above-mentioned luminous chip package structure can bear 200 ℃ of temperature more than-500 ℃, makes led chip to be fixed on the bottom substrate by the eutectic welding technology.The base base plate is fixed on other parts or the cooling mechanism with screw by fixed via again, reaches very good heat dissipation channel.If energy pad heat radiation adhesives between bottom substrate and other parts or cooling mechanism, then its heat dispersion will be better.Big electric current or high-power following, because interface resistance is very low, entire bracket is again a Metal Substrate good conductor, and making led chip produce heat can conduct out rapidly, it is minimum that the interior heat localization of led support has been dropped to, thereby improved the anti-attenuation and the reliability of led chip greatly.In addition, this encapsulating structure also can be applied to the encapsulation of other luminescence chip except being applied to the encapsulation of led chip.

Claims (15)

1. luminous chip package structure, it is characterized in that, comprise at least one base board unit, at least one at the crystal bonding area that is provided with on the described base board unit, be installed at least one luminescence chip on the described crystal bonding area and on described base board unit, be provided with mutually isolated at least two and can realize the electrode of substrate that conduction be connected with the external world; Described base board unit comprises at least two submounts insulated from each other; Described luminescence chip is electrically connected with described electrode of substrate by described base board unit.
2. luminous chip package structure according to claim 1, it is characterized in that, described submounts is the conduction submounts, between adjacent described conduction submounts, be provided with insulating barrier or insulating tape, perhaps, between adjacent described conduction submounts, leave the space, perhaps, in described space, fill insulating encapsulating material; Perhaps,
Described submounts is non-conductive submounts, is provided with the conductive metal film that described luminescence chip is electrically connected to corresponding described electrode of substrate on described non-conductive submounts; Perhaps,
Described submounts comprises conduction submounts and non-conductive submounts, is provided with the conductive metal film that described luminescence chip is electrically connected to corresponding described electrode of substrate on described non-conductive submounts.
3. luminous chip package structure according to claim 1 is characterized in that described base board unit is the single layer substrate unit, comprises at least two described submounts insulated from each other and that splice mutually in the horizontal direction; Perhaps,
Described base board unit is the multilager base plate unit, comprise at least two insulated from each other and at the described submounts of vertical direction mutual superposition; Perhaps,
Described base board unit is the MULTILAYER COMPOSITE base board unit, comprises at least one described submounts and at least one described single layer substrate unit, and described submounts and described single layer substrate unit are insulated from each other and in the vertical direction mutual superposition; Described single layer substrate unit comprises at least two described submounts insulated from each other and that splice mutually in the horizontal direction.
4. luminous chip package structure according to claim 3, it is characterized in that, described crystal bonding area all is arranged on the same described submounts that constitutes described single layer substrate unit, or is separately positioned on the different described submounts that constitutes described single layer substrate unit.
5. luminous chip package structure according to claim 3, it is characterized in that, described crystal bonding area all is arranged on the same described submounts that constitutes described multilager base plate unit, or is separately positioned on the different described submounts that constitutes described multilager base plate unit; Perhaps,
Described crystal bonding area all is arranged on the same described submounts that constitutes described MULTILAYER COMPOSITE base board unit, or is separately positioned on the different described submounts that constitutes described MULTILAYER COMPOSITE base board unit.
6. luminous chip package structure according to claim 5, it is characterized in that, described crystal bonding area is arranged on the described submounts of non-top layer, the described submounts that is positioned at the described submounts upper strata that described crystal bonding area is set is provided with and the corresponding opening of described crystal bonding area, and the madial wall of described opening constitutes embedding bright dipping space and the reflective sidewall that is placed on described luminescence chip in the described crystal bonding area.
7. according to claim 4,5 or 6 described luminous chip package structures, it is characterized in that described crystal bonding area is arranged on the upper surface of described submounts; Perhaps, be positioned at the pit that described submounts surface is provided with, the madial wall of described pit constitutes embedding bright dipping space and the reflective sidewall that is placed on described luminescence chip in the described crystal bonding area.
8. luminous chip package structure according to claim 7 is characterized in that, is provided with the cofferdam of projection around the described crystal bonding area; The madial wall in described cofferdam constitutes embedding bright dipping space and the reflective sidewall that is placed on described luminescence chip in the described crystal bonding area.
9. luminous chip package structure according to claim 7 is characterized in that, the madial wall in described crystal bonding area surface, described embedding bright dipping space can apply the metallic reflective coating and/or the nonmetal reflectance coating of single or multiple lift.
10. luminous chip package structure according to claim 7, it is characterized in that, the madial wall in described embedding bright dipping space comprise become with the smooth surface of described crystal bonding area Surface Vertical and/or with described crystal bonding area surface greater than the smooth bevel of 90 degree angles and/or from described crystal bonding area surface to the smooth cambered surfaces of described base board unit surface extension.
11. luminous chip package structure according to claim 7, it is characterized in that, the madial wall in described embedding bright dipping space comprises at least one ladder, and the horizontal segment surface of described ladder is arranged on the described submounts surface with described crystal bonding area or has on the described submounts of described submounts top of described crystal bonding area.
12. luminous chip package structure according to claim 1 is characterized in that, described luminescence chip is placed on the central authorities of described crystal bonding area, and conduction is connected to corresponding electrode of substrate respectively; Perhaps, described luminescence chip is a plurality of, conducts electricity respectively after some described luminescence chip serial or parallel connections or the connection in series-parallel to be connected to corresponding electrode of substrate again.
13. luminous chip package structure according to claim 1, it is characterized in that, be provided with respectively the wire welding area that conduction is connected to corresponding described electrode of substrate near the described crystal bonding area, described luminescence chip conducts electricity respectively and is connected to corresponding described wire welding area, or after wherein some described luminescence chip serial or parallel connections or the connection in series-parallel more respectively conduction be connected to corresponding wire welding area.
14. luminous chip package structure according to claim 1, it is characterized in that, the exposed surface of described base board unit is provided with the radiator structure that increases cooling surface area and/or is coated with heat sink material, and described heat sink material has the surface heat radianting capacity of increasing and/or capacity of heat transmission.
15. luminous chip package structure according to claim 2 is characterized in that, described insulating barrier is one or more layers compound inslation film; Be provided with one or more layers transiting metal film and/or alloy firm between described insulating barrier and the described submounts.
CN2010102607557A 2010-08-13 2010-08-13 Light-emitting chip packaging structure Pending CN101958390A (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012135976A1 (en) * 2011-04-07 2012-10-11 Cree Huizhou Solid State Lighting Company Limited Led device having tilted peak emission and led display including such devices
US8487326B2 (en) 2006-04-24 2013-07-16 Cree, Inc. LED device having a tilted peak emission and an LED display including such devices
WO2015188383A1 (en) * 2014-06-13 2015-12-17 Dow Corning Corporation Electrical device including an insert
WO2015188384A1 (en) * 2014-06-13 2015-12-17 Dow Corning Corporation Electrical device including an insert
CN105353222A (en) * 2015-09-25 2016-02-24 南京剑桥新港科技发展有限公司 Diversified integrated impedance detection device based on disposable thin film electrode
CN109713107A (en) * 2018-12-13 2019-05-03 佛山市国星光电股份有限公司 Supporting structure, LED component and lamp group array
CN110473944A (en) * 2018-05-09 2019-11-19 深圳市聚飞光电股份有限公司 Multipurpose LED support and LED
CN112071829A (en) * 2020-08-12 2020-12-11 深圳奥比中光科技有限公司 Common anode multi-area emission module and depth camera
US11210971B2 (en) 2009-07-06 2021-12-28 Cree Huizhou Solid State Lighting Company Limited Light emitting diode display with tilted peak emission pattern

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1355571A (en) * 2000-11-23 2002-06-26 诠兴开发科技股份有限公司 Packaging method for LED
JP2005012157A (en) * 2003-05-27 2005-01-13 Matsushita Electric Works Ltd Method of manufacturing highly heat-conductive circuit component
US20050139855A1 (en) * 2003-10-31 2005-06-30 Harvatek Corporation Package structure for semiconductor
JP2006156704A (en) * 2004-11-30 2006-06-15 Nichia Chem Ind Ltd Resin molding and surface-mounted light emitting device, and manufacturing method thereof
CN2814676Y (en) * 2005-06-03 2006-09-06 明达光电(厦门)有限公司 Light-emitting diode packaging structure with groove substrate
CN101313415A (en) * 2005-11-21 2008-11-26 松下电工株式会社 Light-emitting device
CN101546737A (en) * 2008-03-25 2009-09-30 先进开发光电股份有限公司 Package structure of compound semiconductor component and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1355571A (en) * 2000-11-23 2002-06-26 诠兴开发科技股份有限公司 Packaging method for LED
JP2005012157A (en) * 2003-05-27 2005-01-13 Matsushita Electric Works Ltd Method of manufacturing highly heat-conductive circuit component
US20050139855A1 (en) * 2003-10-31 2005-06-30 Harvatek Corporation Package structure for semiconductor
JP2006156704A (en) * 2004-11-30 2006-06-15 Nichia Chem Ind Ltd Resin molding and surface-mounted light emitting device, and manufacturing method thereof
CN2814676Y (en) * 2005-06-03 2006-09-06 明达光电(厦门)有限公司 Light-emitting diode packaging structure with groove substrate
CN101313415A (en) * 2005-11-21 2008-11-26 松下电工株式会社 Light-emitting device
CN101546737A (en) * 2008-03-25 2009-09-30 先进开发光电股份有限公司 Package structure of compound semiconductor component and manufacturing method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8487326B2 (en) 2006-04-24 2013-07-16 Cree, Inc. LED device having a tilted peak emission and an LED display including such devices
US11210971B2 (en) 2009-07-06 2021-12-28 Cree Huizhou Solid State Lighting Company Limited Light emitting diode display with tilted peak emission pattern
WO2012135976A1 (en) * 2011-04-07 2012-10-11 Cree Huizhou Solid State Lighting Company Limited Led device having tilted peak emission and led display including such devices
WO2015188383A1 (en) * 2014-06-13 2015-12-17 Dow Corning Corporation Electrical device including an insert
WO2015188384A1 (en) * 2014-06-13 2015-12-17 Dow Corning Corporation Electrical device including an insert
CN105353222A (en) * 2015-09-25 2016-02-24 南京剑桥新港科技发展有限公司 Diversified integrated impedance detection device based on disposable thin film electrode
CN105353222B (en) * 2015-09-25 2018-07-17 南京剑桥新港科技发展有限公司 Diversified integrated impedance detection device based on disposable thin film electrode
CN110473944A (en) * 2018-05-09 2019-11-19 深圳市聚飞光电股份有限公司 Multipurpose LED support and LED
CN109713107A (en) * 2018-12-13 2019-05-03 佛山市国星光电股份有限公司 Supporting structure, LED component and lamp group array
CN112071829A (en) * 2020-08-12 2020-12-11 深圳奥比中光科技有限公司 Common anode multi-area emission module and depth camera

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