CN101546737A - Package structure of compound semiconductor component and manufacturing method thereof - Google Patents

Package structure of compound semiconductor component and manufacturing method thereof Download PDF

Info

Publication number
CN101546737A
CN101546737A CN200810086311A CN200810086311A CN101546737A CN 101546737 A CN101546737 A CN 101546737A CN 200810086311 A CN200810086311 A CN 200810086311A CN 200810086311 A CN200810086311 A CN 200810086311A CN 101546737 A CN101546737 A CN 101546737A
Authority
CN
China
Prior art keywords
conducting film
crystal grain
groove
film
conducting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200810086311A
Other languages
Chinese (zh)
Other versions
CN101546737B (en
Inventor
陈滨全
林升柏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhanjing Technology Shenzhen Co Ltd
Advanced Optoelectronic Technology Inc
Original Assignee
ADVANCED DEVELOPMENT PHOTOELECTRIC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ADVANCED DEVELOPMENT PHOTOELECTRIC Co Ltd filed Critical ADVANCED DEVELOPMENT PHOTOELECTRIC Co Ltd
Priority to CN200810086311A priority Critical patent/CN101546737B/en
Publication of CN101546737A publication Critical patent/CN101546737A/en
Application granted granted Critical
Publication of CN101546737B publication Critical patent/CN101546737B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

The invention discloses a package structure of a compound semiconductor component and a manufacturing method thereof. The package structure comprises a film substrate, a crystal grain, at least one metal conducting wire and a transparent adhesive material, wherein the film substrate comprises a first conducting film, a second conducting film and a dielectric insulating material; the crystal grain is fixed on the surface of the first conducting film and is electrically connected with the first conducting film or the second conducting film through the metal conducting wire; the transparent adhesive material covers on the first conducting film, the second conducting film and the crystal grain; the first conducting film and the second conducting film are taken as electrodes relative to the surface of the transparent adhesive material; and the dielectric insulating material is arranged between the first conducting film and the second conducting film. The package structure makes the thickness of the component thinner to save the occupied space and solves the problem of poor heat radiation.

Description

The encapsulating structure of compound semiconductor element and manufacture method thereof
Technical field
The present invention relates to a kind of encapsulating structure and manufacture method thereof of compound semiconductor element, relate in particular to a kind of slim encapsulating structure and manufacture method thereof of optoelectronic semiconductor component.
Background technology
Because light-emitting diode (light emitting diode in the photoelectric cell; LED) have that volume is little, luminous efficiency is high and an advantage such as the life-span is long, therefore be considered to the best light source of second generation green energy conservation illumination.The fashion trend of the fast-developing and full-color screen of LCD in addition, make the white light series LED except being applied to purposes such as indicator light and large display screen curtain, more cut vast consumption electronic products, for example: mobile phone and PDA(Personal Digital Assistant).
Fig. 1 is the generalized section of the light-emitting diode of known surface adhesion (SMD) element.LED crystal particle 12 is fixed in the surface that insulating barrier 13c goes up N type copper-foil conducting electricity 13b by crystal-bonding adhesive 11, and link to each other by plain conductor 15 and P-type conduction Copper Foil 13a and N type copper-foil conducting electricity 13b electricity, wherein P-type conduction Copper Foil 13a, N type copper-foil conducting electricity 13b and insulating barrier 13c formation has the substrate 13 of circuit.In addition, transparent adhesive material 14 is covered on substrate 13, plain conductor 15 and the crystal grain 12, can protect whole light-emitting diode 10 not to be subjected to environment and damage of external force.
Light-emitting diode 10 uses general printed circuit board (PCB) as substrate 13, thus its integral thickness insulating barrier 13c thickness can't be thinner in the substrate 13 because of being subject to.But consumption electronic products trend towards gently, thin, short, little external form, so each element of its inside or external shell all need miniaturization.On the other hand, insulating barrier 13c mostly is the relatively poor resin material of thermal diffusivity and makes, and therefore is unfavorable for the heat radiation approach of high-power light emitting compound semiconductor element as the conduction heat.
Fig. 2 is the generalized section that U.S.'s publication discloses high integrated encapsulation structure for US20040090756 number.This kind structure is being coated with layer of cloth on temporary transient base material, and the circuit that design and layout go out to need on insulating barrier.Then, LED crystal particle 221,222 is adhered on the substrate 23, and utilizes routing technology (or flip-chip (flip chip)) technology that crystal grain 221,222 and substrate 23 inner leads are passed through plain conductor 25 mutual conduction.Crystal grain 221,222 tops utilize mold pressing (molding) technology that traditional epoxy resin (epoxy) is covered on the crystal grain 221,222.In order to make whole chip reach slimming, utilize temporary transient base material laser or ultraviolet light (UV) rayed that it is separated with insulating barrier, and the tin ball 26 of on the pad of reserving, adhering, so can reach high integration and purpose of thinness.But this technology is comparatively complicated, and also can increase cost.
In sum, need a kind of slim photoelectricity compound semiconductor element on the market badly, will be thinner except the thickness of element and can save institute takes up space, and to improve the problem of poor heat radiation, with the more favourable making that is applied to high-power components.
Summary of the invention
The invention provides a kind of encapsulating structure and manufacture method thereof of compound semiconductor element, this semiconductor element directly is exposed to adhesive material with outer electrode or contact, and do not need printed circuit board (PCB) between between crystal grain and outer electrode, to transmit electric signal, therefore can improve the problem of poor heat radiation.
The invention provides a kind of encapsulating structure and manufacture method thereof of ultrathin semiconductor element owing to use thin base or metallic diaphragm, so the thickness of this element can be thinner and can save take up space.
For achieving the above object, the present invention discloses a kind of encapsulating structure of compound semiconductor element, and it comprises film substrate, crystal grain and transparent adhesive material.This film substrate comprises first conducting film, second conducting film and insulative dielectric material.This crystal grain is fixed in the surface of this first conducting film.This transparent adhesive material is covered on this first conducting film, this second conducting film and this crystal grain.Respectively as electrode, this insulative dielectric material is between this first conducting film and this second conducting film with respect to the surface of this transparent sealing for this first conducting film and this second conducting film.
The thickness of this film substrate is preferably 20～50 μ m.
This insulative dielectric material is silica (SiO), silicon nitride (SiN), silicon oxynitride (SiON), tantalum oxide (TaO), aluminium oxide (AlO), titanium oxide (TiO), aluminium nitride (AlN), titanium nitride (TiN), epoxy resin (epoxy), silicones (silicone) or insulating polymeric material.
This crystal grain can be LED crystal particle, laser diode or light sensing crystal grain.
The encapsulating structure of this compound semiconductor element also comprises at least one plain conductor that is electrically connected this crystal grain and this film substrate.This first conducting film also comprises can be for the first routing groove of this plain conductor welding.In addition, also comprise can be for the second routing groove of this plain conductor welding for this second conducting film.
The encapsulating structure of this compound semiconductor element also comprises the projection of this crystal grain of a plurality of electrical connections and this film substrate.
This first conducting film also comprises solid brilliant groove, and this crystal grain is fixed in this solid brilliant groove.Should cover reflector layer in the solid brilliant groove.
The encapsulating structure of this compound semiconductor element also comprises the insulation material layer that is patterned that is stacked and placed on this film substrate, and wherein comprise can be for the routing groove of this plain conductor welding for the fixing solid brilliant groove of this crystal grain and at least one for this insulation material layer.
The present invention also discloses a kind of manufacture method of compound semiconductor element encapsulating structure, comprises the following step: film substrate is provided, and it comprises first conducting film, second conducting film and insulative dielectric material; Crystal grain is fixed on this first conducting film, make the positive electrical of this crystal grain be connected to this first conducting film, and the negative electricity of this crystal grain is connected to this second conducting film; And the transparent adhesive tape material coated this crystal grain.
This film substrate is made by the following step: thin plate is provided; On this thin plate, form at least one groove to separate this first conducting film and this second conducting film; And in this groove, insert the insulative dielectric material.
This groove utilizes bore process, etch process or metal stamping technology and forms.
This manufacture method also is contained in the step that this first conducting film forms solid brilliant groove.
This manufacture method also is contained in the step that this first conducting film and this second conducting film form a plurality of routing grooves, and wherein this routing groove is to supply at least one plain conductor welding part.
This manufacture method also is contained in the stacked insulation material layer that is patterned on this film substrate, and wherein this insulation material layer comprises the solid brilliant groove of fixing for this crystal grain and can supply a plurality of routing grooves of at least one plain conductor welding.
This step that this crystal grain is fixed in this film substrate comprises with routing and engages or the flip-chip juncture is electrically connected to this film substrate with this crystal grain.
Admittedly brilliant groove or this routing groove form by photoetching etching, electroforming process or bore process.
The present invention can make the thickness of element thinner and save institute and take up space, and solves the problem of poor heat radiation.
Description of drawings
Fig. 1 is the generalized section of the light-emitting diode of known surface adhesion (SMD) element;
Fig. 2 is the generalized section of US20040090756 number disclosed high integrated encapsulation structure of U.S.'s publication;
Fig. 3 A-Fig. 3 C is the step of manufacturing schematic diagram of film substrate of the present invention;
Fig. 4 A is the generalized section of The compounds of this invention semiconductor component packaging structure;
Fig. 4 B is the vertical view of the compound semiconductor element of Fig. 4 A;
Fig. 5 is the generalized section of another embodiment of the present invention compound semiconductor element encapsulating structure;
Fig. 6 is the generalized section of yet another embodiment of the invention compound semiconductor element encapsulating structure;
Fig. 7 is the generalized section of yet another embodiment of the invention compound semiconductor element encapsulating structure;
Fig. 8 is the generalized section of yet another embodiment of the invention compound semiconductor element encapsulating structure; And
Fig. 9 A-Fig. 9 D forms the schematic diagram of solid brilliant groove or routing groove for the present invention adopts electroforming process.
Wherein, description of reference numerals is as follows:
10 light-emitting diodes
12,221,222 crystal grain
13a P-type conduction Copper Foil
The 13c insulating barrier
15 plain conductors
23 substrates
26 tin balls
31,31 ' the first conducting films
33 grooves
35 insulative dielectric materials
37 metal levels
40 compound semiconductor elements
44 plain conductors
47 crystal-bonding adhesives
50,60,70,80 compound semiconductor elements
54 projections
411 solid brilliant grooves
413,421 routing grooves
Embodiment
Fig. 3 A-Fig. 3 C is the step of manufacturing schematic diagram of film substrate of the present invention.As shown in Figure 3A, it is the thin plate 34 of 20～50 μ m that thickness is provided, for example: the metallic film that Copper Foil or conduction are good.Utilize technologies such as bore process, etch process or metal stamping on thin plate 34, to form groove 33 again, make first conducting film 31 of both sides and second conducting film 32 mutually can't conducting by this groove 33, that is electricity is independent, shown in Fig. 3 B.And in groove 33, insert the making that insulative dielectric material 35 just can be finished film substrate 30, for example: silica (SiO), silicon nitride (SiN), silicon oxynitride (SiON), tantalum oxide (TaO), aluminium oxide (AlO), titanium oxide (TiO), aluminium nitride (AlN), titanium nitride (TiN), epoxy resin (epoxy), silicones (silicone) or insulating polymeric material etc., can increase the rigidity of support of first conducting film 31 and 32 insulating properties of second conducting film and film substrate 30 thus, shown in Fig. 3 C.
Fig. 4 A is the generalized section of The compounds of this invention semiconductor component packaging structure.Compound semiconductor element 40 utilizes solid brilliant or glutinous brilliant (die bonding) technology that compound semiconductor crystal grain 43 is adhered on first conducting film 31 of film substrate 30, that is crystal grain 43 is fixed in the surface of first conducting film 31 by crystal-bonding adhesive 47.This compound semiconductor crystal grain 43 can be LED crystal particle, laser diode crystal grain or light sensing crystal grain.Via plain conductor 44 crystal grain 43 is electrically connected with film substrate 30 again, so film substrate 30 promptly becomes the package carrier of crystal grain 43 and plain conductor 44.Utilize mould pressing process that transparent adhesive material 46 is covered on crystal grain 43, plain conductor 44 and the film substrate 30 at last again, thereby reach the effect of blocks moisture and protection, this transparent adhesive tape material 46 can be epoxy resin (epoxy) or siloxanes (silicone).
Fig. 4 B is the vertical view of the compound semiconductor element of Fig. 4 A.Transparent adhesive material 46 parts are removed, can clearlyer see the connection relationship of crystal grain 43, plain conductor 44 and film substrate 30, two plain conductors 44 extend and connection to first conducting film 31 and second conducting film 32 from crystal grain 43 surfaces respectively.
Fig. 5 is the generalized section of another embodiment of the present invention compound semiconductor element encapsulating structure.Compound semiconductor element 50 utilizes flip-chip technology that crystal grain 43 is fixed on the film substrate 30 by projection (bump) 54.Different with Fig. 4 A, the upset of the active surface of this crystal grain 43 is towards film substrate 30, and utilizes the tin ball to engage with pad on the crystal grain 43 and become projection 54, again through after the reflow then projection 54 understand with film substrate 30 and conduct because of solidifying again after the tin cream melting.Utilize mould pressing process that transparent adhesive material 46 is covered on crystal grain 43 and the film substrate 30 at last again, thereby reach the effect of blocks moisture and protection.The advantage of present embodiment is that current path is short and dispel the heat goodly, compares the bank height (loop height) that previous embodiment can reduce plain conductor.
Fig. 6 is the generalized section of yet another embodiment of the invention compound semiconductor element encapsulating structure.Thickness that present embodiment can further reduce encapsulating structure and the brightness that increases potted element, its first conducting film 31 at film substrate 30a ' on form solid brilliant groove 411, and around solid brilliant groove 411 sidewall and bottom deposit reflector layer 412.Can utilize photoetching etching, electroforming process or bore process to form this solid brilliant groove 411.Crystal grain 43 adheres to the bottom of this solid brilliant groove 411, so can form a kind of similar cup-shaped reflection chamber.The side direction light that this crystal grain 43 sends can effectively reflect towards the top via reflector layer 412, to increase the luminosity of compound semiconductor element envelope 60.Another advantage of present embodiment is: when crystal grain 43 is placed in the solid brilliant groove 411, be electrically connected for utilizing plain conductor 44 to make between crystal grain 43 and film substrate 30a, the bank height of gold thread will be effectively reduced, and the slimming of overall package structure can be reached more.
Fig. 7 is the generalized section of yet another embodiment of the invention compound semiconductor element encapsulating structure.Compared to the foregoing description, present embodiment can further reduce the thickness of encapsulating structure again.On first conducting film, 31 ＂ of film substrate 30b, form routing groove 413, the posetionof weld of plain conductor 44 second solder joints can be provided; Equally, second conducting film 32 ' on also form routing groove 421, the posetionof weld of another plain conductor 44 second solder joints can be provided.Because the position of plain conductor 44 second solder joints descends, therefore can reduce the thickness of the encapsulating structure of compound semiconductor element envelope 70.
Previous embodiment adopts photoetching etching, electroforming process or bore process forms solid brilliant groove or routing groove, can also on film substrate 30, form the insulation material layer 36 of patterning, it utilizes photoengraving to be engraved in solid brilliant groove 411 and the routing groove 413,421 that forms on the insulating barrier 36, as shown in Figure 8.So not only can reduce the thickness of the encapsulating structure of compound semiconductor element envelope 80, the plain conductor 44 that can also avoid connecting second conducting film 32 has improper the contact and short circuit with 31 of first conducting films.
Fig. 9 A-Fig. 9 D forms the schematic diagram of solid brilliant groove or routing groove for the present invention adopts electroforming process.The insulation material layer 36 of formation patterning on film substrate 30 ', for example: photo anti-corrosion agent material.Utilize electroforming process at the surface growth metal level 37 that first conducting film 31 and second conducting film 32 expose, remove edge material layer 36 ' (for example: remove the photoresist step) again to form solid brilliant groove 411 and routing groove 413,421.
Technology contents of the present invention and technical characterstic disclose as above, yet those skilled in the art still may be based on teaching of the present invention and announcements and made all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by appending claims.

Claims (12)

1, a kind of encapsulating structure of compound semiconductor element comprises:
Film substrate comprises first conducting film, second conducting film and insulative dielectric material, and wherein this insulative dielectric material is between this first conducting film and this second conducting film;
Crystal grain is fixed in the surface of this first conducting film; And
Transparent adhesive material is covered in this first conducting film, this second conducting film and this crystal grain.
2, the encapsulating structure of compound semiconductor element according to claim 1, wherein the thickness of this film substrate is 20～50 μ m, and this insulative dielectric material is silica, silicon nitride, silicon oxynitride, tantalum oxide, aluminium oxide, titanium oxide, aluminium nitride, titanium nitride, epoxy resin, silicones or insulating polymeric material.
3, the encapsulating structure of compound semiconductor element according to claim 1, wherein this crystal grain can be LED crystal particle, laser diode or light sensing crystal grain.
4, the encapsulating structure of compound optoelectronic element according to claim 1, it also comprises at least one plain conductor and a plurality of projection that is electrically connected this crystal grain and this film substrate of being electrically connected this crystal grain and this film substrate.
5, the encapsulating structure of compound optoelectronic element according to claim 1, wherein this first conducting film also comprises solid brilliant groove, and this crystal grain is fixed in this solid brilliant groove, covers reflector layer in this solid brilliant groove.
6, the encapsulating structure of compound optoelectronic element according to claim 4, wherein this first conducting film also wraps and can supply the first routing groove of this plain conductor welding, and this second conducting film also comprises can be for the second routing groove of this plain conductor welding.
7, a kind of manufacture method of compound optoelectronic component packaging structure, it comprises step:
Film substrate is provided, and it comprises first conducting film, second conducting film and insulative dielectric material;
Crystal grain is fixed on this first conducting film, make the positive electrical of this crystal grain be connected to this first conducting film, and the negative electricity of this crystal grain is connected to this second conducting film; And
One transparent adhesive tape material is coated this crystal grain.
8, the manufacture method of compound optoelectronic component packaging structure according to claim 7, wherein this film substrate is made by the following step:
Thin plate is provided;
On this thin plate, form at least one groove to separate this first conducting film and this second conducting film; And
In this groove, insert the insulative dielectric material.
9, the manufacture method of compound optoelectronic component packaging structure according to claim 8, wherein this groove utilizes bore process, etch process or metal stamping technology to form.
10, the manufacture method of compound optoelectronic component packaging structure according to claim 8, it also is contained in the step that this first conducting film forms solid brilliant groove, and this crystal grain is fixed in this solid brilliant groove.
11, the manufacture method of compound optoelectronic component packaging structure according to claim 8, it also is contained in the step that this first conducting film and this second conducting film form a plurality of routing grooves, and wherein this routing groove is to supply at least one plain conductor welding part.
12, according to the manufacture method of claim 10 or 11 described compound optoelectronic component packaging structures, wherein brilliant groove or this routing groove form by photoetching etching, electroforming process or bore process admittedly.
CN200810086311A 2008-03-25 2008-03-25 Package structure of compound semiconductor component and manufacturing method thereof Expired - Fee Related CN101546737B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200810086311A CN101546737B (en) 2008-03-25 2008-03-25 Package structure of compound semiconductor component and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200810086311A CN101546737B (en) 2008-03-25 2008-03-25 Package structure of compound semiconductor component and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN101546737A true CN101546737A (en) 2009-09-30
CN101546737B CN101546737B (en) 2012-09-12

Family

ID=41193767

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200810086311A Expired - Fee Related CN101546737B (en) 2008-03-25 2008-03-25 Package structure of compound semiconductor component and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN101546737B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958390A (en) * 2010-08-13 2011-01-26 李刚 Light-emitting chip packaging structure
CN102044620A (en) * 2010-11-11 2011-05-04 深圳市瑞丰光电子股份有限公司 LED substrate and manufacturing method thereof and LED
CN102956761A (en) * 2011-08-25 2013-03-06 展晶科技(深圳)有限公司 Method for packaging light emitting diode
CN106057778A (en) * 2016-05-27 2016-10-26 矽力杰半导体技术(杭州)有限公司 Encapsulation structure and manufacture method thereof
CN110710071A (en) * 2017-06-02 2020-01-17 欧司朗光电半导体有限公司 Laser diode and method for producing a laser diode

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3910171B2 (en) * 2003-02-18 2007-04-25 シャープ株式会社 Semiconductor light emitting device, method for manufacturing the same, and electronic imaging device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958390A (en) * 2010-08-13 2011-01-26 李刚 Light-emitting chip packaging structure
CN102044620A (en) * 2010-11-11 2011-05-04 深圳市瑞丰光电子股份有限公司 LED substrate and manufacturing method thereof and LED
CN102956761A (en) * 2011-08-25 2013-03-06 展晶科技(深圳)有限公司 Method for packaging light emitting diode
CN106057778A (en) * 2016-05-27 2016-10-26 矽力杰半导体技术(杭州)有限公司 Encapsulation structure and manufacture method thereof
CN106057778B (en) * 2016-05-27 2018-11-30 矽力杰半导体技术(杭州)有限公司 Encapsulating structure and its manufacturing method
US10333019B2 (en) 2016-05-27 2019-06-25 Silergy Semiconductor Technology (Hangzhou) Ltd. Package structure of light emitter and light sensor with light-blocking layer and method for manufacturing the same
CN110710071A (en) * 2017-06-02 2020-01-17 欧司朗光电半导体有限公司 Laser diode and method for producing a laser diode
CN114039272A (en) * 2017-06-02 2022-02-11 欧司朗光电半导体有限公司 Laser diode and method for producing a laser diode
US11251587B2 (en) 2017-06-02 2022-02-15 Osram Oled Gmbh Laser diode and method for manufacturing a laser diode
US11749967B2 (en) 2017-06-02 2023-09-05 Osram Oled Gmbh Laser diode and method for manufacturing a laser diode

Also Published As

Publication number Publication date
CN101546737B (en) 2012-09-12

Similar Documents

Publication Publication Date Title
US8298861B2 (en) Package structure of compound semiconductor device and fabricating method thereof
US9812621B2 (en) Semiconductor device and fabrication method for same
TWI420695B (en) Compound semiconductor device package module structure and fabricating method thereof
TWI393275B (en) Light emitting diode package and fabrication method thereof
CN101630668B (en) Compound semiconductor element, packaging structure of optoelectronic element and manufacturing method of optoelectronic element
TW200905907A (en) Package structure of compound semiconductor device and fabrication method thereof
TWI398933B (en) Package structure of integrated circuit device and manufacturing method thereof
US20110266586A1 (en) Led package and manufacturing method thereof
US20120056223A1 (en) Led package structure and packaging method thereof
TW201511347A (en) LED package structure and manufacturing method thereof
CN101546737B (en) Package structure of compound semiconductor component and manufacturing method thereof
CN107912085A (en) For manufacturing method, connection carrier and the optoelectronic semiconductor component with connection carrier of connection carrier
US20110181182A1 (en) Top view light emitting device package and fabrication method thereof
US8461614B2 (en) Packaging substrate device, method for making the packaging substrate device, and packaged light emitting device
CN103618041A (en) ESD (electronic static discharge) protected LED (light-emitting diode) packaging structure as well as packaging method thereof
US8049244B2 (en) Package substrate and light emitting device using the same
CN101728370B (en) Encapsulation modular structure of compound semiconductor elements and manufacturing method thereof
CN101777549B (en) Packaging module structure of compound semiconductor elements and production method thereof
TWI393273B (en) Method for manufacturing light emitting diode assembly
CN101533818B (en) Encapsulation structure of integrated circuit element and method for manufacturing same
TWI548124B (en) Flip chip light emitting device and package structure thereof
CN214956944U (en) Light emitting package module
KR101363980B1 (en) Optical module and manufacturing method thereof
TW201025676A (en) Compound semiconductor device package module structure and fabricating method thereof
US20060157859A1 (en) Led packaging method and package structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: RONGCHUANG ENERGY TECHNOLOGY CO., LTD.

Owner name: ZHANJING TECHNOLOGY (SHENZHEN) CO., LTD.

Free format text: FORMER OWNER: ADVANCED DEVELOPMENT PHOTOELECTRIC CO., LTD.

Effective date: 20101119

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: HSINCHU COUNTY, TAIWAN PROVINCE, CHINA TO: NO. 2, E. RING ROAD 2, INDUSTRY ZONE 10, YOUSONG, LONGHUA SUBDISTRICT OFFICE, BAO'AN DISTRICT, SHENZHEN CITY, GUANGDONG PROVINCE

TA01 Transfer of patent application right

Effective date of registration: 20101119

Address after: No. two, No. 2, East Ring Road, Pinus tabulaeformis Industrial Zone, Longhua, Baoan District, Shenzhen, Guangdong,

Applicant after: Zhanjing Technology (Shenzhen) Co., Ltd.

Co-applicant after: Advanced Optoelectronic Technology Inc.

Address before: Hsinchu County, Taiwan, China

Applicant before: Advanced Development Photoelectric Co., Ltd.

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120912

Termination date: 20210325