TW201208155A - Packaging structure of light emitting chip - Google Patents

Abstract

The present invention relates to a packaging structure of light emitting chip, which comprises at least a substrate unit, at least a die bond zone configured on said substrate unit, at least an light emitting chip mounted on the die bond zone, and at least two substrate electrodes configured on the substrate unit and insulated with each other, which may implement the conductive conneciton with the outside; and, the substrate unit includes at least two sub-substrates insulated with each other and the light emitting chip is electrically connected to the substrate electrode through the substrate unit. The present invention employs the substrate unit that is composed of at least two sub-substrates insulated with each other as the mounting frame for the light emitting chip, which provides a simple structure and with excellent heat dissipation effect; and, between the sub-substrates, only the insulating layer is required or there is no need of insulating layer. The entire structure does not contain any polymer material, and has the merits of high temperature endurance as well as ultraviolet resistance.

Description

201208155 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a chip package structure, and more particularly to a package structure of a light-emitting chip. [Prior Art] [00Θ2] With the improvement of luminous efficiency of light-emitting chips, such as diode (LED) wafers, LEDs are moving from large-scale liquid crystal backlights and indoors to the field of indication and display applications characterized by conventional dot-line surfaces. Outdoor general lighting application field extension _ exhibition. [0003] A conventional package structure for an LED package is as shown in the first figure. The package structure includes an electrode holder 101, an LED chip 0, metal leads 1033 and 103b, and another electrode holder 1 4丨, and the connecting frame of the rose rack 1 〇 5. The above LED chip 102 is placed in a cup supported by the electrode holders 1〇1 and 1〇4. Among them, the electrode holders 101 and 104 are made of a silver-plated material of an elongated iron base, and the heat dissipation capability is limited. LEDs of the above package structure can usually only use an insulating glue (such as epoxy resin) as a solid crystal material. Since the thermal conductivity of the insulating adhesive is very poor, this package structure is mainly used in small current applications. The common package structure for high-power LED sealing is as shown in the second figure. The LED chip base 2 includes an LED chip 2〇2, metal leads 203a and 203b, electrode sheets 2〇43 and 2, and an insulating plastic reflective cup 2〇5. The high-power LED package structure adopts a block (10) wafer base. 201 'The heat sink is relatively large, and the next * can form a surface contact with other heat dissipating mechanisms or devices. 'Improve the dispersive energy. 6. The above-mentioned high-power LED package structure is more complicated and the cost is higher. 099127098 Form No. A0101 Page 3 of 47, ηΜ5 201208155 [0005] The above high-power L E D package structure is usually manufactured by a metal-based structure and a polymer organic material injection molding process. For example, the insulating plastic reflector cup 205 in the second figure is generally made of a thermoplastic polyester having relatively good heat resistance in a polymer material, such as polybutylene terephthalate (PBT), and a high temperature plastic such as polyparaphenylene. P-phenylenediamine (PPA). The modified polyparaphenylene terephthalate plastic has a heat distortion temperature of about 300 ° C and a continuous use temperature of about 170 ° C. Obviously, the heat-resistant temperature of the polymer material will determine the maximum temperature and maximum sustainable operating temperature of the above-mentioned stent. [0006] However, the usual eutectic soldering temperature is 285 ° C - 320 ° C. Since the above-mentioned stent using the above polymer plastic or polyester insulating material has a maximum withstand temperature of only about 300 ° C, the selection of the eutectic material is greatly limited, and the eutectic conditions become very severe, such as temperature control. It must be very precise, the eutectic time should not be too long, etc., resulting in high requirements, high cost and low yield of eutectic bonding. At present, most high-power LEDs still use conventional die-bonding methods, such as silicone, silver paste, solder paste, etc., which have improved thermal conductivity, but the thermal conductivity of the die-bonding interface is not as good as that of the alloyed interface produced by eutectic. . At high current or high power, the heat build-up in the LED holder due to the thermal resistance of the interface causes the temperature of the wafer to rise, thereby affecting the anti-aging and reliability of the LED wafer. Due to the poor ability of the polymer material to resist ultraviolet and high temperature and low temperature impact, the above-mentioned bracket, such as the insulating plastic reflector cup 205 in the second figure, will accelerate aging when used in an open field where ultraviolet light irradiation and high and low temperature impact are severe. As a result, the service life of the LED is very short and the reliability of the application product is very poor. [0007] A high-power LED bracket made of a metal core or ceramic core printed circuit board (MCPCB) can provide a larger bottom surface as a heat-conducting surface and other dispersions. 099127098 Form No. A0101 Page 4 of 47 Page 0992047611-0 201208155 Thermal mechanism connection, but the polymer tree mooncake material on the edge of the remaining electrode on the printed circuit board limits the use temperature of the above-mentioned high-power LED bracket, and usually cannot adopt the eutectic soldering (four) method. The above-mentioned resin is also inferior to ultraviolet light irradiation and high-low temperature impact, so that the above-mentioned high-power LED bracket will accelerate aging when used in an outdoor environment where external light irradiation and high and low temperature impact are severe, resulting in a short service life of the LED. The reliability of the application product is also very poor. The above polymer resin material functioning as an insulating layer is usually Ο [0008] ◎ [0009] 5 〇 2 〇〇 Um. If it is too thick, it can act as an insulator to prevent short-circuiting with the metal base, but it will affect the heat dissipation; if the λ thinness is better than the heat, it will easily cause the metal core and the component lead to be short-circuited. For high-power UD brackets made of ceramic heat-dissipating substrates, including thick and thin substrates, low-temperature co-fired multilayer ceramics, and thin-film ceramic substrates, although a large bottom surface can be provided as a heat-conducting surface to connect with other heat-dissipating mechanisms, ceramic b porcelain The heat dissipation performance of the material is also superior to other organic materials, but its non-conductivity requires the manufacture of conductive connection metal circuit layers on the surface of the substrate by screen printing or sputtering, electric/electrochemical deposition, yellow light processing and low temperature sintering. The circuit produced by the screen printing method is prone to rough lines, inaccurate alignment, sputtering, electric/electrochemical deposition, complicated yellow light process, and easy to fall off metal lines. The above-mentioned various types of LED package structures are widely connected to the brackets with fixed metal LEDs at the bottom for heat conduction, and the bracket itself usually does not have a heat dissipation function. This also greatly limits the use range of LEDs and self-protection. It is clear that the defects that are now widely used for LED packaging are inherently flawed. SUMMARY OF THE INVENTION 099127098 Form No. A0101 Page 5 of 47 〇992〇47611-〇201208155 [0010] The technical problem to be solved by the present invention is to provide a light-emitting chip package with simple structure, good isothermal temperature and good heat dissipation effect. structure. The technical solution of the present invention is: a light-emitting chip package structure comprising at least one substrate unit, at least one die-bonding region disposed on the substrate unit, and mounting on the die-bonding layer At least one illuminating wafer on the region, and at least two substrate electrodes that are electrically isolated from each other are disposed on the substrate unit; the substrate unit includes at least two sub-substrates insulated from each other; The substrate unit is electrically connected to the substrate electrode. [0012] In the light emitting chip package structure of the present invention, the sub-substrate is a conductive sub-substrate 'between adjacent conductive sub-substrates, and an insulating layer or Insulating tape 'either, leaving a gap between adjacent conductive sub-substrate, or 'filling the gap with an insulating potting material; or, [0013] the sub-substrate is a non-conductive sub-substrate, The non-conductive sub-substrate is provided with a conductive metal film electrically connecting the light-emitting chip to the corresponding electrode of the substrate; or [0014] the sub-substrate comprises a conductive sub-substrate and a non-conductive sub-substrate, in the non- The electron-conducting substrate is provided with a conductive metal film electrically connecting the light-emitting chip to the electrode corresponding to the substrate. [0015] In the illuminating chip package structure of the present invention, the substrate unit is a single-layer substrate unit including at least two sub-substrates insulated from each other and spliced to each other in a horizontal direction; or, [0016] the substrate unit The multi-substrate unit 'includes at least two sub-substrates insulated from each other and superimposed on each other in the vertical direction; or, 099127098 Form No. A0101 Page 6 / Total 47 Page 0992047611-0 201208155 [0017] The substrate unit is a multilayer composite a substrate unit comprising at least one of the sub-substrate and at least one of the single-layer substrate units, the sub-substrate and the single-layer substrate unit are insulated from each other and superposed on each other in a vertical direction; the single-layer substrate unit includes at least two The sub-substrates are insulated from each other and spliced to each other in the horizontal direction. [0018] In the light emitting chip package structure of the present invention, the die bonding regions are all disposed on the same sub-substrate constituting the single-layer substrate unit, or are respectively disposed on the single-layer substrate unit. Different on the sub-substrate. [0019] In the light emitting chip package structure of the present invention, the die bonding regions are all disposed on the same sub-substrate constituting the multi-layer substrate unit, or are respectively disposed in different ones constituting the multi-layer substrate unit On the sub-substrate; or, [0020] the solid crystal regions are all disposed on the same sub-substrate constituting the multi-layer composite substrate unit, or respectively disposed on different sub-substrates constituting the multi-layer composite substrate unit on. [0021] In the luminescent wafer drum structure of the present invention, the die bonding region is disposed on the non-top layer sub-substrate, and the sub-substrate located on the upper layer of the sub-substrate in which the die-bonding region is disposed is provided with The corresponding opening of the die bonding region, the inner sidewall of the opening constitutes a potting light exiting space and a reflective sidewall of the light emitting wafer placed in the die bonding region. [0022] In the light emitting chip package structure of the present invention, the die bonding region is disposed on an upper surface of the sub-substrate; or, in a pit disposed on a surface of the sub-substrate, an inner sidewall of the pit constitutes a placement The light-emitting wafer encapsulates the light-emitting space and the reflective sidewall in the die-forming region. 099127098 Form No. A0101, page 7 / 47, 〇 201208155 [0023] In the light emitting chip package structure of the present invention, the solid crystal region is provided with a raised coaming around the inside; the inner side wall of the cofferdam is placed at The light-emitting wafer in the solid crystal region encapsulates the light-emitting space and the reflective sidewall. In the light emitting chip package structure of the present invention, the surface of the die bonding region and the inner sidewall of the potting light emitting space may be coated with a single layer or a plurality of metal reflective films and/or non-metal reflective films. [125] In the light emitting chip package structure of the present invention, the inner sidewall of the potting light exiting space includes a smooth surface perpendicular to the surface of the die bonding region, and/or is substantially dry with the surface of the die bonding region A smooth bevel of a 90 degree central angle, and/or a smooth orphan that extends from the surface of the solid crystal region toward the surface of the substrate unit. [0026] In the light emitting chip package structure of the present invention, the inner sidewall of the potting light exiting space includes at least one step, and the surface level surface of the step is disposed on the surface of the sub-substrate having the solid crystal region or has On the sub-substrate above the sub-substrate of the die bonding region. The invention discloses a light-emitting chip package junction obliquely. The light-emitting chip is placed in the solid crystal region (four), and the plurality of light-emitting wafers are connected in series. Or connected in parallel or in series and parallel, and then electrically connected to the corresponding substrate electrodes. [0028] In the light emitting chip package structure of the present invention, a wire bonding region respectively electrically connected to the corresponding substrate electrode is disposed in the vicinity of the die bonding region, and the light emitting wafers are electrically connected to the corresponding bonding wires respectively The region, or a plurality of the light-emitting wafers φ are connected in parallel or in parallel or in parallel, and then electrically connected to the corresponding bonding wire regions. [0029] 099127098 In the light-emitting chip package structure of the present invention, the form number hall 01 S 8 pages / total 47 pages of the substrate unit bare 0992047611-0 201208155 [0031] [0032]

G In the hair supply structure of the present invention, the insulating layer is a layer or a multilayer composite __; the edge layer of the material layer is provided with one or more layers of transition metal film and/or alloy film. The implementation of the present (4) has the following beneficial effects: the substrate unit composed of at least two sub-substrates insulated from each other is used as a mounting bracket for the illuminating wafer, and has a simple structure and good heat dissipation; and only needs to be used between the sub-substrates. _ or fundamental (four) insulation layer, the entire structure does not contain any polymer material, has the advantages of high temperature resistance and UV resistance. [Embodiment] The embodiments of the present invention and the various Pan-chip package structures for LED packages of the present invention can be fully understood by the following description of the preferred embodiments, and the following preferred embodiments can also be considered as examples of the dance of the claims of the present invention. It will be apparent that the scope of the invention as defined by the claims of the invention is more broadly than the preferred embodiments of the following. More modified and modified embodiments can be produced with the aid of ordinary skill without departing from the spirit and scope of the invention. Therefore, the embodiments described below are intended to be illustrative only and not to limit the scope of the invention as defined by the appended claims. [0033] As shown in the third figures a, 3b, is a first embodiment of the light-emitting chip package structure of the present invention, comprising an insulating underlayer sub-substrate 305, and a two-layer conductive sub-substrate disposed on the insulating underlayer sub-substrate 3〇1 and 3〇2, solid crystal region, metal leads 303 and 304, substrate electrodes 308a, 308b, and sub-substrate 099127098 Form No. A0101 Page 9/47 pages 0992047611-0 201208155 [0034] [0035] [0038] [0038] An insulating tape 3 0 7 is provided between 3 〇 1 and 3 0 2 . In this embodiment, the bottom sub-substrate 305 may be made of an insulating material, such as a ceramic material or other inorganic non-metal material, and may be a single layer structure, a multi-layer structure, or an insulating film, for example, An inorganic insulating film, for example, dioxide; 5 or I fossil, is applied to the back surface of the substrate by steaming or sputtering. The two-layer conductive sub-substrate 301 and 302 are disposed on the underlying sub-substrate 3〇5, and may be made of a conductive material, such as a metal, an alloy, etc., and may be a single-layer structure or a multi-layer structure ◊..; An insulating tape 307 is disposed between the conductive sub-substrates 301 and 302 to insulate the conductive sub-substrate 301 and 302. The insulating tape 307 may be an oxide-based or nitride-based substrate. Or other inorganic insulating material-based single-layer film material or a multilayer composite film material composed of the above materials, and form a tight and firm contact with the conductive sub-substrates 301 and 302. The shape of the insulating tape 307 may be any shape. The substrate unit composed of the conductive sub-substrates 301 and 302 and the bottom mother substrate 305 is an integrated layer substrate unit. The conductive sub-substrate 301, 302 insulated and spliced in the horizontal direction is a single-layer substrate unit, and the underlying sub-substrate 305 and the single-layer substrate unit are insulated from each other and superposed on each other in the vertical direction. The die bonding region may be disposed on the conductive sub-substrate 301 and/or the conductive sub-substrate 302 as a mounting position of the light-emitting wafer 306. Of course, the size, position, and the like of the solid crystal region can be adjusted in accordance with the number, size, and the like of the light-emitting chips 3〇6. [0039] 099127098 The substrate electrodes 308a, 308b are respectively disposed on the conductive sub-substrate 3〇1 and 3〇2, Form No. A0101, Page 10/47, 0992047611-0 201208155 [0040] Ο [0041] [0042] Ο [0043] On both sides, an electrically conductive connection can be made to the outside to provide a working power source for the light-emitting chip 306. As shown in the figure, the present embodiment only schematically shows a package of an illuminating wafer 306. The illuminating wafer 306 is disposed on the conductive sub-substrate 302 by a die bonding method. The positive and negative electrodes of the luminescent wafer 306 are respectively passed through a metal. The leads 303 and 304 are electrically connected to the conductive sub-substrates 301 and 302, and since the conductive sub-substrates 301 and 302 are electrically conductive, the positive and negative electrodes of the luminescent wafer 306 are electrically connected to the substrate electrodes 308a, 308b, respectively. An external power source is introduced from the substrate electrodes 308a, 308b. Of course, as shown in the third figure c, there may be a plurality of illuminating wafers, which may be respectively disposed on the conductive substrates 301 and 302 by solid crystal, and the plurality of illuminating wafers may be connected in parallel and/or in series to the substrate electrodes 308a, respectively. 308b conductive connection. Further, as shown in the third figure d, a potting coaming 309 may be added to the periphery of the wafer to form a potting light-emitting space. The shape of the potting_堰309 may be any shape, such as a square ring or a circle. Various shapes such as a ring shape and an elliptical ring shape serve to enclose the potting material. Of course, it is also possible to directly use the surface tension of the potting material without forming a potting cofferdam, as shown in the third figure e, which is a deformation of the third figure a, by adding the insulating tape 307a, The electronic substrate is divided into four conductive sub-substrate units insulated from each other, and corresponding illuminating wafers can be disposed on the respective independent conductive sub-substrate units, thereby facilitating layout of the illuminating wafer, color matching, and the like. The electrodes are divided into four independent electrodes 308a, 099127098. Form No. A0101 Page 11/47 pages 0992047611-0 201208155 308b, 308c, 308d are respectively connected to the respective conductive sub-substrate units and insulated from each other. It can be understood that more insulation can be added to separate more conductive sub-substrate units, so as to adapt to different occasions. [0044] As shown in the fourth figure a, 4b' is a second embodiment of the present invention, a light-emitting chip package structure having a two-layer substrate structure for an LED package, comprising a bottom substrate 401, an insulating layer 402, and a second layer The substrate 403, the die bonding region disposed on the underlying substrate 401, the LED wafer 406 disposed on the die bonding region by the die bonding, the top bonding wire region 4〇4a and the bottom bonding wire region 404b connected to the wafer, and the metal lead 4 are reduced. & and 4051), the bottom electrode 407a and the top electrode 4〇7b connected to the external power source or/and the signal interface, the fixed through holes 408a, 408b, 408c and 408d, the potting light exiting space 409, and the lower layer substrate lower side wall 410a And upper side wall 410b. The underlying substrate (the Π and the two-layer substrate 403 as the sub-substrate constituting the conductive substrate unit, the potting light-emitting space 4〇9 serves as both the light-emitting space and the potting space of the LED wafer 406. [0045] FIG. The embodiment of 4b is that the two-layer substrate 403 having a barrier-shaped opening in the center is placed on the base substrate 4, and an insulating layer 402 is disposed between the two substrates. The bottom substrate 401 and the two-layer substrate 4〇3 generally have good heat conduction. And conductive metal materials such as steel, aluminum, tungsten molybdenum and other metal materials or alloys thereof can of course be made of ceramic or other inorganic non-metal based materials and form a conductive film on the surface, generally stacked in a sheet form. Usually, the thickness of a single substrate is between several hundred micrometers and several millimeters. A single substrate may also adopt a multilayer structure composed of the above materials. The bottom substrate and the two substrates may be the same or different materials, the same or different thicknesses, and the same Or different sizes, same or different shapes 099127098 Form number A0101

Page 12 / 47 I 0992047611-0 201208155, etc., can be adjusted according to design requirements. [0046] The underlying substrate 401 and the two-layer substrate 403 are stacked in a vertical direction, which are both conductive substrates, and the insulating layer 402 is disposed between the underlying substrate 401 and the two-layer substrate 403 to insulate the two. The insulating layer 402 is typically a single or composite multi-layer film material based on an oxide or nitride based or other inorganic insulating material such as hafnium oxide and tantalum nitride. Usually its thickness is between a few microns and a few hundred microns. In order to enhance the adhesion between the insulating layer 402 and the underlying substrate 401 and the two-layer substrate 403, a film for improving the adhesion is usually disposed between the insulating layer 402 and the underlying substrate 401 and the two-layer substrate 403, and is usually made of, for example, titanium, nickel. And a metal material such as tungsten or an alloy layer composed of the above metal or a multilayer structure composed of the above metal and alloy, usually having a thickness of between several tens of nanometers and several hundred nanometers. [0047] The underlying substrate 401 of the fourth embodiment a, 4b is not only used as a basis for the light-emitting wafer package structure, but also provides a set of electrical connection points with the wafer and the outside, and the substrate 401 itself has the function of a conductive electrode. The underlying substrate 401 includes an underlying conductive substrate body, and a die attach region, a bottom bond wire region 404b, and a bottom electrode 407a for mounting the light emitting wafer (LEE wafer 406) are disposed on the underlying conductive substrate body. [0048] The central via sidewall of the two-layer substrate 403 not only provides a light exit path for the wafer 406 placed on the underlying substrate 4〇1, but also provides a set of electrical connection points with the wafer and the outside, a two-layer substrate. 403 itself has the function of a conductive electrode. The two-layer substrate 403 serves as a top conductive substrate, and includes a top conductive substrate body. The top conductive substrate is provided with an electrically conductive top wire bond region 404b and a top electrode 407b. 099127098 Form No. A0101 Page 13 of 47 0992047611-0 201208155 [〇_] The positive and negative electrodes of the LED chip 406 are electrically connected to the top wire bond area 4 0 4 a and the bottom layer through metal leads 4〇5M〇4〇5b, respectively. The wire bonding area 4 〇 4 b is connected to the outside through the top electrode 407b and the bottom electrode 407a, that is, a power source and a control signal. [0050] Further, the stepped opening in the center of the two-layer substrate 403 forms a potting light-emitting space 409 corresponding to the solid crystal region. The upper and lower two regions enclosed by the lower side wall 41a and the upper side wall 410b may be filled with the same or different light transmissive packaging materials. The white-light LED as described generally can be prepared by injecting the phosphor-containing silicone and the upper potting region of the upper side wall 41 Ob into the lower potting zone as follows. By improving the appearance of the underlying substrate 4 〇 ^ and the two-layer substrate 403, other light-transmissive encapsulating materials and/or various types of pre-formed lenses or other optical devices may be potted over the potting regions 4 〇 9 . The bottom substrate 401 and the layer substrate 403 may have the same or different outer shapes, and may have the same or different sizes. Usually square, rectangular or round. [0051] The upper and lower two-zone potting regions enclosed by the lower sidewall 410a and the upper sidewall 41〇1} in the fourth embodiment a, 4b may be symmetrically asymmetrical and asymmetrical, different or/and the same shape, thereby Achieve different light shapes and light intensity distributions, usually square, rectangular, elliptical or circular. The lower side wall 41〇9 and the surface of the base substrate 401 and the upper side wall 41〇b and the step surface of the two-layer substrate 4〇3 may be perpendicular or oblique, and the lower side wall 41〇a and the upper side wall 41仳 themselves It can be a smooth plane or a smooth arc surface' to control the distribution of light within the potting zone 4〇9, which in turn changes the light efficiency, light shape and light intensity distribution. [〇〇52] Generally, the inner wall surfaces of the above-mentioned side walls 410a and 410b are coated with a highly reflective material such as a red or non-metallic reflective material to form a single or multiple layer metal reflective film and/or non-zero 99127098 Form No. A0101 Page 14 of 47 Page 0992047611-0 201208155 [0054] 99 [0055] 099127098 Metal reflective film. The exposed portions of the underlying substrate 401 and the two-layer substrate 403 which are not laid with electrodes or wire regions (i.e., the surface of the die attach region) are also typically coated with a highly reflective material, such as Ag, to reduce absorption. In order to avoid short circuit, the exposed portions of the electrode unit or the wire bonding area around the substrate unit may also be coated with an insulating film such as yttrium oxide and tantalum nitride. As shown in FIG. 5 and FIG. 5b, another embodiment of the present invention, an illuminating chip package structure having a convex double-layer substrate structure for an LED package, comprising an underlying substrate 501, an insulating layer 5〇2, and 2 The layer substrate 503, the potting zone cofferdam 509, the two-layer substrate coaming 5〇3a flush with the potting zone cofferdam 509, the solid crystal region, and the LEI) wafer 5通过6 disposed on the solid crystal region by die bonding a substrate bonding wire region 5〇4a and a substrate bonding wire region 504b connected to the LED chip 506, metal leads 505a and 505b, substrate electrodes 507a and 507b connected to an external power source or/and a signal interface, and fixed via holes 508a and 508b, 508c and 5 0 8 d LED The LED wafer in the fifth embodiment a, 5b embodiment; five leaves are multiple, and one electrode (positive electrode or negative electrode) of all the LED chips 506 passes through the metal lead 505b and the metal base layer respectively. The first wire bonding region 504b of the substrate 501 is connected, and the other electrode of the LED chip 506 is connected to the bonding wire region 504a of the metal-layer substrate 503 through the metal wires 5〇5a, respectively, to form the above-mentioned upper substrate 501. The parallel connection method of the LED chip 506. The upper surface of the solid crystal region, the inclined side wall surface 51 of the two-layer substrate, the surface 510a of the two-layer substrate, the upper side wall 51 ia and the lower side wall 51 ib of the potting area co-enclose the light-emitting space. The upper and lower two regions surrounded by the upper side wall 51 la and the lower side wall 51 lb may be filled with the same or different light transmissive encapsulating material. The lower potting area surrounded by the side wall 51 lb is filled with the phosphor-containing silicone and the upper side wall 51 la. Form No. A0101 Page 15 / Total 47 Page 0992047611-0 201208155 [0056] [0058] 099127098 Enclosed The above-mentioned white light LED can be prepared by injecting silicone or epoxy resin into the upper potting area. In addition, other transmissive encapsulating materials and/or various types of pre-formed lenses or other optical devices can be potted over the potting area by improving the appearance of the underlying substrate 5 and the potting zone coam 509. The potting region 509 can be a conductive or non-conductive material that can be the same or different in shape and size as the bottom substrate 501, such as square, rectangular, circular, or other various shapes. The upper and lower areas of the upper side wall 511 & and the lower side wall 5丨丨b in the fifth embodiment a, 5b may be symmetrical or/and asymmetrical, different or/and the same shape, thereby realizing Different light shapes and light intensity distributions, for example, square, rectangular, elliptical, circular or other various shapes. The upper side wall 511 a, the lower side wall 511 b and the surface of the bottom substrate 5 〇 1 may be perpendicular or beveled or curved, and the upper side wall 511 a and the lower side wall 511 b may be smooth or smooth arc. , the use of the control of the light distribution in the potting zone 5〇9, and then change the light efficiency, light release and light intensity distribution. Usually, the upper side wall 511a and the lower side wall 511b are coated with a highly reflective material such as a snake. The exposed portions of the underlying substrate 501 and the two-layer substrate 503 which are not laid with electrodes or wire bonding regions are also usually coated with a reflective material such as Ag to reduce absorption and improve light extraction efficiency. As shown in FIG. 6 and FIG. 6b, another embodiment of the light-emitting chip package structure of the grooved double-layer substrate for LEI) package of the present invention comprises an underlying substrate 601, an insulating layer 602, and a two-layer substrate 6. 〇3& and 6〇31), insulating partition strips 6〇3c and 603d between the two substrates, a die bonding region disposed on the underlying substrate 1, and an LED wafer form number A0101 disposed on the solid crystal region by die bonding Page 16 of 47 0992047611-0 201208155 [0059] Ο [0060]

G 606, bond wire regions 604a and 604b connected to the LED chip 606, metal leads 605a' 605b' 605c and 605b, and a wiring 605 between the LED chip 606, a two-layer substrate connected to an external power source or/and a signal interface The electrodes 607a and 607b, the fixed through holes 6〇8a, 608b, 608c and 608d, and the upper surface of the solid crystal region of the lower substrate side wall 61〇a, the upper side wall 610b and the bottom substrate 6〇1 The light space 609 is sealed. The die attach region in the sixth embodiment a, 6b embodiment has two sets of LED chips 606, each set of 6 wafers. The first electrode of each of the first wafers of the wafer is connected to the substrate bonding wire region 604b, and the second electrode of the sixth wafer is connected to the substrate bonding wire region 6〇4a, the first electrode of the first wafer and the second wafer. One electrode is connected 'and so on, and six wafers are connected in series. The entire LED holder inner chip realizes the 6-string parallel connection method. It can be understood that the number of LED chips, the number of groups, and the like can be adjusted as needed. The embodiment of the sixth figure a, 6b is that two two-layer substrates 6〇3a and 6〇3b having the same shape, size and thickness are butt-joined on the base substrate 601, and the two-layer substrates 60 3 a and 6 03b Insulation partition strips 60 3c and 603d are disposed therebetween to form a single-layer substrate unit; and the two-layer substrates 603a and 603b are superimposed in the vertical direction with the underlying substrate 601 and between the two-layer substrates 603a and 603b and the underlying substrate 6〇 An insulating layer 602 is provided to form a multilayer substrate unit. The base substrate 601 and the two-layer substrates 603a and 603b are usually made of a metal material having good heat conductivity and good electrical conductivity, such as copper, aluminum, tungsten, molybdenum and other metal materials, which are generally laminated in a sheet form. Typically a single substrate has a thickness between a few hundred microns and a few millimeters. The single substrate may be a single layer structure or a multilayer structure composed of a top material. [0061] 099127098 Insulation layer 6G2$ is often made of an oxide or vapor film material such as oxidized oxide eve Form No. A0101 Page 17 of 47 0992047611-0 201208155 and tantalum nitride. Usually its thickness is between a few microns and a few hundred microns. In order to enhance the adhesion between the insulating layer 602 and the underlying substrate 601 and the two-layer substrates 6〇33 and 6〇31), a common setting between the insulating layer 6〇2 and the underlying substrate 6〇1 and the two-layer substrates 603a and 603b is generally provided. a film having improved adhesion, usually a metal material such as titanium, nickel, and tungsten or an alloy layer composed of the above metal or a multilayer structure composed of the above metal and alloy, usually having a thickness of several tens of nanometers and several hundred nanometers between. [0063] The insulating partition strips 603c and 603d are generally provided with a gap between the two-layer substrates 6033 and 603b, which is automatically filled with a normally insulating translucent sealing material or a two-layer substrate during the subsequent potting process. 6 〇3 a and 6 〇3 b opposite end faces coated with an inorganic non-metallic insulating material or embedded in the voids of inorganic non-metallic insulating material ^, the bottom substrate 6 〇 1 in the embodiment of the sixth figure a, 6b is mainly used as a package structure The base and heat conduction channels, the inner sidewalls of the two-layer substrates 6〇3& and 6〇31) not only dance the light-emitting channel on the underlying substrate 601, but also reflect the side surface, also provided with the wafer. The electrical connection points to the outside, the two-layer substrates 603a and 603b themselves have the function of a conductive electrode. The stepped inner walls of the two-layer substrates 603a and 603b form a potting light-emitting space 6〇9. The upper and lower two regions enclosed by the upper side wall 610b and the lower side wall 610a may be filled with the same or different light transmissive encapsulating materials. A conventional white LED can be prepared by injecting silicone or epoxy resin into the lower potting area of the side wall 61 〇 a, which is filled with the phosphor powder and the upper side wall 61〇1). By modifying the appearance of the two-layer substrates 603a and 603b, other light-transmissive encapsulating materials and/or various types of pre-formed lenses or other optical elements can be potted over the potting regions 6〇9. The base substrate 601 and the two-layer substrate 6〇33 and 6〇099127098 Form No. A010] The 8th page/total 47 pages 〇992〇47611-〇201208155 The shapes may be the same or different, the sizes may be the same or different, for example, Square, rectangular, round, or any other shape. [0064] The upper and lower two-zone potting regions enclosed by the upper side wall 610b and the lower side wall 610a in the sixth embodiment a, 6b embodiment may be symmetric or asymmetric, have different or the same shape, thereby achieving different light shapes. And light intensity distribution, for example, square, rectangular, elliptical, circular or other shapes. The lower sidewall 610a and the surface of the base substrate 601 and the upper sidewall 61 Ob may be perpendicular or oblique between the stepped surfaces of the two substrates 603a and 603b, and the upper sidewall 610b and the lower sidewall 610a may themselves be smooth planes or Smooth curved surface, used to control the light distribution in the potting area & 09ϋ, and then change the light efficiency, light shape and light intensity. Typically, the upper sidewall 610b and the lower sidewall 610a are coated with a south reflective material such as Ag. The underlying substrate 601 and the two-layer substrate 6 03a and 630b are also uncoated with exposed portions of the electrode or wire bond regions which are also typically coated with a highly reflective material, such as Ag, to reduce absorption. In order to avoid short-circuiting, the exposed portion of the electrode or the wire bonding area around the above-mentioned bracket may also be coated with an insulating film such as oxidized powder and gasified hair. [0065] As shown in FIG. 7 and FIG. 7b, FIG. 2 is another embodiment of the light-emitting chip package structure with a heat dissipation structure for a led package of the present invention, including an underlying substrate 701, insulating layers 702a and 702b, and a second layer. a substrate 703, a die bonding region disposed on the underlying substrate 701, a led wafer 706 disposed on the die bonding region by die bonding, a substrate bonding region 7〇4a and 7〇4b connected to the LED chip 706, and a metal lead 705a and 705b, substrate electrodes 707a' 7〇7b, 707c, 707d, 707e, and 707f connected to the external power source or/and signal interface, fixed through holes 708a, 7〇8b, 708c and 708d, top heat dissipating column array 7U, heat dissipating column Array substrate 711a, heat sink array inside potting 099127098 Form No. A0101 Page 19 / Total 47 page 0992047611-0 201208155 Area 堰 711b, heat dissipation groove 712 provided around the bottom substrate 701, heat dissipation concave provided on the bottom surface of the bottom substrate 701 A slot array 713, and a heat sink 714 beneath the LED wafer. The inner side wall 710a of the second layer substrate 703, the inner side wall 711c of the bank 71b, the upper surface of the die bonding area, and the like collectively enclose the potting light space 709. [0066] The embodiment of the seventh embodiment a, 7b is such that a two-layer substrate 703 having a through hole in the center is placed on the underlying substrate 701 with an insulating layer 702a disposed therebetween. The bottom substrate 701 and the second substrate 703 are generally made of a metal material having good heat conductivity and good electrical conductivity, such as copper, inscriptions, cranes, flips, and other metal materials or alloys thereof, and are generally stacked in a sheet shape; of course, insulation may also be used. The material is made, and a conductive film can be formed on the surface of the insulating substrate. Typically a single substrate has a thickness between a few hundred microns and a few millimeters. A single substrate may also be a multilayer structure composed of the above materials. [0067] The insulating layer 702a is usually made of an oxide or nitride thin film material such as hafnium oxide and tantalum nitride. Usually its thickness is between a few microns and a few hundred microns. In order to enhance the adhesion between the insulating layer 702a and the underlying substrate 701 and the two-layer substrate 703, a metal film for improving the adhesion is usually disposed between the insulating layer 702a and the underlying substrate 701 and the two-layer substrate 703, for example, using titanium, A metal material such as nickel or a town or an alloy layer composed of the above metal or a multilayer structure composed of the above metal and alloy usually has a thickness of between several tens of nanometers and several hundred nanometers. [0068] The heat dissipation substrate 71 la in the embodiment of the seventh embodiment a, 7b is placed on the two-layer substrate 703, and an insulating layer 702b is disposed between the two substrates. A heat dissipating column array 711 is disposed on the heat dissipating substrate 711a (only the heat dissipating column array in the upper right quarter region is illustrated in the seventh figure b, and the rest is omitted. 099127098 Form No. A0101 Page 20 of 47 0992047611 -0 201208155 Heatsink array), the inside is the potting zone cofferdam 711b, and the inside of the cofferdam has the cofferdam inner side wall 711c. The heat dissipation substrate 711a, the heat dissipation column array 711, and the potting zone cofferdam 71 lb are made of a metal material or a non-metal material having good heat conductivity to form a heat dissipation structure for heat dissipation. Usually the diameter of a single heat sink, the height and the distance between the heat sinks are between a few hundred microns and a few millimeters. If the heat dissipation substrate is an insulating material, the insulating layer 702b can be omitted. [0069] The insulating layer 702b is disposed between the heat dissipation substrate 711a and the two-layer substrate 703, and is usually made of an oxide or nitride film material, such as yttrium oxide and tantalum nitride, and the thickness thereof is usually between several micrometers and several hundred micrometers. between. In order to enhance the adhesion between the insulating layer 702b and the heat dissipation substrate 711a and the two-layer substrate 703, a metal film for improving the adhesion is usually disposed between the insulating layer 702b and the heat dissipation substrate 711a and the two-layer substrate 703, and is usually used. A metal material such as titanium, nickel, and niobium or an alloy layer composed of the above metal or a multilayer structure composed of the above metals and alloys usually has a thickness of between several tens of nanometers and several hundred nanometers. [0070] It can be understood that the insulating layer 702b may not be disposed in the embodiment of the seventh embodiment a, 7b, the top heat dissipation column array 711, the heat dissipation column array substrate 711a, the heat dissipation column array inner potting area encircling area 711b, and the heat dissipation. The inner wall 711c of the inner side of the column array is directly disposed on the two-layer substrate 703, and the heat-dissipating column array 711, the heat-dissipating column array substrate 711a, and the inner side of the heat-dissipating column array may be directly prepared on the thickened two-layer substrate 703. The enclosing area 711b of the potting area and the inner side wall 711c of the enclosing area of the inner side of the heat dissipating column array. The heat dissipation column array substrate 71 la may be pasted on the two-layer substrate 703 by pasting. [0071] The bottom substrate 701 in the seventh embodiment a, 7b embodiment not only serves as the basis of the package structure of the light crystal 099127098 Form No. A0101 page 21/47 page 0992047611-0 201208155, but also provides the same with the wafer and the outside world. The substrate electrodes 707a and 707b are combined, and the underlying substrate 701 itself has the function of a conductive electrode. The central via sidewall of a substrate 703 provides not only the light exit path and the reflective side surface of the wafer 706 placed on the underlying substrate 701, but also the set substrate electrodes 7〇7e, 707c and the LED chip and the outside. At 707d, the two-layer substrate 703 itself functions as a conductive electrode. The two electrodes of the LED chip are electrically connected to the substrate electrodes of the underlying substrate 7〇1 and the substrate 703 via metal leads, respectively. [0073] The inner hole of the second layer substrate 703 forms a lower portion of the potting light exiting space 7〇9, and the inner side wall 7Uc of the inner side of the heat dissipating column array forms the upper portion of the potting light exiting space 709. Potting and venting space 7〇9 up and down two parts of the same perfusion of the same or different translucent packaging materials. The commonly described white LEDs can be prepared by infusing the fluorite-containing enamel and the potting zone with enamel or epoxy in the potting zone as follows. By improving the appearance of the bottom substrate 7〇1 two-layer substrate 703 and the inner side of the heat-dissipating column array potting area 711 b, other transparent sealing materials or various types of pre-filling can be potted above the filling area 709. Formed lenses or other exam-pieces. The bottom substrate 7〇1, the two-layer substrate 703, and the heat-dissipating column array substrate 711a may have the same or different shapes, sizes 'and thicknesses, for example, generally smaller than A, square, rectangular or circular, and the thickness of the single layer is several Between 100 microns and a few millimeters. The lower portion of the upper portion of the potting zone formed by the inner side wall of the inner wall of the heat-dissipating column array in the seventh embodiment of the heat-dissipating column array and the central through-hole side wall 71〇a of the two-layer substrate 7〇3 may be symmetrical or Asymmetric 'different or identical shapes' to achieve different filament and light intensity distributions, for example using square 'rectangular, elliptical, circular or other shapes. Central through-hole sidewall 099127098 Form No. A0101 Page 22 / Total 47 Page 0992047611-0 201208155 Ο [0074] 710a and the surface of the bottom substrate 701, the inner side of the heat-dissipating column array, the inner side wall 711c of the potting area and the step of the two-layer substrate 703 The surfaces may be perpendicular or beveled, and the central through-hole side wall 71 0 a and the inner side wall 711 c of the inner side of the heat-dissipating column array may be a smooth plane or a smooth curved surface for controlling the potting area 709. The distribution of light, which in turn changes the light efficiency, light shape and light intensity distribution. Typically, the central through-wall side wall 71 0 a and the inner side of the heat-dissipating column array are encircled: the inner side wall 711 c is coated with a highly reflective material such as Ag. The exposed portions of the underlying substrate 701 and the two-layer substrate 703 that are not laid with electrodes or wire bonds are also typically coated with a highly reflective material, such as Ag, to reduce absorption. In order to avoid short circuit, the exposed portion of the above-mentioned bracket or the bare portion of the wire bonding area may also be coated with an insulating film such as yttrium oxide and tantalum nitride. Further, a lower portion of the bottom substrate 701 is provided with a heat dissipation groove array 713, and a good heat conduction is disposed under the LED wafer 706 as a heat sink 714. The width, depth, and groove pitch of the heat sink groove array 713 are between several hundred micrometers and a few millimeters. The array of heat dissipating grooves arranged in a crosswise manner forms an array of heat dissipating columns to further increase the heat dissipating area. In order to enhance the contact area with other components or the heat dissipating mechanism and avoid the formation of voids in the contact area, the above-mentioned heat dissipating groove array 713 may be disposed on the lower surface of the underlying substrate not in contact with other components or heat dissipating mechanisms; and the heat dissipating groove array 713 may Arranged into various shapes. A heat sink 714 having good thermal conductivity can be added to the underlying substrate in contact with other components or heat sinks. [0075] As shown in FIG. 8 and FIG. 8b, a light-emitting chip package structure with a heat dissipation structure multi-wafer integration for an LED package of the present invention includes an underlying substrate 801, a die bonding region 801a disposed at the center of the substrate, and insulation. Layers 802a, 802b, 802c, 802d, 802e and 802f, four-piece two-layer substrate 803a 099127098 Form No. A0101 Page 23/47 pages 0992047611-0 201208155 '80 3b, 803c and 803d, through the die-bonding in the die-bonding zone The upper LED chips 806a, 806b, 806c and 806d, the metal leads 805, the substrate electrodes 8〇7a, 807b, 807c' 807d ' 807e ' 807f ' 807g ' 807e ' 807f ' 807g and 807h, the fixed through holes 808a connected to the external power source or/and the signal interface , 80 8b, 808c and 808d, the top of the potting area 812. Exposed solder wire areas 8iia, 811b, 811c and 811d are respectively disposed on the four two-layer substrates. The upper surface of the solid crystal region, the corresponding oblique sidewalls 810a' 81 Ob, 810c, and 810d of the four-layer two-layer substrate and the inner wall 813 of the top cofferdam of the potting region are enclosed by a potting light-emitting space 809 for setting in the solid crystal The led chip of the area is lighted out. A heat dissipating column array 8 i 4 is arranged on the top of the Guanzheng 8 i 2 in the potting area to improve the heat dissipation efficiency. [0077] The embodiment of the eighth embodiment a, 8b is to place four square two-layer substrates 8〇3a, 803b′ 8〇3c, and 803d on the circular base substrate 801, between the substrates. An insulating layer 8〇2a is provided. The base substrate 801 and the two-layer substrates 803a, 803b, 803c, and 803d are generally made of a metal material having good heat conductivity and good electrical conductivity, such as copper, aluminum, tungsten, molybdenum, and various materials thereof or alloys thereof, which are generally stacked in a sheet form. Together, typically a single substrate has a thickness between a few hundred microns and a few millimeters. The single-substrate may also adopt a multilayer structure composed of the above materials. The insulating layer 802a is disposed between the underlying substrate 801 and the two-layer substrates 803a, 803b, 803c, and 803d, and is usually made of an oxide or nitride thin film material such as hafnium oxide and tantalum nitride. Usually its thickness is between a few microns and a few hundred microns. To enhance the adhesion between the insulating layer 8〇2a and the underlying substrate 8〇1 and the two-layer substrate 8〇3a, 803b, 803 (; and 8〇3 (1, between the insulating layer 8〇2a and the underlying substrate 8〇1) And a two-layer substrate 8〇3&, 8〇3b, view c and 099127098 Form No. A0101 Page 24/47 pages 0992047611-0 201208155 803d is usually provided with a metal film to improve the adhesion, usually using titanium, recorded a metal material such as a crane or an alloy layer composed of the above metal or a multilayer structure composed of the above metal and alloy, usually having a thickness of between several tens of nanometers and several hundred nanometers. [0078] Four pieces of two [0079] An insulating tape 802c, 802d, 802e and 802f is disposed between the layer substrates 803a, 803b, 803c and 803d. The insulating layers 802c, 802d, 802e and 802f are usually made of an oxide film material or a nitride film material or an inorganic non-metal insulating material or A gap is provided to automatically fill the normally insulating light-transmissive encapsulating material during the subsequent potting process or to embed the inorganic non-metallic insulating material in the void. Usually, the thickness or the gap is between several micrometers and several hundred micrometers. Layer 802c, 802d The adhesion between 802e and 802f and the two-layer substrates 803a, 803b, 803c and 803d is usually provided with a metal film for improving the adhesion between the insulating layer 802a and the two-layer substrates 803a, 803b, 803c and 803d, usually such as A metal material such as Qin, Lu, and crane, or an alloy layer composed of the above metal or a multilayer structure composed of the above metal and alloy, usually having a thickness of between several tens of nanometers and several hundred nanometers. Four sheets of two-layer substrates 803a, 803b The inner sides of 803c and 803d are provided with inclined side walls 810a, 810b, 810c and 810d and bare wire areas 811a, 811b, 811c and 81 Id. The oblique side walls 810a, 810b, 810c and 810d enclose the lower part of the potting light exiting space 809. The substrate electrodes 807a, 807b, 807c, 807d, 807e, 807f, 807g and 807h connected to the external power source or/and the signal interface are disposed outside the 801 and the two-layer substrates 803a, 803b, 803c and 803d, and the outer substrate 801 is fixedly disposed outside.孑L808a, 808b, 808c and 808d ° 099127098 Form No. A0101 Page 25 of 47 0992047611-0 201208155 [0080] The potting area top cofferdam 812 is placed on the two-layer substrates 803a, 803b, 8〇3c and 803d The top cofferdam 812 of the potting zone is usually made of a metal material or a ceramic material having good heat conductivity, wherein the metal material may be copper, aluminum 'tungsten, molybdenum and other metal materials or alloys thereof. The top cofferdam of the potting zone and the two-layer substrates 803a, 803b, 803c and 803d are superimposed in a sheet shape. Typically, the thickness of the top pot 812 of the potting zone is between a few hundred microns and a few millimeters. If the top cofferdam 812 of the potting zone is a conductive material, an insulating layer 802b is disposed between the top cofferdam 812 of the potting zone and the second substrate 8〇3a, 803b, 803c and 803d. The insulating layer 802b is typically made of an oxide or nitride film material, such as tantalum and nitrided, etc., typically having a thickness between a few microns and a few hundred microns. In order to enhance the adhesion between the edge layer 8〇2b and the top enclosing 812 of the potting zone and the two substrates 8〇3a, 803b, 803c and 803d, the insulating layer 802b and the top of the potting zone cofferdam 812 and the second layer A film for improving the adhesion between the substrates 803a, 803b, 803c and 803d is usually provided, and a metal material such as titanium, nickel and tungsten or an alloy layer composed of the above metals or a multilayer structure composed of the above metals and alloys is usually employed. Its thickness is between tens of nanometers and several hundred nanometers. If the top cofferdam 812 of the potting zone is a non-conductive material, a metal ruthenium film with improved dryness is disposed between the top cofferdam 812 of the potting zone and the second layer substrates 803a, 803b, 803c and 803d, usually using titanium, recording and A metal material such as tungsten or an alloy layer composed of the above metal or a multilayer structure composed of the above metals and alloys generally has a thickness of between several tens of nanometers and several hundred nanometers. The top cofferdam 81 2 of the potting area can also be pasted on the two-layer substrates 803a, 803b, 803c and 803d by pasting. [0081] The top side of the potting zone 81 2 inner side wall 81 3 encloses the enclosing light space 809 099127098 Form No. A0101 Page 26 of 47 0992047611-0 201208155 Upper part. The top of the top of the potting 812 is also provided with a heat sink array 8 i 4 to increase the heat dissipation area. “The diameter of a single heat sink is usually between a few hundred microns and a few millimeters. ❹ [0083] ❹ Four sets of LED chips 806a ' 80 6b ' 806c and 806d (two in each group) are placed on the solid crystal region 8〇1a of the underlying substrate 801, wherein the surface of the die-bonding region 801a of the underlying substrate A solid crystal material is provided. The led wafers 806a, 806b, 806c and 806d are such that one electrode is connected to the bonding line region on the solid crystal region 801a of the underlying substrate 8〇, and the other electrode is respectively connected to the two-layer substrate 8〇3a, 803b' 803c and The bare bond wire areas 811a, 811b, 811c and 811d of 803d are joined to form a joint pattern of four sets of LED chips 8〇6a, 806b, 806c and 806d with common anodes or cathodes but different cathodes or intestinal poles. The intra-group wafers are connected in parallel. Practical applications Each group can have a different number of wafers, and the intra-group wafers can also be serial or combined or combined. The four sets of chips can be the same or different wafers. If one red, one green, one red, one yellow is used, a high quality full color display point can be produced. In the eighth embodiment a, 8b embodiment, the two-layer substrate inner side wall 81 〇a, 81 Ob ' 810c and 810d form the lower part of the potting light-emitting space 809, and the top wall 813 of the top wall of the potting area forms a potting light-emitting space. Upper part of 809 lower part. The upper and lower areas of the potting light space 809 can be filled with the same or different light transmissive packaging materials. For example, a white LED that is generally described can be prepared by injecting a phosphor powder-containing Shixi gum and a potting 809 or a two-zone potting gel or epoxy resin in the second chamber of the potting light-emitting space. By modifying the appearance of the top of the potting zone, other light transmissive encapsulating materials and/or various types of pre-formed lenses or other optical components can be potted over the potting zone 809. Substrate 801 'four-piece two-layer substrate 803a, 803b, 803c and 803d 099127098 Form No. A0101 Page 27 of 47 0992047611-0 201208155 The shape of the enclosing area, the top of the potting area 81 2 can be the same or different The sizes can be the same or different. For example, square, rectangular, circular or other shapes are used. [0084] In the eighth embodiment a, 8b embodiment, the two-layer substrate inner side walls 81〇a, 810b, 810c and 810d form a lower part of the potting light-emitting space 8〇9, and the top side wall of the potting area of the potting area is 81 3 The upper portion of the potting light exiting space 8 〇9 may be symmetrical or asymmetrical, different or identical in shape to achieve different light shape and light intensity distribution, for example, square, rectangular, elliptical, circular or other shapes. The inner side of the two-layer substrate is 81, the edges of the inner layer 801, the 810c and 810d and the bottom substrate 801, and the inner side wall 813 of the potting area and the bare side of the two layers of the substrate 8〇3a, 803b' 803c and 803d The surface of the wire bond areas 811a, 811b, 811c and 81 Id may be perpendicular or beveled. 'One layer of the substrate inner side walls 810a' 810b, 810c and 81 0d and the potting area top coaming inner side wall 813 may themselves be smooth. A flat or smooth curved surface is used to control the distribution of light within the potting zone 8 〇 9 , which in turn changes the light efficiency, light profile and light intensity distribution. Generally, the above two-layer base is coated with a highly reflective material such as an Ag ◊ base substrate 801, a two-layer substrate 8 〇 3a by the inner oblique sidewalls 810a ' 81 Ob, 81 〇 c and 810d and the top surface of the top wall 813 of the potting zone. The exposed portions of the 803b '803c and 803d and the top of the potting zone 812 without the electrode or wire bond area are also typically coated with a highly reflective material, such as Ag, to reduce absorption. In order to avoid short circuit, the exposed portion of the electrode or the exposed portion of the wire area around the bracket may also be coated with an insulating film such as yttrium oxide and tantalum nitride. As shown in the ninth diagrams a and 9b, another embodiment of the chip package structure for an LED package of the present invention includes sub-substrate 901 and 〇2, at sub-9919127098, form number A0101, page 28/total page 47 0992047611-0 [0085] 201208155 A die bonding region provided on the substrate 901 and/or 902, an LED chip 906 disposed on the solid region by die bonding, and a bonding wire region and a substrate electrode 904a are disposed on the sub substrates 901 and 902, respectively. 904b, metal leads 9〇5a and 905b. [0086] In the present embodiment, the sub-substrates 901 and 902 are non-conductive sub-substrates, for example, ceramic substrates or the like, and are spliced in a horizontal direction to form a single layer. At the same time, in order to achieve an electrically conductive connection between the bonding wire region and the substrate electrodes 9〇4a and 9〇4b, conductive metal films can be formed on the upper surfaces of the sub-substrates 901 and 902, for example, metal materials such as chin, nickel and tungsten are used. Or an alloy layer composed of the above metals or a multilayer structure composed of the above metals and alloys, usually having a thickness of between several tens of nanometers and a few nanometers. Further, the solid crystal region may be arbitrarily disposed on the sub-substrate 9〇1 and 9〇2 as needed, for example, a pit provided on the surface of the sub-substrate, and the pit itself constitutes a potting light-emitting space of the light-emitting chip. Of course, it is also possible to provide a raised cofferdam around the dimple to form a better potting light exiting space. [0089] It can be understood that the structural features of the above embodiments need to be combined in any way to form a new embodiment. The scope of the present invention is not limited to the above embodiments, and should be any of the above structural features. combination. Since the above-mentioned light-emitting chip package structure does not contain any polymer material, its resistance to ultraviolet light irradiation and high-low temperature impact is strong, and is basically not affected by the environment, thereby greatly improving the reliability of the LED, and the above-mentioned light-emitting chip package structure can withstand 200. °C-500. The temperature above 〇 allows the LED wafer to be attached to the underlying substrate by eutectic bonding techniques. The bottom base plate is then screwed to other components or heat sinks through the fixed through holes to achieve a very good heat dissipation path. If the underlying substrate and other components or 099127098 Form No. A0101 Page 29 of 47 0992047611-0 201208155 heat sink can be filled with heat-dissipating bonding material, the heat dissipation performance will be better. At high current or high power, the thermal resistance of the interface is very low, and the whole bracket is a good metal-based conductor, so that the heat generated by the LED chip can be quickly transmitted, so that the heat accumulation in the LED bracket is minimized, thereby greatly improving the LED chip. Anti-aging and reliability. In addition, the package structure can be applied to other LED packages as well as packages for LED chips. BRIEF DESCRIPTION OF THE DRAWINGS [0090] The present invention will be further described with reference to the accompanying drawings and embodiments, in which: [0091] The first figure: a conventional bracket and connection method for LED packaging. [0092] Second figure: Another common bracket and connection method for high power LED packages. Third FIG. 3, 3b is a schematic view of a first embodiment of the light emitting chip package structure of the present invention. Fourth FIG. 4, 4b is a schematic view of a second embodiment of the light emitting chip package structure of the present invention. [0095] Fifth Figures a, 5b: A schematic view of a third embodiment of the light emitting chip package structure of the present invention. [0096] Fig. 6a, 6b are schematic views of a fourth embodiment of the light emitting chip package structure of the present invention. [0097] Seventh FIGS. a, 7b are schematic views of a fifth embodiment of the light emitting chip package structure of the present invention. 099127098 Form No. A0101 Page 30 of 47 0992047611-0 201208155 [0098] Eighth Figures a, 8b: A schematic view of a sixth embodiment of the light emitting chip package structure of the present invention. Ninth Diagram a, 9b: A schematic view of a seventh embodiment of the light-emitting chip package structure of the present invention. [Explanation of main component symbols] Electrode holder 101, 104 LED wafer 102 [0101] Metal lead 103a, 103b Bracket connecting piece 105 [0102] Base 201 LED chip 202 Metal lead 203a, 203b Electrode piece 204a , 204b [0104] reflective cup 205 sub-substrate 301, 302 [0105] metal lead 303, 304 underlying sub-substrate 305 [0106] luminescent wafer 306 insulating tape 307 [0107] substrate electrode 308a, 308b, 3: scale l: p " : .r.-'* 'IliiU . i -; !./'i - ' [0108] 〇[0109] ..~3, 丨β.' :...-.l~% «; Potting Cofferdam 30 底层 Substrate 401 Insulation Layer 402 [0110] Two-layer Substrate 403 Bottom Wire Bond Region 404a [0111] Top Shield Wire 404b Metal Leads 405a, 405b [0112] LED Wafer 406 Bottom Electrode 407a [0113] Top Electrode 407b Fixed Through Hole 408a, 408b, 408c, 408d [0114] Potting light exiting space 409 lower side wall 410a 099127098 Form No. A0101 Page 31 / Total 47 page 0992047611-0 201208155 [0115] [0117] [0118] [0119] [0120 [0126] [0128] [0126] [0128] [0128] [0133] [0133] 099127098 upper side wall 410b bottom substrate 501 Insulation layer 502 two-layer substrate 503 two-layer substrate bank 503a substrate wire region 504a, 504b metal wire 505a, 505b LED chip 506 substrate electrode 507a, 507b fixed through hole 508a, 508b, 508c, 508d potting area cofferdam 509 oblique Side wall surface 510 upper surface 510a upper side wall 511a lower side wall 511b bottom substrate 601 insulating layer 602 two-layer substrate 603a, 603b partitioning strip 603c, 603d bonding line area 604a, 604b connecting line 605 metal lead 605a, 605b, 605c, 605b LED chip 606 two-layer substrate electrodes 607a, 607b fixed through holes 608a, 608b, 608c, 608d potting light space 609 bottom substrate 701 insulating layer 702a, 702b two-layer substrate 703 bond wire area 704a, 704b metal lead 705a, 705b LED chip 706 substrate Electrodes 707a, 707b, 707c, 707d, 707e, 707f fixed through holes 708a, 708b, 708c, 708d Form No. A0101 Page 32 / Total 47 Page 0992047611-0 201208155 [0134] Encapsulating the light-emitting space 709 inner side wall 710a [0135] Top Heatsink Array 711 Hot Column Array Substrate 711a [0136] Heat Sink 712 Heat Sink Array 713 [0138] Heat Sink 714 [0139] Substrate 801 Solid Crystal Area 801a [0140] 〇 [ 0141] Insulating layers 802a, 802b, 802c, 802d, 802e, 802f Two-layer substrates 803a, 803b, 803c, 803d [0142] Metal leads 805 [0143] LED wafers 80 6a, 806b, 80 6c, 806d [0144] Substrate electrodes 807a, 807b, 807c, 807d, 807e, 807f, 807g, 807h [0145] The fixed through holes 808a, 808b, 808c, 808d 灌 enclose the light space 809 oblique side walls 810a' 810b, 810c, 810d [0147] 811a, 811b, 811c, 811d top bank 812 [0148] inner side wall 813 heat sink column array 814 [0149] sub-substrate 901, 902 substrate electrode 904a, 904b [0150] metal lead 905a, 905b LED chip 906 099127098 Form No. A0101 33 pages / total 47 pages 0992047611-0

Claims (1)

201208155 VII. Patent application scope: 1. A light-emitting chip package structure, comprising: at least one substrate single/0, at least one solid crystal region disposed on the substrate unit, mounted on the solid-state region At least one illuminating wafer 'and at least two substrate electrodes that are electrically isolated from each other are disposed on the substrate unit; the substrate unit includes at least two sub-substrates insulated from each other; The substrate unit is electrically connected to the substrate electrode. The illuminating chip package structure of the invention, wherein the sub-substrate is a conductive sub-substrate, and an insulating layer or an insulating tape is disposed between the adjacent conductive sub-substrates, or a gap is left between the adjacent conductive sub-substrate, or an insulating potting material is filled in the gap; or the sub-substrate is a non-conductive sub-substrate, and the non-conductive sub-substrate is disposed on the non-conductive sub-substrate The conductive metal film is electrically connected to the conductive metal film corresponding to the substrate electrode; or the sub-substrate includes a conductive sub-substrate and a non-conductive sub-substrate, and the illuminating chip is disposed on the non-conductive sub-substrate Electrically connected to a conductive metal film corresponding to the substrate electrode. 3. The illuminating chip package structure according to claim 1, wherein the substrate unit is a single-layer substrate unit comprising at least two sub-substrates insulated from each other and spliced to each other in a horizontal direction; or The substrate unit 70 is a multi-layer substrate unit including at least two sub-substrates insulated from each other and superimposed on each other in a vertical direction; or the substrate unit is a multi-layer composite substrate unit including at least one of the sub-substrates and at least a single-layer substrate unit, the sub-substrate and the single 099127098 Form No. A0101, page 34/47 pages 0992047611 201208155, the substrate units are insulated from each other and superposed on each other in the vertical direction; the single-layer substrate unit includes at least two The sub-substrates are insulated from each other and spliced to each other in the horizontal direction. 4. The light emitting chip package structure according to claim 3, wherein the solid crystal regions are all disposed on the same sub-substrate constituting the single-layer substrate unit, or are respectively disposed in a constitution On the different sub-substrates of the single-layer substrate unit. 5. The light emitting chip package structure according to claim 3, wherein the solid crystal regions are all disposed on the same sub-substrate constituting the multi-layer substrate unit, or are respectively disposed to constitute the On the different sub-substrates of the multi-layer substrate unit; or, the solid crystal regions are all disposed on the same sub-substrate constituting the multi-layer composite substrate unit, or are respectively disposed in different places constituting the multi-layer composite substrate unit On the substrate. 6. The illuminating chip package structure according to claim 5, wherein the die bonding region is disposed on the non-top layer sub-substrate, and is located on an upper layer of the sub-substrate on which the die bonding region is disposed. The sub-substrate is provided with an opening corresponding to the die-bonding region, and an inner sidewall of the opening constitutes a potting light-emitting space and a reflective sidewall of the light-emitting chip placed in the die-forming region. The illuminating chip package structure of claim 4, 5 or 6, wherein the die bonding region is disposed on an upper surface of the sub-substrate; or is disposed on a surface of the sub-substrate Within the pit, the inner sidewall of the recess constitutes a potting light exiting space and a reflective sidewall of the light emitting wafer disposed within the die attach region. 8. The light emitting chip package structure according to claim 7, wherein the solid crystal region is provided with a raised coaming; the inner circumference of the cofferdam is 099127098, form number A0101, page 35/total 47 pages 0992047611-0 201208155 The sidewalls constitute a potting light exiting space and a reflective sidewall of the light-emitting wafer placed in the die-bonding region. 9. The illuminating chip package structure according to claim 7, wherein the surface of the die bonding region and the inner sidewall of the potting light-emitting space are coated with a single or multiple layers of metal reflective film and/or Or a non-metallic reflective film. The illuminating chip package structure of claim 7, wherein the inner side wall of the potting light-emitting space comprises a smooth surface perpendicular to a surface of the die-bonding region, and/or The surface of the crystal region is a smooth bevel having an angle greater than 90 degrees, and/or a smooth arc surface extending from the surface of the crystal-crystalline region toward the surface of the substrate unit. The illuminating chip package structure of claim 7, wherein the inner sidewall of the potting light-emitting space comprises at least one step, and the surface of the stepped surface of the step is disposed with the solid crystal The sub-substrate surface of the region or the sub-substrate above the sub-substrate having the solid crystal region. The illuminating chip package structure according to claim 1, wherein the illuminating wafer is placed in a center of the die bonding region and electrically connected to a corresponding substrate electrode, respectively; or the illuminating There are a plurality of wafers, and a plurality of the light-emitting wafers are electrically connected to the corresponding substrate electrodes in series or in parallel or in series. The illuminating chip package structure according to claim 1, wherein a vicinity of the die bonding region is provided with a bonding wire region electrically connected to the corresponding substrate electrode, wherein the luminescent wafers are respectively electrically conductive. Connected to the corresponding wire bond zone, or a plurality of the light-emitting wafers are electrically connected to the corresponding wire bond zone in series or parallel or in series and parallel. The illuminating chip package structure according to claim 1, wherein the exposed surface of the substrate unit is provided with a dispersion of increased heat dissipation surface area. 099127098 Form No. 1010101 Page 36/47 pages 0992047611-0 201208155 The thermal structure, and/or is coated with a heat dissipating material that has an increased surface heat radiation capability and/or thermal conductivity. The illuminating chip package structure of claim 2, wherein the insulating layer is one or more layers of a composite insulating film; one or more layers of transition between the insulating layer and the sub-substrate Metal film and/or alloy film. ❹ 0992047611-0 099127098 Form No. A0101 Page 37 of 47