CN101908379B - 基于访问时间调整对非易失性半导体存储器的访问 - Google Patents

基于访问时间调整对非易失性半导体存储器的访问 Download PDF

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CN101908379B
CN101908379B CN201010134420.0A CN201010134420A CN101908379B CN 101908379 B CN101908379 B CN 101908379B CN 201010134420 A CN201010134420 A CN 201010134420A CN 101908379 B CN101908379 B CN 101908379B
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CN101908379A (zh
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M-M·L·西马
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Western Digital Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/30—Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory

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Abstract

公开了一种非易失性的半导体存储器，该存储器包括第一存储装置和可操作用于向第一存储装置发出访问命令的控制电路。在状态延迟之后向第一存储装置请求命令状态。当命令状态指示第一存储器已经完成命令时，测量对该存储装置的第一访问时间。之后，响应该访问时间修改第一存储装置的访问序列。

Description

基于访问时间调整对非易失性半导体存储器的访问
背景技术
非易失性半导体存储器可以用作计算机系统(诸如台式机、笔记本计算机、便携式计算机等)或消费设备(诸如音乐播放器、手机、照相机等)或其他适当应用的大容量存储装置。非易失性半导体存储器可以包括一个或多个存储装置(诸如闪存)和用于访问每个存储装置的控制电路。每个存储装置与一地址总线和一数据总线以及多个接口控制线耦合。当向存储装置发出写命令或擦除命令时，控制电路配置地址总线和多个控制线，并且接着在数据总线上传输命令数据(和用于写操作的用户数据)。接收命令后，存储装置在“访问时间”内在内部执行该命令。为了确定存储装置何时完成执行该命令，控制电路通常通过发出“命令状态”请求来轮询存储装置，其中存储装置向控制电路发送命令状态寄存器的内容。
图1A图示说明了使用现有技术序列写或擦除存储装置时的一个问题。图1A中的波形表示存储装置的可用/占用线。在传输命令数据(中的串行数据)后(以及用于写操作的用户数据)，控制电路延迟预定的时间(STATUS_DELAY)并且接着开始轮询存储装置，以获得命令状态寄存器的内容。当命令状态寄存器指示先前的命令已经成功完成时，控制电路可向存储装置发送下一个命令。根据特定存储装置的速度，状态延迟时间(STATUS_DELAY)可能明显短于实际访问时间，因此控制电路可能在存储器完成处理命令之前开始轮询状态命令寄存器。这是不期望有的，因为对状态命令寄存器过多的轮询消耗电池供电的主机设备的电能。
图1B说明了使用现有技术序列通过单个通道写第一和第二存储装置时的另一个问题。在图1B显示的例子中，第二存储装置的访问时间比第一存储装置的访问时间短。在向第一存储装置发送命令数据之后，命令数据立即在第一存储装置的访问时间内被发送到第二存储装置。当第一存储装置的命令状态寄存器指示已经成功完成该命令时，向第一存储装置发送下一个命令。然而，在传输下一个命令给第一存储装置时，第二存储装置可能也准备接收下一个命令，但是必须等待控制电路完成下一个命令至第一存储装置的发送(即，在访问共享总线时存在冲突)。图1B中显示的等待时间是不期望有的，因为其降低了非易失性半导体存储器的整体性能(吞吐量)。
附图说明
图1A图示说明现有技术对存储装置的访问，其中状态延迟可明显短于访问时间，这就增加了发送到存储装置的命令状态请求的数量。
图1B图示说明现有技术通过共享总线对两个存储装置访问，其中由于存储装置具有不同的访问时间，所以可能会发生冲突。
图2A显示了根据本发明的一个实施例的非易失性半导体存储器，该存储器包括控制电路访问的第一和第二存储装置。
图2B是控制电路根据本发明的一个实施例执行的流程图，其中存储装置的访问时间被测量，以修改多个存储装置的访问序列。
图3A显示现有技术对存储装置的擦除操作，其中状态延迟明显地短于访问时间，这就增加了发送到存储装置的命令状态请求的数量。
图3B图示说明了本发明的一个实施例，其中通过响应测量得到的存储时间来调整状态延迟，以此修改存储装置的访问序列，从而减少发送到存储装置的命令状态请求的数量。
图3C图示说明了本发明的一个实施例，其中通过修改向存储装置发送命令的顺序来修改存储装置的访问序列，从而通过减少或避免由于冲突造成的等待时间来改善性能。
图4是根据本发明的一个实施例的流程图，其中通过响应测量得到的访问时间来调整状态延迟，从而修改存储装置的访问序列。
图5是根据本发明的一个实施例的流程图，其中，通过修改向存储装置发送命令的顺序来修改存储装置的访问序列。
图6A显示了本发明的一个实施例，其中控制电路在分离的、专用的总线上访问每个存储装置。
图6B显示了本发明的一个实施例，其中控制电路在共享的总线上访问每个存储装置。
具体实施方式
图2A显示了根据本发明的一个实施例的非易失性半导体存储器2，该存储器包括第一存储装置4A和控制电路6，该控制电路可操作用来执行图2B中显示的流程图。发出访问命令到第一存储装置(步骤8)。在状态延迟之后请求来自第一存储装置的命令状态(步骤10)。当命令状态指示第一存储装置已经完成命令(步骤12)时，测量存储装置的第一访问时间。接着，响应访问时间修改第一存储装置的访问序列(步骤16)。
图2A的实施例中的存储装置4A可以包括任何适当的装置，例如NAND闪存。对典型的NAND闪存的访问是通过以下方式实现：在地址/数据总线(ADDR/DATA)上发送相应的地址和发送/接收数据，并且认定适当的控制线(例如，地址锁存使能(ALE)、命令锁存使能(CLE)、芯片使能(CE)等等)。在图2A的实施例中，非易失性半导体存储器2包括多个存储装置(例如4A和4B)，控制电路6通过在地址/数据总线(可以是并行总线或串行总线)上发送合适的地址访问这些存储装置。在一个实施例中，控制电路6通过初始化计数器(步骤18)测量图2B中的每个存储装置的访问时间，该计数器的值逐步增加(步骤20)，直到已经完成对所有存储装置的访问时间的测量(步骤22)。
图3A显示了现有技术对存储装置的擦除操作，其中，在发送擦除命令后，控制电路等待标称状态延迟并且开始通过向存储装置请求命令状态来轮询存储装置。然而，标称状态延迟可能明显地短于存储装置实际的访问时间，因此控制电路可能在需要轮询之前更早地开始命令状态的轮询，从而导致不期望的电能损耗。在图3B所示的本发明的一个实施例中，控制电路测量存储装置的访问时间，之后根据访问时间调整状态延迟，以此修改存储装置的访问序列。通过这种方式，控制电路在更加理想的时间点上开始命令状态的轮询，从而通过减少对命令状态的请求数量降低电能消耗，如图3B所示。
在一个实施例中，执行擦除命令所需的访问时间与执行写命令所需的访问时间不同。因此，在一个实施例中，对应于不同类型的访问命令优化了状态延迟(例如，为擦除命令优化的状态延迟和为写命令优化的状态延迟)。
图3C显示了本发明的一个实施例，其中通过选择根据访问时间发送写命令的顺序来修改存储装置的访问序列。例如，在一个实施例中，使用将数据条带化的(“striping”)技术将数据写入存储装置中，以此优化性能。写命令的数据块被有序地存储，以特定的顺序每次向每个所选的存储装置存储一数据块。以这种方式，在并发地处理写命令时每个存储装置的访问时间会重叠，而不会连续地将每个块存储到单个存储装置，后者需要控制电路在发送下一个数据块之前等待该存储装置的访问时间。
在图3C的例子中，第二存储装置具有比第一存储装置更短的访问时间，因此，第一写命令和相应的数据块被发送到第二存储装置。在第二存储装置的访问时间内，控制电路向第一存储装置发送第二写命令和相应的数据块。当第二存储装置完成处理第一写命令时，该存储装置能从控制电路6立即接收新的写命令。相似地，当第一存储装置完成处理第二写命令时，该存储装置能从控制电路立即接收新的写命令。因此，该实施例可通过降低或避免试图在共享的总线上同时访问两个或更多的存储装置时的冲突来减少或去除图1B的现有技术顺序中显示的等待时间。
图4是根据本发明实施例的流程图，该流程图是图2B中的流程图的扩展，其中修改存储装置的访问序列的步骤(图2B中的步骤16)包括图3B所示的调整存储装置的状态延迟(步骤24)。图5是根据本发明的实施例的流程图，该流程图是图2B中的流程图的扩展，其中修改存储装置的访问序列的步骤(图2B中的步骤16)包括图3C所示的修改向存储装置发送命令的顺序(步骤26)。
图6A显示了根据本发明实施例的非易失性半导体存储器2，其中控制电路6在分离的、专用的总线28A和28B上访问每个存储装置(例如4A和4B)。在此实施例中，不是必须将发送的命令按照访问时间排序，因为永远不会存在试图同时访问共享总线的冲突。然而，该实施例仍旧会受益于优化状态延迟，以此来减少图3B图示说明的对命令状态的请求数量。
图6B显示了根据本发明一个实施例的非易失性半导体存储器2，其中控制电路6在共享总线28上访问每个存储装置(例如4A和4B)。共享总线28在图6B中概念性地图示说明为，配置多路复用器(MUX)30以访问期望的存储装置。然而，共享总线可能以任何合适的方式实现，例如具有专用的芯片使能(CE)线的有线-OR应用，其使期望的存储装置能够被访问。该实施例受益于优化状态延迟以降低命令状态请求的数量，还受益于按照访问时间对发送的命令排序以降低或避免冲突。
测量每个存储装置的访问时间和修改访问序列的过程可以在任何合适的时间进行。在一个实施例中，在非易失性半导体存储器的生产过程中测量访问时间和修改访问序列。在其他实施例中，访问时间可在非易失性半导体存储器2的整个使用期变化和/或受环境条件(例如温度)的影响。因此，在一个实施例中，可以在非易失性半导体存储器被供电的任何时间测量访问时间，或者在非易失性半导体存储器的使用期内周期性地测量访问时间，或者响应探测到的环境条件的改变而测量访问时间，或者响应从主机系统接收到的命令而测量访问时间。
本发明的非易失性半导体存储器2可以用于任何合适的应用中，例如固态硬盘驱动(SSD)或其他存储卡或存储棒。此外，非易失性半导体存储器2可以使用任何合适的呈现不同访问时间(即，擦除命令和/或写命令的不同的访问时间)的存储装置4A和4B。

Claims (12)

1.一种非易失性半导体存储器，包括第一存储装置、第二存储装置和控制电路，所述控制电路可操作用于：
向所述第一存储装置发出访问命令；
在状态延迟后向所述第一存储装置请求命令状态；
当所述命令状态指示所述第一存储装置已经完成所述访问命令时，测量所述第一存储装置的第一访问时间；
测量所述第二存储装置的第二访问时间；以及
响应所述第一访问时间，调整所述状态延迟。
2.根据权利要求1所述的非易失性半导体存储器，其中所述访问命令包括写命令和擦除命令中的一种。
3.根据权利要求1所述的非易失性半导体存储器，其中，所述控制电路进一步可操作用于通过共享总线访问所述第一存储装置和所述第二存储装置。
4.根据权利要求3所述的非易失性半导体存储器，其中，所述控制电路进一步可操作用于修改所述控制电路在所述共享总线上向所述第一存储装置和所述第二存储装置发送命令的顺序。
5.根据权利要求4所述的非易失性半导体存储器，其中，所述控制电路进一步可操作用于：
响应所述第一访问时间和第二访问时间第一次选择所述第一存储装置和所述第二存储装置之一；
向第一次选择的存储装置发送第一命令；
响应所述第一访问时间和第二访问时间第二次选择所述第一存储装置和所述第二存储装置中的另一个；以及
向第一次选择的存储装置发送所述第一命令之后，向第二次选择的存储装置发送第二命令。
6.根据权利要求5所述的非易失性半导体存储器，其中，第一次选择的存储装置的访问时间比第二次选择的存储装置的访问时间短。
7.一种操作具有第一存储装置和第二存储装置的非易失性半导体存储器的方法，该方法包括：
向所述第一存储装置发出访问命令；
在状态延迟后向所述第一存储装置请求命令状态；
当所述命令状态指示所述第一存储装置已经完成所述访问命令时，测量所述第一存储装置的第一访问时间；
测量所述第二存储装置的第二访问时间；以及
响应所述第一访问时间，调整所述状态延迟。
8.根据权利要求7所述的方法，其中，所述访问命令包括写命令和擦除命令之一。
9.根据权利要求7所述的方法，进一步包括通过共享总线访问所述第一存储装置和第二存储装置。
10.根据权利要求9所述的方法，进一步包括修改在所述共享总线上向所述第一存储装置和第二存储装置发送命令的顺序。
11.根据权利要求10所述的方法，其进一步包括：
响应所述第一访问时间和第二访问时间第一次选择所述第一存储装置和所述第二存储装置之一；
向第一次选择的存储装置发送第一命令；
响应所述第一访问时间和第二访问时间第二次选择所述第一存储装置和所述第二存储装置中的另一个；以及
向第一次选择的存储装置发送所述第一命令之后，向第二次选择的存储装置发送第二命令。
12.根据权利要求11所述的方法，其中，所述第一次选择的存储装置的访问时间比第二次选择的存储装置的访问时间短。
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