CN101859594A

CN101859594A - Self-timing write tracking type static random memory integrated with weak write test function and calibration method thereof

Info

Publication number: CN101859594A
Application number: CN 201010214627
Authority: CN
Inventors: 张昭勇; 郑坚斌
Original assignee: Aicestar Technology Suzhou Corp
Current assignee: Zhiyuan Microelectronics (suzhou) Co Ltd
Priority date: 2010-07-01
Filing date: 2010-07-01
Publication date: 2010-10-13
Anticipated expiration: 2030-07-01
Also published as: CN101859594B

Abstract

The invention relates to a self-timing writing tracking type static random memory integrated with the weak write test function. A writing tracking word line array and a writing tracking bit line array which are arranged in the memory are used to realize load tracking on the word line and bit line; the writing tracking word line array is provided with a plurality of analog word line load SRAM units, the analog word line signal thereof is connected with the analog word line driver and the word line of an integrated writing tracking SRAM unit; the writing tracking bit line array comprises a plurality of integrated writing tracking SRAM units and analog bit line load SRAM units; the writing tracking bit lines are connected with the output end of a programmable integrated analog write driver, the writing tracking complementary bit lines are connected to a writing tracking reset circuit, and the power source of the integrated writing tracking SRAM unit is connected on the VREF of a virtual power with an external detection end. The memory can be not only used in ordinary time-write control, but also in the time-write control under weak write test function mode; and the weak write test calibration method can be used to simplify the process of weak write test calibration.

Description

Integrated with weak is write the self-timing writing tracking type static random access memory and the calibration steps thereof of test function

Technical field:

The present invention relates to a kind of static RAM, particularly a kind of integrated with weak is write the self-timing writing tracking type static random access memory and the calibration steps thereof of test function.

Background technology:

Static RAM (being SRAM) is a kind of short-access storage that is widely used, and its data keep only needing power supply to get final product, and need not to refresh.Static RAM might produce some defective units in process, cause it to read out wrong data.These defected memory cells have number of different types, wherein just comprise causing the defected memory cell that keeps wrong.This relevant connection place that keeps mistake might occur in PMOS pipe in the storage unit, being connected between PMOS pipe and the power supply for example, if this connection exists bigger resistance can cause the output drive strength of PMOS pipe to die down, and then can cause that data keep incessantly (the static ram cell state turnover promptly takes place).In order to screen out the static RAM that has this mistake, therefore just need some test patterns to discern this maintenance defective.Traditional maintenance defect test needs long time out, can make the test duration become very long like this, and increases testing cost.The maintenance defect test method of comparatively knowing in recent years is that (WWTM is Weak Write Test Mode to weak write test mode, referring to paper Meixner et al., " Weak Write Test Mode:An SRAM Cell Stability Design for Test Technique ", International Test Conference 1997, pp.1043-1052), write a little less than this method is used and write a little less than driving circuit carries out storage unit, can judge that if the storing value of storage unit is rewritten there is the maintenance defective in this storage unit, and the storing value of good storage unit will can not rewritten.Though weak write test mode can reduce the test duration with respect to traditional maintenance defect test, but write common employing regular time control a little less than in the method, 50 nanoseconds for example, the too short or oversize potential problems of the pulsewidth of writing a little less than can existing like this, if a little less than the pulsewidth write too short then might cause some to exist keeping the storage unit of defectives not to be found; If a little less than the pulsewidth write oversize then can waste the test duration and increase testing cost.

The common write time control of static RAM roughly has three kinds of methods: the first uses logic time-delay circuit as writing sequential control (referring to US5546355A), its shortcoming is the write time of delay circuit and memory circuitry and not exclusively follows the tracks of (tracking), might cause storer to write performance degradation; It two is to write control to use the tracking of reading when reading, and promotes to some extent though the method writes performance than first method to storer, and the mechanism that writes of static RAM is different with reading mechanism, and its time is also inequality.It is narrow and cause and write failure very likely can to cause writing fashionable pulsewidth in this way, causes that perhaps to write fashionable pulsewidth wide and cause waste of time; It three is to use and writes tracking and control the write time (referring to US5715201A, US6201757B1 and US6392957B1), this method use is write trace memory unit (its unit is identical or approximate with common memory cell) and is realized writing time sequence control, to write tracking behavior identical with the behavior that writes usually or approximate because of it, so this method can further improve the write time control ability of static RAM.United States Patent (USP) has disclosed a kind of sequential control circuit and method of following the tracks of of writing for No. 5715201, though the method has used the trace memory unit as the core control that writes sequential, the method is not simulated the influence to the write time of word line load and NMOS transfer tube.United States Patent (USP) has then disclosed other two kinds for No. 6201757 and No. 6392957 and has write the tracking sequential control circuit, though the tracking path of writing of these two kinds of methods all has simulation word line load and NMOS transfer tube, but only used a memory write tracking cell as the tracking Control that writes sequential, when technology generation deviation, can cause that very likely control timing has greatly changed, and then cause that bigger variation appears in the write performance of storer.

Need in the test to select to write driving force a little less than suitable weak writing in addition, if a little less than write driving circuit driving force select too by force, might cause good storage unit to be filtered out mistakenly so; And if a little less than write driving circuit driving force select too lowly, then very likely detect the storage unit that keeps defective less than existing.Therefore write calibration a little less than doing some before being necessary a little less than carrying out, to write test and write driving force a little less than great to determine employing.United States Patent (USP) has disclosed a kind of calibration steps and flow process of weak write test mode for No. 7076376, and the method has greatly been saved testing cost and time and reduced the calibration difficulty with respect to former focused ion beam (FIB) method.The part but this calibration steps also comes with some shortcomings, for example needed testing current can increase difficulty of test and testing cost in the calibration flow process, writes weak that needed alignment unit (CALRAM) step that reads will increase the alignment time in the calibration process in addition.

Summary of the invention:

In order to solve the problems of the technologies described above, the invention provides self-timing writing tracking type static random access memory and the calibration steps thereof of writing test function a little less than a kind of being integrated with.

The technical solution adopted for the present invention to solve the technical problems is: a kind of integrated with weak is write the self-timing writing tracking type static random access memory of test function, except that being provided with memory array, having the input/output circuitry and word line driver array and state control circuit of weak write test mode, also be provided with:

Write and follow the tracks of reset circuit, virtual power supply generation circuit and simulation word line driver;

Write the trace bit linear array, follow the tracks of sram cell and mimotope linear load sram cell is formed by a plurality of integrated writing, described integrated writing followed the tracks of writing of sram cell and followed the tracks of paratope line and be connected to write and follow the tracks of on the reset circuit, its power supply is connected on the virtual power supply that is provided with end of probe, and the word line of described mimotope linear load sram cell is put ground;

Write the trace word linear array, be made up of a plurality of simulation word line load sram cells, its simulation word-line signal links to each other with the integrated word line of following the tracks of sram cell of writing with the simulation word line driver, and its bit line is unsettled;

Integrated simulation write driver able to programme, its output terminal are followed the tracks of bit line with writing of mimotope linear load sram cell and are connected with the integrated tracking bit line of writing of following the tracks of sram cell of writing.

Can the self-timing writing tracking type static random access memory that integrated with weak is write test function be described in further detail by following content:

Described integrated simulation write driver able to programme is provided with PMOS pipe, described PMOS pipe source electrode links to each other with power supply, its drain electrode is connected with the drain electrode of a NMOS pipe and places to write to be followed the tracks of on the bit line, its grid is connected with the grid of this NMOS pipe, and the source electrode of this NMOS pipe links to each other with a plurality of drain electrodes with NMOS pipe of different channel dimensions, described a plurality of source electrode with NMOS pipe of different channel dimensions is connected to ground jointly, the grid of writing other several NMOS pipes of voltage a little less than the grid of one of them NMOS pipe is connected to then is connected with logic controller, writes voltage a little less than described and is connected and writes on the voltage generator a little less than being provided with.

Described virtual power supply produces circuit by virtual power supply and provides, described virtual power supply produces circuit by being parallel to by PMOS pipe, the 2nd PMOS pipe source, drain electrode between supply voltage and the virtual power supply and structure is formed, the grid of a described PMOS pipe is connected with variable voltage signal, and the grid of described the 2nd PMOS pipe is connected with the test pattern enable signal.

Described variable voltage signal is by providing by dual mode: 1. provided by external circuit or input pin signal; 2. provide by the Vpbias generator, described Vpbias generator comprises: one can select to be connected in series first resistance again after the parallel connection of resistance circuit and NMOS pipe, describedly select resistance circuit to connect respectively to be formed in parallel again behind the corresponding resistance by three NMOS pipe, the other end of described first resistance is connected with the drain electrode of the 3rd PMOS pipe, the source electrode of described the 3rd PMOS pipe connects supply voltage, the grid of a grid and a NMOS pipe is connected on the output terminal of the phase inverter of being controlled by the test pattern enable signal jointly, the described source electrode of the NMOS pipe in the resistance circuit and the source ground of a NMOS pipe selected.

The described integrated tracking sram cell of writing is formed by standard 6 pipe sram cells modifications, and it writes leakage, the source shorted of following the tracks of the 2nd NMOS pipe on the paratope line.

Described write to follow the tracks of be provided with one in the reset circuit and write to follow the tracks of and finish monitor signal end and reset circuit, described write to follow the tracks of finish the monitor signal end at the test pattern enable signal during for " 1 ", receive inside and write and follow the tracks of end signal and output synchronously.

The present invention also provides this integrated with weak to write the calibration steps of the self-timing writing tracking type static random access memory of test function except the self-timing writing tracking type static random access memory that a kind of integrated with weak is provided writes test function:

(1) sets a defective according to the test target of weak write test mode and keep resistance value R.

(2) external control signal of choosing a variable voltage Vpbias voltage or choosing a certain setting produces corresponding variable voltage Vpbias.

(3) keep resistance value R ' by end of probe measure analog defective.

(4) compare test as a result R ' with set whether approximately equal of resistance value R, if approximately equal then can enter (5) step of calibration flow process; If approximately equal was not then returned for (2) step and is chosen new variable voltage Vpbias voltage or its corresponding setting.

(5) variable voltage Vpbias voltage or its correspondence of preserving for (2) this moment in step set.

(6) choose the setting of writing voltage Vnbias a little less than in the of one, the voltage of writing voltage Vnbias a little less than choose is too strong and cause good storage unit to be filtered out mistakenly, and the setting of writing voltage Vnbias voltage a little less than should be from correspondence when choosing this setting for the first time the most weak begins to choose.

(7) carry out write order, write the integrated tracking sram cell of writing a little less than the meeting of simulation write driver.

(8) observation is write and follow the tracks of to be finished monitor signal and whether become low level by high level then, if this signal becomes (9) step that low level then can enter the calibration flow process by high level; To write voltage a little less than then representing too low if this signal is still for high level, and the calibration requirements of process was returned for (6) step and chosen a setting of writing voltage Vnbias a little less than new.

(9) preserve at last (6) step this moment corresponding a little less than write the setting of voltage Vnbias and use this and be set to memory chip WWTM test.

Integrated self-timing writing tracking circuit proposed by the invention not only can use in the control of common write time, and the write time control can be applied to weak write test mode the time, can save chip area like this.Write the process of writing detection calibration a little less than detection calibration method and flow process have then further been simplified a little less than proposed by the invention in addition.

Description of drawings:

Fig. 1 is a kind of system architecture synoptic diagram of the present invention.

Fig. 2 is the input/output circuitry with weak write test mode (the being I/O Circuits WithWWTM) structural drawing among Fig. 1.

Fig. 3 is able to programme integrated simulation write driver (the being Dummy Write Driver) circuit diagram among Fig. 1.

Fig. 4 is virtual power supply (V _REF) the generation circuit.Wherein (a) variable voltage (Vpbias) is provided by external circuit or input pin; (b) variable voltage (Vpbias) is provided by variable voltage (Vpbias) generator.

Fig. 5 is for writing the tracking reset circuit among Fig. 1.

Fig. 6 is four kinds of static random access memory cell circuit diagrams among Fig. 1.Wherein (a) standard 6 is managed sram cells (being Memory Cell); (b) simulation word line load sram cell (being Dummy Cell); (c) integrated writing followed the tracks of sram cell (being Reference Cell); (d) mimotope linear load sram cell (being Load Ref.Cell).

Fig. 7 is weak write test mode calibration process flow diagram.

The main element symbol description:

Dummy Write Driver: integrated simulation write driver able to programme

Word Line Drivers: word line driver array

Control Circuitry: state control circuit

I/O Circuits: input/output circuitry

WWTM (being Weak Write Test Mode): weak write test mode

Load ref.cell: mimotope linear load sram cell

Reference cell: the integrated tracking sram cell of writing

Dummy cell: simulation word line load sram cell

Memory cell:SRAM storage unit

IWRC: integrated writing followed the tracks of reset circuit (comprise writing and follow the tracks of reset circuit and virtual power supply generation circuit)

DWL Driver: simulation word line driver

DWL: simulation word-line signal

Probe: end of probe

Vnbias Generator: a little less than write voltage generator

Control Logic: logic control circuit

CAL_WREND: write to follow the tracks of and finish monitor signal (when being used for test pattern)

TM: test pattern enable signal (TM=1 enters test pattern, otherwise is normal use pattern)

WREND: the tracking end signal is write in inside

WL: word-line signal

TKBL: write the tracking bit line

TKBLB: write the tracking paratope line

V _DD: supply voltage:

Vpbias: variable voltage

V _REF: virtual power supply

Vnbias: a little less than write voltage

1, NMOS pipe

2, PMOS pipe

3, the 2nd PMOS pipe

4, the 3rd PMOS pipe

5, first resistance

6, phase inverter

7, can select resistance circuit

8, the 2nd NMOS pipe

Embodiment:

The present invention is further described below in conjunction with drawings and Examples.

In order to disclose the present invention better, some are known and follow the tracks of irrelevant circuit, logic and structure and do not give detailed description at this with writing.The present invention not merely is only limited to 6 pipe static RAM, and its principle and structure can be applied to 8 pipe or multiport static RAM equally, and these do not break away from claim scope of the present invention.

Fig. 1 is an embodiment who writes the self-timing writing tracking type static random access memory of test function a little less than being integrated with according to the present invention, though this embodiment has used entity stores device framework, but principle of the present invention also can be applied in two arrays or the many array architectures, and these do not break away from claim scope of the present invention.Comprise common memory array (it is made up of a plurality of SRAM storage unit) in this example structure, write tracking row, word line driver array, the input/output circuitry with weak write test mode and integrated simulation write driver able to programme, state control circuit, write and follow the tracks of reset circuit and virtual power supply generation circuit.Wherein write follow the tracks of row comprise by a plurality of write that trace word linear load sram cell forms write the trace word linear array, by a plurality of integrated write follow the tracks of sram cell and write that trace bit linear load sram cell forms write trace bit linear array (integrated writing wherein followed the tracks of the control that sram cell is used to write tracking time, and this is write and follows the tracks of path and not only can be applied to the write time that the common write time controls but also can be used under the weak write test mode state and control).Being arranged in Fig. 1 writes the mimotope linear load sram cell (shown in Fig. 6 (d)) of following the tracks of row and is used for simulating the bit-line load of writing tracing process.Be arranged in Fig. 1 and write follow the tracks of row a plurality of integrated and write and follow the tracks of sram cell (shown in Fig. 6 (c)) and be used for simulating and write usually or the behavior that writes during weak write test mode, wherein integrated writing followed the tracks of writing of sram cell to follow the tracks of bit line TKBL continuous with mimotope linear load sram cell and be connected with the output of integrated simulation write driver able to programme; It is write and follows the tracks of paratope line TKBLB and be connected to write and follow the tracks of reset circuit but it does not link to each other with mimotope linear load sram cell; Its word line is connected to the word line of simulation word line load sram cell (shown in Fig. 6 (b)) and links to each other with the output of simulation word line driver.By top trace word linear array and the bit line array write, write tracking signal and can realize load tracking on word line and the bit line direction.Used a plurality of integrated writing to follow the tracks of sram cell in this embodiment in order to improve the caused variation of whole self-timing writing tracking sequential resisting process deviation.

As shown in Figure 1, common its power supply of memory cell is connected to power supply V _DD, the power supply of simulation word line and bit-line load unit equally also is connected to power supply V _DD, but the integrated power supply of following the tracks of sram cell of writing then is connected to virtual power supply V separately _REFThis virtual power supply V _REFProduce by internal circuit (shown in Fig. 4 b).(non-weak write test mode state, TM=0 at this moment) this virtual power supply V when chip is in common state _REFVoltage can be approximately equal to power supply V _DDVoltage, this moment is integrated writes the behavior of writing that sram cell is used to simulate the common memory cell that does not keep defective of following the tracks of.And when chip is in the state of weak write test mode (this moment TM=1) virtual power supply V _REFVoltage can be less than power supply V _DDVoltage, this moment is integrated to be write and follows the tracks of sram cell and be used to simulate the behavior of writing that has the common memory cell that keeps defective.Be connected to virtual power supply V _REFEnd of probe (Probe) be used for the test that the simulation of weak write test mode calibration process keeps the defect resistance value.

Fig. 2 is arranged in the I/O Circuits with WWTM of Fig. 1 for having the input/output circuitry structural drawing of weak write test mode (WWTM).Wherein 3 PMOS pipes going out of example are as precharge device, and its grid is controlled by corresponding precharging signal; Wherein a plurality of NMOS pipes be the column selection transfer tube (can form usually 2 select 1,4 select 1,8 select 1,16 select 1 or 32 select structure such as 1), be integrated with the signal that the write driver of weak write test mode produces in order to the selectivity transmission.The explanation this patent of attaching most importance to, ignored among this figure some known or with write irrelevant circuit.

Fig. 3 is integrated simulation write driver circuits figure able to programme, be arranged in the Dummy Write Driver of Fig. 1, a little less than being provided with, its inside writes voltage generator No. the 7133319th, United States Patent (USP) (be Vnbias Generator, referring to) and programmable analog write driver.The programmable analog write driver circuits is used to simulate the write driver that is integrated with weak write test mode usually, its inner PMOS pipe M30 source electrode links to each other with power supply, its drain electrode is connected and places to write with the drain electrode of a NMOS pipe M31 to be followed the tracks of on the bit line, its grid is connected with the grid of this NMOS pipe M31, wherein PMOS pipe M30 is used for the pre-charge circuit in the simulation drawing 2, be connected to and write the NMOS pipe M31 that follows the tracks of bit line TKBL and be used for column selection transfer tube (can use identical size) in the simulation drawing 2, source electrode and four sources of above-mentioned this NMOS pipe M31, the NMOS pipe M32～M35 of drain terminal parallel connection connects, this NMOS pipe M32～M35 is used for regulating and writes driving force, the NMOS pipe M35 that writes voltage Vnbias a little less than wherein grid is connected to is used for writing the NMOS pipe a little less than the simulation and (is arranged in the write driver that Fig. 2 is integrated with weak write test mode, write a little less than it and write on the voltage generator a little less than voltage Vnbias then is connected), the write time that other three NMOS pipe M32～M34 with different channel dimensions are used to realize writing usually when following the tracks of is regulated.When three external control signals (being External Settings) changed, NMOS pipe M32～M34 can realize eight kinds of different driving forces of writing.This scalable is write driving force and can be changed and write tracking signal and writing the transmission time of following the tracks of on the bit line, and then can regulate the size that writes pulsewidth usually, realizes the controlled of write time surplus.Use three external control signals as example in this embodiment, in specific implementation, can reduce or increase the number of external control signal.Writing voltage generator when the weak write test mode state a little less than (this moment TM=1) can export a more weak voltage Vnbias (its magnitude of voltage is usually less than supply voltage V _DDVoltage) a little less than integrated simulation write driver able to programme, write NMOS pipe M35 and common write driver, and the grid of other three NMOS pipe M32～M34 is set to ground level by logic control circuit (Control Logic) and closes, and writes transmission a little less than having realized on the bit line TKBL writing to follow the tracks of like this; The output voltage of writing voltage generator when chip is in common state a little less than (TM=0 this moment) can become common supply voltage, and the gate status of other three NMOS pipe M32～M34 is determined by logic control circuit.

Fig. 4 is virtual power supply (V _REF) produce circuit diagram, wherein the 2nd PMOS pipe M41 has stronger driving force, the driving force of PMOS pipe M40 then relatively a little less than.The source of these two PMOS pipes, drain electrode are parallel to power supply V _DDWith virtual power supply V _REFBetween, wherein the grid of PMOS pipe M40 is by the Vpbias signal controlling, and the grid of the 2nd PMOS pipe M41 is then controlled by test pattern enable signal TM.When chip was in the weak write test mode state, the TM signal that is set to high level can be closed the 2nd PMOS pipe M41, and PMOS pipe M40 can export a more weak virtual voltage V under the control of Vpbias simultaneously _REFIn order to offer the integrated tracking sram cell of writing; When chip was in common state, test pattern enable signal TM can be connected to ground level, and at this moment the 2nd PMOS pipe M41 opens and export an approximate supply voltage V _DDVirtual voltage V _REFWhen the weak write test mode state, if the voltage of regulating Vpbias corresponding virtual voltage V so _REFAlso can change thereupon, so just can realize that simulated defect keeps the controllability of resistance.Variable voltage Vpbias can be provided (as Fig. 4 (a) example) by external circuit or input pin, also can be produced (as Fig. 4 (b) example) by internal circuit.

Fig. 4 (b) example the generator of a kind of variable voltage Vpbias, wherein the 3rd PMOS pipe M42 connects with a variable divider resistance circuit, the drain electrode of the one NMOS pipe M43 links to each other with node Vpbias, source electrode is connected to ground level, and the grid of the 3rd PMOS pipe M42 and NMOS pipe M43 is connected to the output of phase inverter jointly, the input signal of this phase inverter is test pattern enable signal TM.Described variable divider resistance circuit is by first resistance R _TWith can select resistance circuit to form, described select resistance circuit by three NMOS pipe M46, M45 and M44 respectively with corresponding resistance R _M, 2R _MAnd 4R _MBe formed in parallel again after being in series.Wherein whether NMOS pipe M44～M46 is used for optionally controlling corresponding resistance and participates in and first resistance R _TDividing potential drop, if for example the grid control signal of NMOS pipe M44 be a ground level, NMOS manages the resistance 4R that M44 can close and be in series with it so _MTo not participate in and first resistance R _TDividing potential drop, if instead the grid control signal of NMOS pipe M44 is a high level, resistance 4R so _MTo participate in and first resistance R _TDividing potential drop.Resistance R _M, 2R _MAnd 4R _MHave different resistance value (for example a times, twice and four times of resistances), can realize the output of eight kinds of different voltage Vpbias by changing this variable resistor bleeder circuit of three external control signals like this.When chip is in the weak write test mode state (signal TM=1), the output low level of first phase inverter can be opened the 3rd PMOS pipe M42 and be closed NMOS pipe M43, can select resistance circuit work this moment, can realize exporting different voltage by regulating external control signal variable voltage Vpbias; When chip is in common state (signal TM=0), the output high level of phase inverter can be closed the 3rd PMOS pipe M42 and be opened NMOS pipe M43, can select resistance circuit not work this moment, and variable voltage Vpbias is connected to low level by NMOS pipe M43.Used three external control signals as example in this embodiment, can reduce or increase the number and the corresponding circuit of external control signal in specific implementation, these do not break away from the claim scope of this patent.

Fig. 5 is for writing the tracking reset circuit in the present embodiment, WREND is that the tracking end signal is write in inside, when becoming low level by high level, WREND means a certain tracking end of writing, CAL_WREND finishes monitor signal for writing to follow the tracks of, be mainly used under the weak write test mode state a little less than write calibration process and a little less than write the monitoring in when test, NMOS pipe M50 is used to write the integrated state of following the tracks of after finishing of following the tracks of the sram cell circuit of writing and resets.When original state, signal TKBLB is that low level, simulation word-line signal DWL also are in closed condition for low level, NMOS pipe M50; When writing state, after the programmable analog write driver is write upset with the integrated state of writing the tracking sram cell, write tracking paratope line signal TKBLB and can become high level, signal WREND can become low level subsequently, treat that simulation word-line signal in WREND signal reset mode control circuit (Control Circuitry) back can become low level thereupon, two inputs this moment all are that low level rejection gate can be exported high level signal to the grid of NMOS pipe M50 and with its unlatching, the NMOS pipe M50 that opens can make to write and follow the tracks of that paratope line TKBLB becomes low level and then integrated the writing that reset followed the tracks of sram cell to initial state, for write next time follow the tracks of ready.When chip is in the weak write test mode state (signal TM=1), cmos transmission gate can open and with the state transfer of inner WREND signal to CAL_WREND, just can know the state of internal signal WREND by the state of observing the CAL_WREND signal, because the method need not to read integrated writing and writes success a little less than the state of following the tracks of sram cell just can know whether, so this method is write the calibration process of test a little less than having simplified.

Fig. 6 is four kinds of static random access memory cell circuit diagrams, and wherein Fig. 6 (a) is standard 6 pipe sram cells (being Memory Cell); Fig. 6 (b) example simulation word line load sram cell (being Dummy Cell); Fig. 6 (c) follows the tracks of sram cell (being Reference Cell) for integrated writing; Fig. 6 (d) is a mimotope linear load sram cell (being Load Ref.Cell).Simulation word line load sram cell is used for simulating writing follows the tracks of the load of path on word-line direction, and its word line is connected on the simulation word-line signal DWL, and its bit line and paratope line are then unsettled, and a plurality of simulation word line load sram cells compositions are write the trace word linear array.Mimotope linear load sram cell then is used for simulating writing follows the tracks of the load of path on bit line direction, and its word line is connected to ground level, and its bit line with write tracking bit line TKBL and be connected, its paratope line is connected to power supply V _DD, a plurality of mimotope linear load sram cells and a plurality of integrated writing are followed the tracks of sram cell and have been formed and write the trace bit linear array.The integrated word line of following the tracks of sram cell of writing links to each other with simulation word line DWL, its bit line with write follow the tracks of that bit line signal TKBL connects, its paratope line and writing follows the tracks of that paratope line signal TKBLB links to each other and the storage inside node corresponding with it is connected (being about to and leakage, the source shorted of writing the 2nd NMOS pipe that tracking paratope line (TKBLB) links to each other), its power supply is connected to independently virtual power supply V _REFOn.The integrated tracking paratope line TKBLB storage inside node corresponding with it of writing of following the tracks of sram cell of writing is connected, thereby is to avoid high level signal can produce a threshold voltage and reduce the voltage attenuation effect of being brought through the NMOS pipe for its output signal realizes full swing.

Introducing integrated self-timing writing tracking circuit of the present invention is below writing under the state and the course of work under the weak write test mode state usually.

When writing state usually (non-weak write test mode state), this moment TM=0, virtual power supply V _REFAnd a little less than write voltage Vnbias voltage be approximately equal to power supply V _DDVoltage, ifs circuit is in its inner word line of stand-by operation state and the simulation word line can be in low level, integrated writing followed the tracks of writing of sram cell and followed the tracks of bit line TKBL and be precharged to high level, write and follow the tracks of paratope line TKBLB and then be in low level, inside is write and followed the tracks of end signal WREND is high level, and at this moment state control circuit waits for that external clock receives new order.When external timing signal sampling write command, internal clock signal can be enabled to high level, and decoded subsequently word line (Word Line) and the simulation word line thereof that comes out is activated, and corresponding selected column selection transfer tube is opened; The simulation write driver can drag down to write follows the tracks of bit line TKBL, subsequently " 0 " be written into integrated write to follow the tracks of sram cell and raise to write follow the tracks of paratope line TKBLB to high level, meanwhile common write driver circuit can drive corresponding bit line or paratope line to low level, and then new numerical value is write sram cell.Because write following principle and common to write principle identical, therefore when inner when writing tracking end signal WREND and being pulled to low level common sram cell also finished it and write new numerical value.After WREND is pulled to low level, this signal can feed back to state control circuit and impel its internal clock signal to low level, corresponding subsequently word line can be pulled to low level, and common column selection transfer tube is closed and bit line and paratope line are precharged to high level; Meanwhile simulate write driver and can then can pulled down to low level to high level, simulation word line by preliminary filling autotelegraph trace bit line TKBL, can with write follow the tracks of paratope line TKBLB be discharged to low level and then impel integrated write follow the tracks of sram cell be reset to initial state by writing the NMOS pipe M50 that follows the tracks of in the reset circuit this moment, and inside is write tracking signal WREDN and can be become high level subsequently.So far once common self-timing writing tracking cycle finishes.

When the weak write test mode state, this moment TM=1, a little less than write voltage generator output Vnbias through a little less than write the selected a certain voltage of detection calibration, be used to produce virtual voltage V _REFVpbias voltage through a little less than write the also selected a certain voltage of detection calibration, use these light current and be depressed into and write test a little less than relevant circuit promptly can begin to carry out.As under the weak write test mode state write tracing process and usually sram cell a little less than identical when writing process and writing state usually, be not described in detail at this.

Introduce with regard to weak write test mode calibration flow process of the present invention at last.

Write test a little less than carrying out before, the setting (as the WWTM Settings in Fig. 1 and 3) of writing voltage generator a little less than needing to regulate produces suitable weak write driving voltage, and this process is commonly called the weak write test mode calibration.The integrated supply voltage of writing the tracking sram cell that the present invention proposes is virtual power supply V _REF, can obtain different V by the setting of Vpbias magnitude of voltage or its correspondence among adjusting Fig. 4 _REFMagnitude of voltage, the therefore integrated V that follows the tracks of sram cell that writes _REFEnd and supply voltage V _DDBetween the connection of this similar resistance behavior can be used for simulating and have a common memory cell that keeps defective.The corresponding simulating defective keeps resistance value directly to measure by test lead Probe, and this direct test process can be simplified testing process, reduce testing cost.Weak write test mode is calibrated flow process as shown in Figure 7, and detailed process is described in detail as follows (TM=1 in all processes):

(1) at first set a defective and keep resistance value R, this is by the test target decision of weak write test mode.

(2) choose a Vpbias voltage or its corresponding setting then, it is promptly passable only need to choose a certain Vpbias voltage if Vpbias provides (shown in Fig. 4 (a)) by external circuit or input pin, if Vpbias produces corresponding Vpbias voltage by the external control signal that internal circuit generation (shown in Fig. 4 (b)) needs to choose a certain setting so.

(3) keep resistance value R ' by end of probe Probe measure analog defective.

(4) then compare test as a result R ' with set whether approximately equal of resistance value R, if approximately equal then can enter (5) step of calibration flow process; If approximately equal was not then returned for (2) step and is chosen new Vpbias voltage or its corresponding setting.

(5) Vpbias voltage or its correspondence of preserving for (2) this moment in step set.

(6) secondly choose the setting (being WWTM Settings) of writing voltage Vnbias a little less than in the of one, cause good storage unit to be filtered out mistakenly too by force for fear of the Vnbias voltage of choosing, when choosing this setting for the first time, should begin to choose from the setting of the most weak Vnbias voltage of correspondence.

(8) observation is write and follow the tracks of to be finished monitor signal CAL_WREND and whether become low level by high level then, if this signal becomes (9) step that low level then can enter the calibration flow process by high level; To write voltage a little less than then representing too low if this signal is still for high level, and the calibration requirements of process was returned for (6) step and chosen a setting of writing voltage Vnbias a little less than new.

It is emphasized that: above only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, every foundation technical spirit of the present invention all still belongs in the scope of technical solution of the present invention any simple modification, equivalent variations and modification that above embodiment did.

Claims

1. an integrated with weak is write the self-timing writing tracking type static random access memory of test function, is provided with memory array, has input/output circuitry and the word line driver array and the state control circuit of weak write test mode, it is characterized in that: also be provided with:

2. a kind of integrated with weak according to claim 1 is write the self-timing writing tracking type static random access memory of test function, it is characterized in that: described integrated simulation write driver able to programme is provided with PMOS pipe, described PMOS pipe source electrode links to each other with power supply, its drain electrode is connected with the drain electrode of a NMOS pipe and places to write to be followed the tracks of on the bit line, its grid is connected with the grid of this NMOS pipe, and the source electrode of this NMOS pipe links to each other with a plurality of drain electrodes with NMOS pipe of different channel dimensions, and described a plurality of source electrodes with NMOS pipe of different channel dimensions are connected to ground jointly, the grid of writing other several NMOS pipes of voltage a little less than the grid of one of them NMOS pipe is connected to then is connected with logic controller.

3. a kind of integrated with weak according to claim 2 is write the self-timing writing tracking type static random access memory of test function, it is characterized in that: write a little less than described and write on the voltage generator a little less than voltage is connected.

4. a kind of integrated with weak according to claim 1 is write the self-timing writing tracking type static random access memory of test function, it is characterized in that: described virtual power supply produces circuit by virtual power supply and provides, described virtual power supply produce circuit by a PMOS manage, the 2nd PMOS pipe source, draining is parallel between supply voltage and the virtual power supply and constitutes, the grid of a described PMOS pipe is connected with variable voltage signal, and the grid of described the 2nd PMOS pipe is connected with the test pattern enable signal.

5. a kind of integrated with weak according to claim 4 is write the self-timing writing tracking type static random access memory of test function, it is characterized in that: described variable voltage signal is provided by external circuit or input pin.

6. a kind of integrated with weak according to claim 4 is write the self-timing writing tracking type static random access memory of test function, it is characterized in that: described variable voltage signal is provided by the Vpbias generator, described Vpbias generator comprises: one can select to be connected in series first resistance again after the parallel connection of resistance circuit and NMOS pipe, describedly select resistance circuit to connect respectively to be formed in parallel again behind the corresponding resistance by three NMOS pipe, the other end of described first resistance is connected with the drain electrode of the 3rd PMOS pipe, the source electrode of described the 3rd PMOS pipe connects supply voltage, the grid of a grid and a NMOS pipe is connected on the output terminal of the phase inverter of being controlled by the test pattern enable signal jointly, the described source electrode of the NMOS pipe in the resistance circuit and the source ground of a NMOS pipe selected.

7. a kind of integrated with weak according to claim 1 is write the self-timing writing tracking type static random access memory of test function, it is characterized in that: the described integrated tracking sram cell of writing is formed by standard 6 pipe sram cells modifications, and it writes leakage, the source shorted of following the tracks of the 2nd NMOS pipe on the paratope line.

8. a kind of integrated with weak according to claim 1 is write the self-timing writing tracking type static random access memory of test function, it is characterized in that: described write to follow the tracks of be provided with one in the reset circuit and write to follow the tracks of and finish monitor signal end and reset circuit, described writing followed the tracks of end monitor signal end when the test pattern enable signal is " 1 ", receives inside and writes tracking end signal and synchronous output.

9. an integrated with weak is write the calibration steps of the self-timing writing tracking type static random access memory of test function, and it is characterized in that: described calibration steps step is as follows:

(3) keep resistance value R ' by end of probe measure analog defective.