CN116013395A

CN116013395A - Test method and test circuit

Info

Publication number: CN116013395A
Application number: CN202310311842.8A
Authority: CN
Inventors: 杨杰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2023-04-25
Anticipated expiration: 2043-03-28
Also published as: CN116013395B

Abstract

The present disclosure provides a test method and a test circuit, the test method including: providing a memory, wherein the memory has a first sensing margin in a first test mode and a second sensing margin in a second test mode, the test time of the first test mode is smaller than that of the second test mode, and the first sensing margin is larger than the second sensing margin; determining a lining bias voltage adjustment value of a sense amplifier of the memory, wherein after the lining bias voltage of the sense amplifier is adjusted by the lining bias voltage adjustment value, the memory can have a third sensing margin in a first test mode, and the difference value between the third sensing margin and the second sensing margin is smaller than the difference value between the first sensing margin and the second sensing margin; and adjusting the lining bias voltage of the sense amplifier according to the lining bias voltage adjusting value, and testing the whole memory by adopting a first test mode. The embodiment of the disclosure is at least beneficial to improving the covering capability of the test process of the memory to the exception.

Description

Test method and test circuit

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a testing method and a testing circuit.

Background

Memory chips are an important component of most electronic products. In order to test the quality of the memory and ensure the service performance of the memory chip after being on line, the memory chip often needs to be tested before formally leaving the factory, so that a product with lower yield is found.

Along with the precision and the miniaturization of electronic products, the complexity of various memory chips is higher and higher, corresponding failure modes are more and more, and the method for testing the memory chips completely, efficiently and accurately has very important significance for ensuring the quality of the memory chips.

Disclosure of Invention

The disclosure provides a testing method and a testing circuit, which are at least beneficial to improving the covering capability of a testing process of a memory to an abnormality.

An aspect of an embodiment of the present disclosure provides a test method, including: providing a memory, wherein the memory has a first sensing margin in a first test mode and a second sensing margin in a second test mode, the test time of the first test mode is smaller than that of the second test mode, and the first sensing margin is larger than the second sensing margin; determining a lining bias voltage adjustment value of a sense amplifier of the memory, wherein after the lining bias voltage of the sense amplifier is adjusted by the lining bias voltage adjustment value, the memory can have a third sensing margin in a first test mode, and the difference value between the third sensing margin and the second sensing margin is smaller than the difference value between the first sensing margin and the second sensing margin; and adjusting the lining bias voltage of the sense amplifier according to the lining bias voltage adjusting value, and testing the whole memory by adopting a first test mode.

In some embodiments, the sense amplifier includes a first sense NMOS transistor, a second sense NMOS transistor, a first sense PMOS transistor, and a second sense PMOS transistor, a first pole of the first sense NMOS transistor, a first pole of the first sense PMOS transistor, a gate of the second sense NMOS transistor, and a gate of the second sense PMOS transistor are all coupled to a bit line corresponding to a memory cell to be tested in the memory, a first pole of the second sense NMOS transistor, a first pole of the second sense PMOS transistor, a gate of the first sense NMOS transistor, and a gate of the first sense PMOS transistor are all coupled to complementary bit lines corresponding to the bit line, a second pole of the first sense NMOS transistor and a second pole of the second sense NMOS transistor are coupled, and a second pole of the first sense PMOS transistor and a second pole of the second sense PMOS transistor are coupled; adjusting the liner bias voltage of the sense amplifier according to the liner bias voltage adjustment value includes: and adjusting the lining bias voltage of the second sensing NMOS tube of the sensing amplifier according to the lining bias voltage adjusting value.

In some embodiments, the memory includes a plurality of sets of bit lines, each set of bit lines including N bit lines arranged in succession, N being an integer greater than 1; the first test mode includes: writing first test data into memory cells corresponding to at least one group of bit lines, wherein the first test data are all data representing high level; the second test mode includes: and writing second test data into the memory cells corresponding to at least one group of bit lines, wherein one bit of data in the second test data is data representing high level, and the rest bit of data is data representing low level.

In some embodiments, determining the liner bias voltage adjustment value of the sense amplifier of the memory includes: providing a test circuit, the test circuit comprising: a first signal processing circuit including a first transistor, a gate of the first transistor being connected as an input terminal of the first signal processing circuit to a target bit line of the memory, the first signal processing circuit outputting a first signal from an output terminal based on a potential of the target bit line in a first test mode; the second signal processing circuit comprises a second transistor, the grid electrode of the second transistor is used as the input end of the second signal processing circuit to be connected with the reference bit line of the memory, and the second signal processing circuit outputs a second signal from the output end based on the potential of the reference bit line in a second test mode; the comparison circuit is respectively connected with the output end of the first signal processing circuit and the output end of the second signal processing circuit, and outputs a first potential from the output end based on the phase difference of the first signal and the second signal, wherein the magnitude of the first potential depends on the magnitude of the phase difference; the bias circuit is connected with the output end of the comparison circuit, and adjusts the lining bias voltage of the first transistor based on the first potential until the first potential is smaller than a preset value; and acquiring the lining bias voltage of the first transistor when the first potential is smaller than a preset value, and determining a lining bias voltage adjustment value according to the lining bias voltage of the first transistor.

In some embodiments, the comparison circuit includes a phase detector.

In some embodiments, the bias circuit comprises a window comparator array and a trimming circuit, wherein the window comparator array comprises a plurality of window comparators connected in parallel, and the window comparators are connected with the trimming circuit and used for controlling the trimming circuit to output corresponding voltages.

In some embodiments, in the test circuit, the first transistor and the second transistor are each identical to a second sense NMOS transistor of a sense amplifier of the memory.

In some embodiments, in the test circuit, the first signal processing circuit is a ring oscillator, the first signal processing circuit further includes a first inverter group, an input terminal of the first inverter group is connected to a first pole of the first transistor, and an output terminal of the first inverter group is connected to a second pole of the first transistor; the second signal processing circuit is a ring oscillator, and further comprises a second inverter group, wherein the input end of the second inverter group is connected with the first pole of the second transistor, and the output end of the second inverter group is connected with the second pole of the second transistor.

In some embodiments, the first inverter group includes an odd number of first inverters in series, and the second inverter group includes an odd number of second inverters in series, the first inverters being the same as the second inverters, the number of first inverters in the first inverter group being the same as the number of second inverters in the second inverter group.

In some embodiments, the number of first inverters in the first inverter group is greater than 20 and less than 50.

In some embodiments, the first inverter includes a first PMOS transistor and a first NMOS transistor, the second inverter includes a second PMOS transistor and a second NMOS transistor, a source of the first PMOS transistor and a source of the second PMOS transistor are both connected to a same power supply voltage, and a source of the first NMOS transistor and a source of the second NMOS transistor are both connected to a same ground voltage.

In some embodiments, obtaining the liner bias voltage of the first transistor when the first potential is less than the preset value comprises: setting a reference bit line and a target bit line, and connecting the reference bit line and the target bit line with a test circuit; setting the reference bit line and the target bit line includes: selecting any two groups of bit lines which are independent of each other from the multiple groups of bit lines as a first group of bit lines and a second group of bit lines, writing first test data into memory cells corresponding to the first group of bit lines, and writing second test data into memory cells corresponding to the second group of bit lines, wherein data representing high level is written into memory cells corresponding to the nth bit line of the second group of bit lines, the nth bit line of the second group of bit lines is used as a reference bit line, and the nth bit line of the first group of bit lines is used as a target bit line.

In some embodiments, N is an even number, N is N/2 or N is N/2+1.

In some embodiments, N is 8 and N is 4 or 5.

Another aspect of the disclosed embodiments provides a test circuit comprising: a first signal processing circuit including a first transistor, a gate of the first transistor being connected as an input terminal of the first signal processing circuit to a target bit line of the memory, the first signal processing circuit outputting a first signal from an output terminal based on a potential of the target bit line in a first test mode; the second signal processing circuit comprises a second transistor, the grid electrode of the second transistor is used as the input end of the second signal processing circuit to be connected with the reference bit line of the memory, and the second signal processing circuit outputs a second signal from the output end based on the potential of the reference bit line in a second test mode; the comparison circuit is respectively connected with the output end of the first signal processing circuit and the output end of the second signal processing circuit, and outputs a first potential from the output end based on the phase difference of the first signal and the second signal, wherein the magnitude of the first potential depends on the magnitude of the phase difference; and the bias circuit is connected with the output end of the comparison circuit and adjusts the lining bias voltage of the first transistor based on the first potential until the first potential is smaller than a preset value.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages: the test time of the memory in the first test mode is shorter than that of the memory in the second test mode, but because the data written in the first test mode and the data written in the second test mode are different, the coupling interference of the bit lines in the first test mode and the coupling interference of the bit lines in the corresponding positions in the second test mode are different, the coupling interference is different, so that the sensing margin of the memory in the first test mode is larger than that of the memory in the second test mode, namely, the first sensing margin is larger than the second sensing margin, and the memory possibly leaks to grasp the memory cells with serious leakage phenomenon when the memory cells with serious leakage phenomenon are tested in the first test mode, namely, the first test mode cannot accurately test abnormality, but the memory has smaller second sensing margin in the second test mode, and has better abnormality coverage capability in the second test mode. According to the testing method, the lining bias voltage of the sensing amplifier is further adjusted by determining the lining bias voltage adjusting value of the sensing amplifier, so that the performance of the sensing amplifier in the first testing mode is changed, the sensing margin of the memory in the first testing mode is closer to the second sensing margin with excellent normal covering capacity, the abnormal covering capacity of the first testing mode is improved, the memory is tested by the first testing mode with shorter testing time, and the testing efficiency of the memory is effectively improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic diagram of a partial circuit structure of a memory according to an embodiment of the disclosure;

FIG. 2 is a schematic layout diagram of a portion of bit lines of a memory according to an embodiment of the disclosure;

FIG. 3 is a graph illustrating voltage relationships on bit lines in different test modes according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a test circuit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another test circuit provided by an embodiment of the present disclosure;

FIG. 6 is a timing diagram of a first signal and a second signal according to an embodiment of the disclosure;

Fig. 7 is a schematic circuit diagram of a window comparator according to an embodiment of the disclosure;

FIG. 8 is a schematic diagram of a voltage transfer characteristic of a window comparator according to an embodiment of the disclosure;

fig. 9 is a schematic circuit diagram of a bias circuit according to an embodiment of the disclosure.

Detailed Description

The background technology can know how to completely, efficiently and accurately test the memory chip, and has very important significance for ensuring the quality of the memory chip.

The embodiment of the disclosure provides a testing method and a testing circuit, wherein the testing method adjusts the lining bias voltage of a sense amplifier by determining the lining bias voltage adjusting value of the sense amplifier so as to change the performance of the sense amplifier in a first testing mode, so that the sensing margin of a memory in the first testing mode is closer to a second sensing margin with excellent normal covering capacity, thereby being beneficial to improving the abnormal covering capacity of the first testing mode, testing the memory by using the first testing mode with shorter testing time and effectively improving the testing efficiency of the memory.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the embodiments of the present disclosure. However, the technical solutions claimed in the embodiments of the present disclosure can be implemented without these technical details and based on various changes and modifications of the following embodiments.

Fig. 1 is a schematic diagram of a partial circuit structure of a memory according to an embodiment of the disclosure; FIG. 2 is a schematic layout diagram of a portion of bit lines of a memory according to an embodiment of the disclosure; FIG. 3 is a graph illustrating voltage relationships on bit lines in different test modes according to an embodiment of the present disclosure; FIG. 4 is a schematic diagram of a test circuit according to an embodiment of the present disclosure; FIG. 5 is a schematic diagram of another test circuit provided by an embodiment of the present disclosure; FIG. 6 is a timing diagram of a first signal and a second signal according to an embodiment of the disclosure; fig. 7 is a schematic circuit diagram of a window comparator according to an embodiment of the disclosure; FIG. 8 is a schematic diagram of a voltage transfer characteristic of a window comparator according to an embodiment of the disclosure; fig. 9 is a schematic circuit diagram of a bias circuit according to an embodiment of the disclosure.

The testing method provided by the embodiment of the disclosure comprises the following steps: providing a memory, wherein the memory has a first sensing margin in a first test mode and a second sensing margin in a second test mode, the test time of the first test mode is smaller than that of the second test mode, and the first sensing margin is larger than the second sensing margin. The test method further comprises the following steps: and determining a lining bias voltage adjustment value of a sense amplifier of the memory, wherein after the lining bias voltage of the sense amplifier is adjusted by the lining bias voltage adjustment value, the memory can have a third sensing margin in a first test mode, and the difference value between the third sensing margin and the second sensing margin is smaller than the difference value between the first sensing margin and the second sensing margin. After the lining bias voltage adjustment value is determined, the testing method comprises the following steps: and adjusting the lining bias voltage of the sense amplifier according to the lining bias voltage adjusting value, and testing the whole memory by adopting a first test mode.

It should be noted that, because the data written in the first test mode is different from the data written in the second test mode, the bit lines in the first test mode are different from the bit lines in the corresponding positions in the second test mode, the coupling interference is different, the sensing margin of the memory in the first test mode is greater than the sensing margin of the memory in the second test mode, that is, the first sensing margin is greater than the second sensing margin, so that the memory may not grasp the memory cells with serious leakage phenomenon when the memory cells with serious leakage phenomenon are tested in the first test mode, that is, the first test mode may not accurately test the abnormality, but the memory has smaller second sensing margin in the second test mode, and the memory has better abnormality coverage capability in the second test mode. According to the testing method, the lining bias voltage of the sensing amplifier is further adjusted by determining the lining bias voltage adjusting value of the sensing amplifier, so that the performance of the sensing amplifier in the first testing mode is changed, the sensing margin of the memory in the first testing mode is closer to the second sensing margin with excellent normal covering capacity, the abnormal covering capacity of the first testing mode is improved, the memory is tested by the first testing mode with shorter testing time, and the testing efficiency of the memory is effectively improved.

For example, referring to fig. 1 and 2, the memory includes a plurality of memory cells, which may be a 1T1C (1 transistor&1 capacitor) structure composed of a cell transistor 101 and a cell capacitor C, and further, the memory may further include a Sense Amplifier (Sense Amplifier) 100, an equalizing circuit (Equalization circuit, not shown), an input/output circuit (not shown), and the like.

One of the source and the drain of the cell transistor 101 is connected to the cell capacitor C, the other is connected to the bit line BL, and the word line WL is connected to the gate of the cell transistor 101, for selectively turning on the corresponding cell transistor 101, so that the cell capacitor C is connected to the bit line BL, thereby writing an electrical signal in the bit line BL into the cell capacitor C, or reading an electrical signal in the cell capacitor C into the bit line BL.

The sense amplifier 100 is connected between the bit line BL and the complementary bit line BLB, and the sense amplifier 100 is configured to receive and amplify a voltage difference between the bit line BL and the complementary bit line BLB based on the first power signal PCS and the second power signal NCS. For example, the sense amplifier 100 includes: the first sensing NMOS transistor 102, the second sensing NMOS transistor 103, the first sensing PMOS transistor 104 and the second sensing PMOS transistor 105, wherein the first pole of the first sensing NMOS transistor 102, the first pole of the first sensing PMOS transistor 104, the gate of the second sensing NMOS transistor 103 and the gate of the second sensing PMOS transistor 105 are all coupled with the bit line BL corresponding to the memory cell to be tested in the memory, the first pole of the second sensing NMOS transistor 103, the first pole of the second sensing PMOS transistor 105, the gate of the first sensing NMOS transistor 102 and the gate of the first sensing PMOS transistor 104 are all coupled with the complementary bit line BLB corresponding to the bit line BL, the second pole of the first sensing NMOS transistor 102 and the second pole of the second sensing NMOS transistor 103 are all coupled, and the second pole of the first sensing NMOS transistor 104 and the second pole of the second sensing PMOS transistor 105 are all coupled. The sense amplifier 100 further includes a transfer transistor for transferring a power signal, the transfer transistor including a PMOS transistor 106 for transferring a high level signal and an NMOS transistor 107 for transferring a low level signal. Adjusting the liner bias voltage of the sense amplifier 100 according to the liner bias voltage adjustment value includes: the liner bias voltage of the second sense NMOS 103 of the sense amplifier 100 is adjusted according to the liner bias voltage adjustment value.

The read operation of the memory includes a precharge phase, a charge sharing phase, a sense amplifying phase, and a reset phase. Referring to fig. 1, a reading operation will be described below taking reading of "1" from the cell capacitor C as an example.

Precharge (Precharge) phase: precharging is performed to stabilize the voltages on bit line BL and BLB on the complementary bit line at Vref, where vref=vdd/2.

Charge sharing (Access) phase: after the voltages on the bit line BL and the complementary bit line BLB stabilize at Vref, the gate of the cell transistor 101 is controlled by the word line WL, turning on the cell transistor 101, the positive charge stored in the cell capacitor C flows to the bit line BL, and the voltage on the bit line BL is pulled up to Vref+ [ delta ] V, where [ delta ] V is the voltage increment on the bit line BL.

Sense amplification (Sense) stage: since the voltage of the bit line BL is pulled up to Vref+DeltaV, the voltage of the complementary bit line BLB is still Vref, the second sensing NMOS transistor 103 is more conductive than the first sensing NMOS transistor 102, the first sensing PMOS transistor 104 is more conductive than the second sensing PMOS transistor 105, and the PMOS transistor 106 and the NMOS transistor 107 are turned on. The voltage value of the node PCS is set to a logic 1 voltage, and the voltage value of the node NCS is set to a logic 0 voltage. Since the second sense NMOS transistor 103 is more conductive than the first sense NMOS transistor 102, the voltage on the complementary bit line BLB is pulled to logic 0 by node NCS faster, and similarly, the voltage on the bit line BL is pulled to logic 1 by node PCS faster. Then, the first sensing PMOS transistor 104 and the second sensing NMOS transistor 103 enter the on state, and the second sensing PMOS transistor 105 and the first sensing NMOS transistor 102 enter the off state. The voltages on bit line BL and complementary bit line BLB both enter a steady state, correctly presenting the data stored by cell capacitor C.

Recovery (Restore) phase: after the sense amplifying stage is completed, the bit line BL is at a stable logic 1 voltage, and at this time, the bit line BL charges the cell capacitor C, so that the charge of the cell capacitor C is restored to a state before the read operation. Finally, the column select signal CSL turns on the input/output transistors, reading out the data on the bit line BL.

The plurality of bit lines in the memory are arranged in series, and in some embodiments the memory includes a plurality of sets of bit lines, each set of bit lines including N bit lines arranged in series, N being an integer greater than 1. The number of bit lines in a group of bit lines is the number of bit lines for which test data writing is performed at one time. In some embodiments, N is an even number, e.g., N is 8. Referring to fig. 2, taking a group of 8 bit lines (BL 0, BL1, BL2, BL3, BL4, BL5, BL6, and BL 7) arranged in succession as an example, the 8 bit lines share at least one word line WL, and corresponding memory cells are disposed at the connection nodes of the word lines WL and the bit lines.

The first test mode includes: first test data is written to memory cells corresponding to at least one set of bit lines, wherein the first test data are all data representing a high level (e.g., logic 1). For example, taking the plurality of bit lines as a group of bit lines as shown in fig. 2 as an example, the memory is tested in the first test mode. Referring to fig. 2, data representing a high level is written to each of BL0, BL1, BL2, BL3, BL4, BL5, BL6 and BL7, for example, after a charge sharing phase, if the coupling interference effect of adjacent bit lines is not considered, the potential of 8 bit lines is vref++Δv1, where Δv1 is the voltage increment on the bit lines from the precharge phase to the charge sharing phase. In the case of an abnormality, taking a case that a serious leakage phenomenon occurs in a memory cell corresponding to BL3 as an example, in principle, the potential of BL3 is smaller than a sensing threshold vref+Δv (Δv < <Δv1), and data read out from BL3 is data representing a low level, so that the occurrence of an abnormality in the memory cell corresponding to BL3 can be detected; however, under the condition that the potential of the adjacent bit line is higher than the potential of the BL3, the potential of the BL3 may be pulled up to be higher than the sensing threshold vref+Δv due to the effect of the coupling interference, that is, the potential of the BL3 may still drive the second sensing NMOS 103 to be turned on, then the voltage of the BL3 may still be stabilized at logic 1 through the sense amplifying stage, and the data read from the BL3 is still data representing a high level, so that the abnormality of the memory cell corresponding to the BL3 cannot be detected in the first test mode.

The second test mode includes: and writing second test data into the memory cells corresponding to at least one group of bit lines, wherein one bit of data in the second test data is data representing a high level (for example, logic 1), and the rest bit of data is data representing a low level (for example, logic 0). For example, taking the plurality of bit lines as a group of bit lines as shown in fig. 2 as an example, the memory is tested in the second test mode. Referring to fig. 2, data representing a high level is written to one bit line of BL0, BL1, BL2, BL3, BL4, BL5, BL6, and BL7, and data representing a low level is written to the remaining bit lines, and in order to correspond to the aforementioned first test mode, data representing a high level is written to BL 3. For example, after the charge sharing stage, if the coupling interference effect of the adjacent bit lines is not considered, the potential theory of BL3 is vref+Δv1 under normal conditions. Referring to fig. 2 and 3, if the coupling interference of adjacent bit lines is considered, the actual potential of BL3 may be vref+Δv2 where Δv1 > - Δv2 and Δv2 > - Δv2 in the case where the potential of adjacent bit lines is lower than the potential of BL 3. Under abnormal conditions, taking the case that a serious leakage phenomenon occurs in a memory cell corresponding to BL3 as an example, under the condition that the potential of an adjacent bit line is lower than that of BL3, the potential of BL3 is easier to be smaller than a sensing threshold Vref+ [ delta ] V due to the effect of coupling interference, so that the memory cell corresponding to BL3 can be more easily detected, namely the memory cell corresponding to BL3 is more easily detected under a second test mode.

From the above analysis, the memory has a relatively large first sensing margin in the first test mode and a relatively small second sensing margin in the second test mode.

It should be noted that, the first data writing in the first test mode is writing data representing a high level into each bit line, and the abnormality of the memory cells corresponding to the plurality of bit lines can be judged by reading the data once; the first test mode is to write data representing high level into one bit line, write data representing low level into the other bit lines, and if the plurality of bit lines are tested, write data representing high level and read data into each bit line once, taking the plurality of bit lines shown in fig. 2 as a group of bit lines as an example, if the plurality of bit lines are tested, the second test mode is to write data into 8 times and read data from 8 times, and the first test mode is to write data into 8 bit lines once and read data from one time. Therefore, the test time of the first test mode is less than the test time of the second test mode.

In summary, in order to save test time and improve test efficiency, the first test mode may be used to test the memory, but the first sensing margin of the memory in the first test mode has poor capability of covering the abnormality. In the sense amplifier, the bias voltage of the sense NMOS transistor with the gate connected to the bit line BL, that is, the bias voltage of the second sense NMOS transistor 103 shown in fig. 1, referring to fig. 1, the second sense NMOS transistor 103 is turned on by increasing the bias voltage of the second sense NMOS transistor 103 to increase the threshold voltage of the second sense NMOS transistor 103, so that the voltage on the bit line BL is sufficiently large after the charge sharing stage, and if the voltage on the bit line BL is small, the bit line BL cannot be pulled to the logic 1 potential, so that the read data is abnormal, that is, the leakage phenomenon is detected. After the lining bias voltage of the second sensing NMOS tube 103 of the sensing amplifier is adjusted, the sensing margin of the memory in the first test mode is reduced to a third sensing margin, the third sensing margin is smaller than the first sensing margin, and the third sensing margin is closer to the second sensing margin with higher abnormal coverage capacity.

In some embodiments, determining the liner bias voltage adjustment value of the sense amplifier of the memory includes: a test circuit is provided, and a liner bias voltage adjustment value is determined using the test circuit. In some embodiments, prior to determining the liner bias voltage adjustment value using the test circuit, further comprises: setting the reference bit line and the target bit line and connecting the reference bit line and the target bit line to the test circuit, for example, includes: selecting any two groups of bit lines which are independent of each other from the multiple groups of bit lines as a first group of bit lines and a second group of bit lines, writing first test data into memory cells corresponding to the first group of bit lines, and writing second test data into memory cells corresponding to the second group of bit lines, wherein data representing high level is written into memory cells corresponding to the nth bit line of the second group of bit lines, the nth bit line of the second group of bit lines is used as a reference bit line, and the nth bit line of the first group of bit lines is used as a target bit line. That is, if the memory cell corresponding to the 2 nd bit line in the second group of bit lines writes data indicating a high level, the 2 nd bit line in the second group of bit lines is used as the reference bit line, and the 2 nd bit line in the first group of bit lines is used as the target bit line, and since the first test mode is that all the data indicating a high level is written, the target bit line is also written with the data indicating a high level. Bit lines at the same positions in two different groups of bit lines are selected to be respectively used as a target bit line and a reference bit line, so that consistency of the target bit line and the reference bit line is guaranteed.

In some embodiments, N is an even number, N is N/2 or N is N/2+1. For coupling interference in the second test mode, the bit line located in the middle position of the group of bit lines may be subjected to the largest coupling interference, so that the bit line located in the middle position of the group of bit lines is selected as the target bit line, which is favorable for acquiring more effective lining bias voltage adjustment values by utilizing the reference bit line and the target bit line, and further effective adjustment of the sensing margin of the memory is realized. It is understood that in other embodiments, N is an odd number and N is (n+1)/2. In some embodiments, N may be 8, and N may be 4 or 5.

Setting a reference bit line and a target bit line, connecting the reference bit line and the target bit line with a test circuit, and determining a lining bias voltage adjusting value by using the test circuit. For example, referring to fig. 4 and 5, the test circuit includes: a first signal processing circuit 200 including a first transistor 201, a gate of the first transistor 201 being connected to a target bit line of the memory as an input terminal IN1 of the first signal processing circuit 200, the first signal processing circuit 200 outputting a first signal from an output terminal OUT1 based on a potential of the target bit line IN a first test mode; the second signal processing circuit 210 including the second transistor 211, the gate of the second transistor 211 is connected to the reference bit line of the memory as the input terminal IN2 of the second signal processing circuit 210, and the second signal processing circuit 210 outputs the second signal from the output terminal OUT2 based on the potential of the reference bit line IN the second test mode.

As can be seen from the above analysis, the bit lines performing the first test mode are interfered by the surrounding bit lines and the bit lines performing the second test mode are interfered by the surrounding bit lines, and if the potential of the reference bit line defining the data representing the high level is the reference potential, the potential of the target bit line defining the data representing the high level is the target potential, and the bit lines adjacent to the reference bit line are all written with the data representing the low level, the potential of the reference bit line is pulled down. In the first test mode, all bit lines adjacent to the target bit line write data representing a high level, and the potential of the target bit line is pulled up due to coupling of the adjacent bit lines, so that the target potential is higher than the reference potential. The data representing the high level written by the target bit line is the same as the data representing the high level written by the reference bit line.

Referring to fig. 4 and 5, the gate of the first transistor 201 is driven by the target potential to turn on the first transistor 201, and the gate of the second transistor 211 is driven by the reference potential to turn on the second transistor 211. It should be noted that, the first transistor 201 and the second transistor 211 are identical, and the reference potential is smaller than the target potential, and among the first transistor 201 and the second transistor 211 that receive the gate driving voltage, the first transistor 201 is turned on faster than the second transistor 211, the first signal processing circuit 200 and the second signal processing circuit 210 are also identical, and according to different on-times of the first transistor 201 and the second transistor 211, the first signal processing circuit 200 and the second signal processing circuit 210 output different signals, for example, the first signal processing circuit 200 outputs the first signal, and the second signal processing circuit 210 outputs the second signal. Referring to fig. 6, the frequency of the first signal is the same as the frequency of the second signal, the first signal and the second signal have a phase difference ΔΦ, which is formed based on the potential difference of the reference potential and the target potential.

It should be noted that, in the embodiment of the disclosure, the first transistor 201 and the second transistor 211 are both NMOS transistors.

In some embodiments, referring to fig. 4 and 5, the first transistor 201 and the second transistor 211 are both identical to the second sense NMOS transistor of the sense amplifier of the memory, i.e., the second sense NMOS transistor 103 shown in fig. 1. The first transistor 201 and the second transistor 211 are set to be the same as the second sensing NMOS 103, and then the bias voltage of the second sensing NMOS 103 of the sense amplifier can be adjusted according to the bias voltage of the first transistor 201, so that the memory has a third sensing margin in the first test mode.

In some embodiments, referring to fig. 4 and 5, the first signal processing circuit 200 is a ring oscillator, the first signal processing circuit 200 further includes a first inverter group 202, an input terminal of the first inverter group 202 is connected to the first pole 10a of the first transistor 201, and an output terminal of the first inverter group 202 is connected to the second pole 10b of the first transistor 201. The second signal processing circuit 210 is a ring oscillator, and the second signal processing circuit 210 further includes a second inverter group 212, an input terminal of the second inverter group 212 is connected to the first pole 20a of the second transistor 211, and an output terminal of the second inverter group 212 is connected to the second pole 20b of the second transistor 211. It should be noted that, the output end of the first inverter group 202 is the output end OUT1 of the first signal processing circuit 200, and the output end of the second inverter group 212 is the output end OUT2 of the second signal processing circuit 210. The first pole 10a of the first transistor 201 is one of a source or a drain of the first transistor 201, the second pole 10b of the first transistor 201 is the other of the source or the drain of the first transistor 201, the first pole 20a of the second transistor 211 is one of the source or the drain of the second transistor 211, and the second pole 20b of the second transistor 211 is the other of the source or the drain of the second transistor 211. The first transistor 201 and the second transistor 211 are respectively used as switches in the loops of the two ring oscillators, that is, the first transistor 201 can be used for controlling the starting time of the corresponding ring oscillator, the second transistor 211 can be used for controlling the starting time of the corresponding ring oscillator, and the different starting times of the first transistor 201 and the second transistor 211 enable the starting time of the different ring oscillators to be different due to the fact that the reference potential is different from the target potential, and further a phase difference exists between a first signal output by the ring oscillator of the first signal processing circuit 200 and a second signal output by the ring oscillator of the second signal processing circuit 210.

In some embodiments, referring to fig. 5, the first inverter group 202 includes an odd number of first inverters 300 connected in series, the second inverter group 212 includes an odd number of second inverters 301 connected in series, the first inverters 300 are the same as the second inverters 301, and the number of first inverters 300 in the first inverter group 202 is the same as the number of second inverters 301 in the second inverter group 212. Therefore, the frequency of the first signal is guaranteed to be the same as that of the second signal, the amplitude of the first signal is guaranteed to be the same as that of the second signal, and the difficulty in comparing the first signal with the second signal is reduced.

In some embodiments, referring to fig. 5, the number of first inverters 300 in the first inverter group 202 is greater than 20 and less than 50. For example 21, 23, 27, 35 or 37. Since the number of first inverters 300 in the first inverter group 202 is the same as the number of second inverters 301 in the second inverter group 212, the number of second inverters 301 in the second inverter group 212 is greater than 20 and less than 50, and may be 21, 23, 27, 35, or 37, for example. The too few inverters in the first inverter group 202 may cause the frequency of the first signal to be too high, so setting the number of the first inverters 300 in the first inverter group 202 in a range greater than 20 and less than 50 is beneficial to outputting the first signal with higher resolution, and setting the number of the second inverters 301 in the second inverter group 212 in a range greater than 20 and less than 50 is beneficial to outputting the second signal with higher resolution, thereby being beneficial to reducing the difficulty of comparing the first signal with the second signal.

In some embodiments, referring to fig. 5, the first inverter 300 includes a first PMOS transistor (not shown) and a first NMOS transistor (not shown), the second inverter 301 includes a second PMOS transistor (not shown) and a second NMOS transistor (not shown), the source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the same power supply voltage, and the source of the first NMOS transistor and the source of the second NMOS transistor are both connected to the same ground voltage. Note that, since the first inverter 300 is identical to the second inverter 301, the first PMOS transistor is identical to the second PMOS transistor, and the first NMOS transistor is identical to the second NMOS transistor. The source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the same power supply voltage, and the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the same ground voltage, so that consistency of the first inverter 300 and the second inverter 301 is guaranteed, and setting difficulty of the first inverter 300 and the second inverter 301 is reduced.

With continued reference to fig. 4 and 5, the test circuit includes: the comparison circuit 220, the comparison circuit 220 is connected to the output terminal OUT1 of the first signal processing circuit 200 and the output terminal OUT2 of the second signal processing circuit 210, respectively, and the comparison circuit 220 outputs a first potential from the output terminal based on the phase difference between the first signal and the second signal, the magnitude of the first potential being dependent on the magnitude of the phase difference. For example, the comparing circuit 220 is configured to receive the first signal and the second signal, compare the phase of the first signal with the phase of the second signal, obtain a phase difference between the first signal and the second signal, and output a first potential according to the phase difference, where the first potential can be in a linear relationship with the phase difference, so that it is beneficial to directly adjust the phase difference between the first signal and the second signal according to the first potential, and reduce the complexity of the testing circuit.

In some embodiments, the comparison circuit 220 includes a phase detector. The phase detector is a device capable of discriminating a phase difference of an input signal, and an output potential of the phase detector has a certain relationship with the phase difference between two input signals, for example, the phase detector may output a potential having a linear relationship with the phase difference. The use of a phase detector as the comparison circuit 220 is advantageous in reducing the complexity of the test circuit and in reducing the difficulty of setting the test circuit.

With continued reference to fig. 4 and 5, in some embodiments, the test circuit includes: the bias circuit 230, the bias circuit 230 is connected to the output terminal of the comparison circuit 220, and the bias circuit 230 adjusts the lining bias voltage of the first transistor 201 based on the first potential until the first potential is less than a preset value. The bias circuit 230 may control an adjustment value of the bias voltage of the first transistor 201 according to the magnitude of the first potential, and feed back the adjustment value to the bias voltage of the first transistor 201, so as to adjust the threshold voltage of the first transistor 201. The adjusted turn-on time of the first transistor 201 after receiving the target potential is slower and is close to the turn-on time of the second transistor 211, the phase difference between the first signal and the second signal is smaller, and the first potential is smaller until the first potential is smaller than a preset value (for example, the first potential is made to be close to zero), at this time, the liner bias voltage of the first transistor 201 is the required liner bias voltage.

After the first potential is less than the preset value, the first transistor 201 is obtained through the test circuit, and then the lining bias voltage adjustment value is determined according to the lining bias voltage of the first transistor 201. And the lining bias voltage of the sense amplifier is adjusted, so that the sense margin of the first test mode is ensured to be closer to the sense margin of the second test mode, namely, the sense margin of the memory in the first test mode is adjusted to be the third sense margin, and the memory has excellent abnormal coverage capability in the first test mode.

Determining a liner bias voltage adjustment value based on the liner bias voltage of the first transistor 201 and adjusting the liner bias voltage of the sense amplifier includes: the bias voltage of the first transistor 201 is set to the bias voltage of the second sense NMOS transistor of the sense amplifier.

Referring to fig. 5, in some embodiments, the bias circuit 230 includes a window comparator array and a trimming (Trim) circuit, the window comparator array includes a plurality of window comparators connected in parallel, and the window comparators are connected to the Trim circuit for controlling the Trim circuit to output a corresponding voltage. For example, the window comparator array selects a specific window comparator according to the first potential, so that only the selected window comparator of the window comparators outputs a low potential, the remaining window comparators output a high potential, the output ends of different window comparators are connected with the gates of different transistors in the trimming circuit, different nodes in the different transistor control trimming circuit provide a lining bias voltage for the first transistor 201, and different transistors are turned on to enable the trimming circuit to output different voltage adjustment values, so that the lining bias voltage of the first transistor 201 is adjusted in a specific gear. It will be appreciated that in other embodiments, only selected ones of the plurality of window comparators output a high potential and the remaining window comparators output a low potential.

In some embodiments, referring to fig. 7 and 8, the window comparator may be input with an applied voltage URH and an applied voltage URL, where URH is greater than URL, and the window comparator further includes a clipping circuit formed by a resistor R1, a resistor R2, and a regulator DZ. For example, when the input voltage Ui of the window comparator is greater than URH, the diode D1 is turned on and the diode D2 is turned off, and the output voltage u0=uz of the window comparator. When the input voltage Ui of the window comparator is smaller than URL, the diode D1 is turned off and the diode D2 is turned on, and the output voltage u0=uz of the window comparator. When the input voltage Ui of the window comparator is greater than URL and less than URH, both the diode D1 and the diode D2 are turned off, and the output voltage u0=0 of the window comparator.

With respect to the bias circuit, in some embodiments, referring to fig. 7-9, the bias circuit may include a window comparator array 231 and a trimming circuit, the window comparator array 231 including a plurality of parallel window comparators 232, e.g., the window comparator array 231 may include 4 parallel window comparators 232. The trimming circuit comprises a plurality of resistors 233, the resistors 233 are connected in series between a power supply voltage VSS and a ground voltage GND, voltage output nodes a are arranged between adjacent resistors 233, each voltage output node a is connected with a corresponding capacitor 234 and a transistor 235, a first pole of each capacitor 234 is connected with the voltage output node a, a second pole of each capacitor 234 is connected with an output end OUT3 of the biasing circuit, the output end OUT3 of the biasing circuit is used for providing a lining bias voltage for the first transistor, the first pole of the transistor 235 is connected with the voltage output node a, a second pole of the transistor 235 is connected with the output end OUT3 of the biasing circuit, and a grid of the transistor 235 is connected with an output end of the corresponding window comparator 232. The applied voltages URH and the applied voltages URL of the different window comparators 232 in the window comparator array 231 are different, for example, when the input terminals of the window comparators 232 each receive the input voltage Ui, only the output terminal of one window comparator 232 outputs a low level, and the window comparator 232 outputting the low level turns on the corresponding transistor 235, so that the capacitor 234 at the corresponding voltage output node a is broken down, and the corresponding voltage output node a is connected to the output terminal OUT3 of the bias circuit, so that the output terminal OUT3 of the bias circuit outputs the corresponding voltage.

It should be noted that, in other embodiments, the number of the voltage output nodes in the bias circuit may be 7, 8, 9 or 10, and the bias circuit including 4 voltage output nodes a shown in fig. 9 is only an example, and in practical application, the bias circuit may be designed according to the requirement of the lining bias voltage of the first transistor, so that the bias circuit provides the lining bias voltage of more gears for the first transistor.

In the test method provided by the embodiment, the lining bias voltage of the sense amplifier is further adjusted by determining the lining bias voltage adjustment value of the sense amplifier so as to change the performance of the sense amplifier in the first test mode, so that the sensing margin of the memory in the first test mode is closer to the second sensing margin with excellent normal covering capacity, the abnormal covering capacity of the first test mode is improved, the memory is tested by using the first test mode with shorter test time, and the test efficiency of the memory is effectively improved.

Another aspect of the disclosed embodiments also provides a test circuit, which is applicable to the test method provided in the above embodiments, for determining a liner bias voltage adjustment value of a sense amplifier.

In some embodiments, referring to fig. 4 and 5, the test circuit includes: a first signal processing circuit 200 including a first transistor 201, a gate of the first transistor 201 being connected to a target bit line of the memory as an input terminal IN1 of the first signal processing circuit 200, the first signal processing circuit 200 outputting a first signal from an output terminal OUT1 based on a potential of the target bit line IN a first test mode; a second signal processing circuit 210 including a second transistor 211, the gate of the second transistor 211 being connected to the reference bit line of the memory as an input terminal IN2 of the second signal processing circuit 210, the second signal processing circuit 210 outputting a second signal from an output terminal OUT2 based on the potential of the reference bit line IN a second test mode; the comparison circuit 220, the comparison circuit 220 is connected with the output end of the first signal processing circuit 200 and the output end of the second signal processing circuit 210 respectively, the comparison circuit 220 outputs the first potential from the output end based on the phase difference of the first signal and the second signal, the magnitude of the first potential depends on the magnitude of the phase difference; the bias circuit 230, the bias circuit 230 is connected to the output terminal of the comparison circuit 220, and the bias circuit 230 adjusts the lining bias voltage of the first transistor 201 based on the first potential until the first potential is less than a preset value.

The first signal processing circuit 200 and the second signal processing circuit 210 in the test circuit are used for respectively processing the potential of the target bit line and the potential of the reference bit line to output a first signal and a second signal with a phase difference, the phase difference between the first signal and the second signal is converted into the first potential by the comparison circuit 220, the bias voltage of the first transistor 201 in the first signal processing circuit 200 is adjusted according to the first potential until the first potential is smaller than a preset value, so that the first signal and the second signal with a smaller phase difference can be output by adjusting the bias voltage of the first transistor 201, and then the bias voltage of the sense amplifier of the memory is adjusted according to the adjusted bias voltage of the first transistor 201, so that the sense margin of the memory in the first test mode is ensured to be closer to the sense margin of the memory in the second test mode, the abnormal coverage capability of the first test mode is facilitated to be improved, the memory is tested by using the first test mode with shorter test time, and the test efficiency of the memory is effectively improved.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should therefore be assessed as that of the appended claims.

Claims

1. A method of testing, comprising: providing a memory, wherein the memory has a first sensing margin in a first test mode and a second sensing margin in a second test mode, the test time of the first test mode is smaller than the test time of the second test mode, and the first sensing margin is larger than the second sensing margin;

determining a lining bias voltage adjustment value of a sense amplifier of the memory, wherein after the lining bias voltage of the sense amplifier is adjusted by the lining bias voltage adjustment value, the memory can have a third sensing margin in the first test mode, and the difference value between the third sensing margin and the second sensing margin is smaller than the difference value between the first sensing margin and the second sensing margin;

and adjusting the lining bias voltage of the sense amplifier according to the lining bias voltage adjusting value, and testing the whole memory by adopting the first test mode.

2. The test method of claim 1, wherein the sense amplifier comprises a first sense NMOS, a second sense NMOS, a first sense PMOS, and a second sense PMOS, the first pole of the first sense NMOS, the first pole of the first sense PMOS, the gate of the second sense NMOS, and the gate of the second sense PMOS are each coupled to a bit line corresponding to a memory cell to be tested in the memory, the first pole of the second sense NMOS, the first pole of the second sense PMOS, the gate of the first sense NMOS, and the gate of the first sense PMOS are each coupled to complementary bit lines corresponding to the bit lines, the second pole of the first sense NMOS, and the second pole of the second sense PMOS are each coupled to a second pole of the second sense PMOS; adjusting the liner bias voltage of the sense amplifier according to the liner bias voltage adjustment value includes: and adjusting the lining bias voltage of the second sensing NMOS tube of the sensing amplifier according to the lining bias voltage adjusting value.

3. The method of claim 1, wherein the memory comprises a plurality of sets of bit lines, each set of bit lines comprising N bit lines arranged in succession, N being an integer greater than 1;

the first test mode includes: writing first test data into memory cells corresponding to at least one group of bit lines, wherein the first test data are all data representing high level;

the second test mode includes: and writing second test data into the memory cells corresponding to at least one group of bit lines, wherein one bit of data in the second test data is data representing high level, and the rest bit of data is data representing low level.

4. The method of testing of claim 3, wherein determining the liner bias voltage adjustment value of the sense amplifier of the memory comprises:

providing a test circuit, the test circuit comprising:

a first signal processing circuit including a first transistor, a gate of the first transistor being connected as an input terminal of the first signal processing circuit to a target bit line of the memory, the first signal processing circuit outputting a first signal from an output terminal based on a potential of the target bit line in the first test mode;

A second signal processing circuit including a second transistor, a gate of the second transistor being connected as an input terminal of the second signal processing circuit to a reference bit line of the memory, the second signal processing circuit outputting a second signal from an output terminal based on a potential of the reference bit line in the second test mode;

the comparison circuit is respectively connected with the output end of the first signal processing circuit and the output end of the second signal processing circuit, and outputs a first potential from the output end based on the phase difference of the first signal and the second signal, wherein the magnitude of the first potential depends on the magnitude of the phase difference;

the bias circuit is connected with the output end of the comparison circuit and is used for adjusting the lining bias voltage of the first transistor based on the first potential until the first potential is smaller than a preset value;

and acquiring the lining bias voltage of the first transistor when the first potential is smaller than the preset value, and determining the lining bias voltage adjusting value according to the lining bias voltage of the first transistor.

5. The test method of claim 4, wherein the comparison circuit comprises a phase detector.

6. The test method of claim 4 or 5, wherein the bias circuit comprises a window comparator array and a trimming circuit, the window comparator array comprising a plurality of window comparators connected in parallel, the window comparators being connected to the trimming circuit for controlling the trimming circuit to output corresponding voltages.

7. The method of testing of claim 4, wherein the first transistor and the second transistor are each identical to a second sense NMOS transistor of a sense amplifier of the memory in the test circuit.

8. The test method according to claim 4 or 7, wherein in the test circuit, the first signal processing circuit is a ring oscillator, the first signal processing circuit further comprises a first inverter group, an input terminal of the first inverter group is connected to a first pole of the first transistor, and an output terminal of the first inverter group is connected to a second pole of the first transistor;

the second signal processing circuit is a ring oscillator, the second signal processing circuit further comprises a second inverter group, the input end of the second inverter group is connected with the first pole of the second transistor, and the output end of the second inverter group is connected with the second pole of the second transistor.

9. The method of testing of claim 8, wherein the first inverter group comprises an odd number of first inverters in series, the second inverter group comprises an odd number of second inverters in series, the first inverters are the same as the second inverters, and the number of first inverters in the first inverter group is the same as the number of second inverters in the second inverter group.

10. The method of testing of claim 9, wherein the number of the first inverters in the first inverter group is greater than 20 and less than 50.

11. The method of claim 9, wherein the first inverter comprises a first PMOS transistor and a first NMOS transistor, the second inverter comprises a second PMOS transistor and a second NMOS transistor, the source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the same power supply voltage, and the source of the first NMOS transistor and the source of the second NMOS transistor are both connected to the same ground voltage.

12. The method of testing as claimed in claim 4, wherein said obtaining a liner bias voltage of the first transistor when the first potential is less than the preset value comprises:

Setting the reference bit line and the target bit line, and connecting the reference bit line and the target bit line with the test circuit;

setting the reference bit line and the target bit line includes:

selecting any two groups of bit lines which are independent of each other from the multiple groups of bit lines as a first group of bit lines and a second group of bit lines, writing the first test data into a memory cell corresponding to the first group of bit lines, and writing the second test data into a memory cell corresponding to the second group of bit lines, wherein the memory cell corresponding to the nth bit line of the second group of bit lines is written with data representing high level, the nth bit line of the second group of bit lines is used as the reference bit line, and the nth bit line of the first group of bit lines is used as the target bit line.

13. The method of claim 12, wherein N is an even number, N is N/2 or N is N/2+1.

14. The test method of claim 13, wherein N is 8 and N is 4 or 5.

15. A test circuit, comprising:

a first signal processing circuit including a first transistor, a gate of the first transistor being connected as an input terminal of the first signal processing circuit to a target bit line of a memory, the first signal processing circuit outputting a first signal from an output terminal based on a potential of the target bit line in a first test mode;

A second signal processing circuit including a second transistor, a gate of the second transistor being connected as an input terminal of the second signal processing circuit to a reference bit line of a memory, the second signal processing circuit outputting a second signal from an output terminal based on a potential of the reference bit line in a second test mode;

and the bias circuit is connected with the output end of the comparison circuit and is used for adjusting the lining bias voltage of the first transistor based on the first potential until the first potential is smaller than a preset value.