CN108922573B - Word line bias generator and method for SRAM - Google Patents
Word line bias generator and method for SRAM Download PDFInfo
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- CN108922573B CN108922573B CN201810537150.4A CN201810537150A CN108922573B CN 108922573 B CN108922573 B CN 108922573B CN 201810537150 A CN201810537150 A CN 201810537150A CN 108922573 B CN108922573 B CN 108922573B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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Abstract
The invention discloses a word line bias generator of SRAM, comprising: a memory cell correction column, a read disturb detection circuit, a voltage regulation circuit; the memory cell correction row consists of a row of memory cells, and word lines connected with the memory cells are correction word lines; the clock signal is connected to the correction word line through the first and second inverters; the clock end of the voltage regulating circuit is connected with a clock signal, and the control end of the voltage regulating circuit is connected with the output end of the reading interference detection circuit; the output end of the voltage regulating circuit is connected to the word line of the array structure and the power supply end of the second inverter; and reading from the maximum power supply voltage, and adjusting the output voltage of the voltage adjusting circuit according to the detection result of the read interference detection circuit, so that the output voltage of the voltage adjusting circuit is maximum under the condition of ensuring correct reading. The invention also discloses a word line bias generation method of the SRAM. The invention can ensure correct reading and improve the reading speed.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a word line bias generator for a Static Random Access Memory (SRAM); the invention also relates to a word line bias generation method of the SRAM.
Background
FIG. 1 is a circuit diagram of a memory cell of a conventional SRAM; the storage unit 101 of the SRAM comprises a Q bit node and a QB bit node which are mutually in opposite phases; each of the memory cells 101 in the SRAM is arranged in an array structure 1.
The storage unit 101 of the SRAM has a 6T-type structure, and the mutually inverted Q-bit node and QB-bit node are formed by coupling and connecting two CMOS inverters, and in fig. 1, the two CMOS inverters of the storage unit 101 are respectively: a CMOS inverter 102a composed of a PMOS transistor MP1 and an NMOS transistor MN3, and a CMOS inverter 102b composed of a PMOS transistor MP2 and an NMOS transistor MN 4.
The array structure 1 of the SRAM is as follows:
the Q bit node of each memory cell 101 is connected to the source of a first NMOS transistor MN1, the QB bit node of each memory cell 101 is connected to the source of a second NMOS transistor MN2, the drain of the first NMOS transistor MN1 of each memory cell 101 in the same column is connected to the same first bit line BL, and the drain of the second NMOS transistor MN2 of each memory cell 101 in the same column is connected to the same second bit line BLB.
The gates of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 of each memory cell 101 in the same row are both connected to the same word line WL.
As shown in fig. 1, when the word line WL is raised, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on, and the values of the Q bit node and the QB bit node, which are storage information of the memory cell 101, can be read by reading signals of the first bit line BL and the second bit line BLB. As shown in fig. 2A, it is a timing diagram of signals when the memory cell of the SRAM is read and read normally by the conventional method; in fig. 2A, a curve 201 represents a signal curve of the first bit line BL, a curve 201 represents a signal curve of the second bit line BLB, a curve 203 represents a signal curve of the word line WL, a curve 204 represents a signal curve of the Q bit node, and a curve 205 represents a signal curve of the QB bit node, assuming that a signal stored in the Q bit node is 1 and a signal stored in the QB bit node is 0. It can be seen that when the word line WL is low, the first bit line BL and the second bit line BLB coincide; when the word line WL is at high level, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on, and the second bit line BLB is connected to the QB node and grounded through the NMOS transistor MN4, so the voltage of the second bit line BLB is gradually decreased to 0V, and the voltage of the QB node is first increased and then slowly decreased until it is decreased to 0V. The voltage of the first bit line BL is kept at a high level, while the voltage of the Q-bit node is slightly increased and then decreased at the moment of conduction with the first bit line BL, and then the voltage of the Q-bit node is slightly decreased and then increased at the moment of switching the word line WL to a low level.
The word line WL voltage is often increased to increase the read rate, but this causes a disturb flip (data flip) problem, which may cause a greater chance of a read disturb flip under process, voltage and temperature (PVT) variations. FIG. 2B is a timing diagram of signals when a memory cell of an SRAM is read and a disturb flip occurs in the read in a conventional method; as shown in fig. 2B, since the voltage of the QB bit node is increased and the voltage of the Q bit node is decreased when the word line WL is switched to the high level, the Q bit node is inverted when the two are equal to each other, as shown by the dotted circle 206, the information of the inverted Q bit node becomes 0, and the information of the QB bit node becomes 1, which is opposite to the originally stored information.
In order to avoid the phenomenon of disturbance inversion during reading as shown in fig. 2B, the voltage of the word line WL is often reduced in the conventional method, as shown in fig. 2C, which is a timing diagram of signals when the word line voltage is reduced based on fig. 2B and then the memory cell of the SRAM is read and read normally in the conventional method; it can be seen that the high level voltage of the word line WL in fig. 2C is reduced to be lower than the voltage of the Q-bit node, and at this time, the voltages of the QB-bit node and the Q-bit node are well separated, and the voltages of the QB-bit node and the Q-bit node are not equal, so that the phenomenon of disturb and flip does not occur.
However, since the voltage of the word line WL is lowered to cause a drawback that the read rate is lowered, the conventional method sacrifices the important performance of the read rate in order to realize accurate reading.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a word line bias generator of an SRAM, which can provide the maximum voltage for the word line of the SRAM under the condition of ensuring no read disturb, thereby optimizing the voltage of the word line of the SRAM, and improving the read rate while ensuring correct read. Therefore, the invention also provides a word line bias generation method of the SRAM.
In order to solve the above technical problem, in the word line bias generator of the SRAM according to the present invention, a storage unit of the SRAM includes a Q bit node and a QB bit node that are inverted with respect to each other; each memory cell in the SRAM is arranged into an array structure; the voltage of the word line in the array structure is provided by a word line bias generator.
The word line bias voltage generator includes: a memory cell correction column, a read disturb detection circuit, and a voltage regulation circuit.
The memory cell correction row is composed of a row of memory cells, and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube of each memory cell in the memory cell correction row are connected to a correction word line; the drains of the first NMOS transistors of the memory cells of the memory cell correction row are connected together and connected to a first end of a pre-charge unit, and the drains of the second NMOS transistors of the memory cells of the memory cell correction row are connected together and connected to a second end of the pre-charge unit.
The clock signal is connected to the correction word line through a first inverter and a second inverter.
The clock end of the voltage regulating circuit is connected with a clock signal, and the control end of the voltage regulating circuit is connected with the output end of the reading interference detection circuit.
An output terminal of the voltage regulating circuit is connected to the word line of the array structure and a power terminal of the second inverter.
The output voltage of the voltage regulating circuit is adjustable, and the word line bias generator adjusts the output voltage of the voltage regulating circuit which is finally output to the word line through the following correction steps:
step one, the output voltage of the voltage regulating circuit is selected as a power supply voltage.
Reading each memory cell of the memory cell correction row under the control of the clock signal, detecting whether interference inversion is generated in the reading process of each memory cell of the memory cell correction row through the reading interference detection circuit, forming a detection result signal and sending the detection result signal to the control end of the voltage regulation circuit.
Step three, the voltage regulating circuit regulates the output voltage of the voltage regulating circuit according to the detection result signal; and if the detection result signal indicates that the interference overturning situation exists, reducing the output voltage of the voltage regulating circuit, and then repeating the step two.
And if the detection result signal is that no interference overturning situation exists, the output voltage of the voltage regulating circuit is unchanged and is used as the output voltage finally output to the word line.
A further improvement is that the read disturb detecting circuit is composed of a plurality of read disturb detecting units, each of the read disturb detecting units is arranged in a row, the number of the read disturb detecting units included in the read disturb detecting circuit is the same as the number of the memory cells in the memory cell correction row, each of the read disturb detecting units corresponds to one of the memory cells in the memory cell correction row, an input end of each of the read disturb detecting units is connected to a data node of the memory cell in the memory cell correction row corresponding to the input end of the read disturb detecting unit, and an output end of each of the read disturb detecting units outputs a disturb flip detection result for the connected memory cell and serves as one bit in the detection result signal.
In a further improvement, each of the read disturb detection units is comprised of a third inverter.
In a further improvement, an input end of each read disturb detection unit is connected to a QB bit node of the corresponding storage unit; or the input end of each read disturb detection unit is connected with the Q-bit node of the corresponding storage unit.
In a further improvement, the third inverter of each read disturb detect unit is a CMOS inverter.
In a further refinement, the voltage regulation circuit includes:
the reference voltage generating circuit, the first comparator and the first PMOS tube.
And the clock end of the reference voltage generating circuit is used as the clock end of the voltage regulating circuit.
And the control end of the reference voltage generating circuit is used as the control end of the voltage regulating circuit.
The output end of the reference voltage generating circuit is connected with the first input end of the first comparator, the output end of the first comparator is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the power supply voltage, the drain electrode of the first PMOS tube is connected with the second input end of the first comparator, and the drain electrode of the first PMOS tube serves as the output end of the voltage regulating circuit.
The reference voltage output by the output end of the reference voltage generating circuit is regulated under the control of the detection result signal of the control end.
In a further improvement, the pre-charging unit comprises a second PMOS transistor and a third PMOS transistor, and a source electrode of the second PMOS transistor and a source electrode of the third PMOS transistor are both connected with a power supply.
And the drain electrode of the second PMOS tube is used as the first end of the pre-charging unit.
And the drain electrode of the third PMOS tube is used as a second end of the pre-charging unit.
And the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are both connected with the clock signal.
The pre-charging unit further comprises a fourth PMOS tube, wherein the grid electrode of the fourth PMOS tube is connected with the grid electrode of the second PMOS tube, the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube.
The further improvement is that the storage unit of the SRAM is in a 6T type structure, and a Q bit node and a QB bit node which are opposite in phase are formed by coupling and connecting two CMOS inverters.
The further improvement is that the array structure of the SRAM is as follows:
the Q bit node of each memory cell is connected with the source electrode of the first NMOS tube, the QB bit node of each memory cell is connected with the source electrode of the second NMOS tube, the drain electrode of the first NMOS tube of each memory cell in the same column is connected to the same first bit line, and the drain electrode of the second NMOS tube of each memory cell in the same column is connected to the same second bit line.
The grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube of each memory unit in the same row are connected to the same word line.
In order to solve the above technical problem, in the word line bias generating method of the SRAM according to the present invention, a storage unit of the SRAM includes a Q bit node and a QB bit node that are inverted with respect to each other; each memory cell in the SRAM is arranged into an array structure; the voltage of the word line in the array structure is provided by a word line bias generator.
The word line bias voltage generator includes: a memory cell correction column, a read disturb detection circuit, and a voltage regulation circuit.
The memory cell correction row is composed of a row of memory cells, and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube of each memory cell in the memory cell correction row are connected to a correction word line; the drains of the first NMOS transistors of the memory cells of the memory cell correction row are connected together and connected to a first end of a pre-charge unit, and the drains of the second NMOS transistors of the memory cells of the memory cell correction row are connected together and connected to a second end of the pre-charge unit.
The clock signal is connected to the correction word line through a first inverter and a second inverter.
The clock end of the voltage regulating circuit is connected with a clock signal, and the control end of the voltage regulating circuit is connected with the output end of the reading interference detection circuit.
An output terminal of the voltage regulating circuit is connected to the word line of the array structure and a power terminal of the second inverter.
The output voltage of the voltage regulating circuit is adjustable, and the word line bias generator adjusts the output voltage of the voltage regulating circuit which is finally output to the word line through the following correction steps:
step one, the output voltage of the voltage regulating circuit is selected as a power supply voltage.
Reading each memory cell of the memory cell correction row under the control of the clock signal, detecting whether interference inversion is generated in the reading process of each memory cell of the memory cell correction row through the reading interference detection circuit, forming a detection result signal and sending the detection result signal to the control end of the voltage regulation circuit.
Step three, the voltage regulating circuit regulates the output voltage of the voltage regulating circuit according to the detection result signal; and if the detection result signal indicates that the interference overturning situation exists, reducing the output voltage of the voltage regulating circuit, and then repeating the step two.
And if the detection result signal is that no interference overturning situation exists, the output voltage of the voltage regulating circuit is unchanged and is used as the output voltage finally output to the word line.
A further improvement is that the read disturb detecting circuit is composed of a plurality of read disturb detecting units, each of the read disturb detecting units is arranged in a row, the number of the read disturb detecting units included in the read disturb detecting circuit is the same as the number of the memory cells in the memory cell correction row, each of the read disturb detecting units corresponds to one of the memory cells in the memory cell correction row, an input end of each of the read disturb detecting units is connected to a data node of the memory cell in the memory cell correction row corresponding to the input end of the read disturb detecting unit, and an output end of each of the read disturb detecting units outputs a disturb flip detection result for the connected memory cell and serves as one bit in the detection result signal.
In a further improvement, each of the read disturb detection units is comprised of a third inverter.
In a further improvement, an input end of each read disturb detection unit is connected to a QB bit node of the corresponding storage unit; or the input end of each read disturb detection unit is connected with the Q-bit node of the corresponding storage unit.
In a further refinement, the voltage regulation circuit includes:
the reference voltage generating circuit, the first comparator and the first PMOS tube.
And the clock end of the reference voltage generating circuit is used as the clock end of the voltage regulating circuit.
And the control end of the reference voltage generating circuit is used as the control end of the voltage regulating circuit.
The output end of the reference voltage generating circuit is connected with the first input end of the first comparator, the output end of the first comparator is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the power supply voltage, the drain electrode of the first PMOS tube is connected with the second input end of the first comparator, and the drain electrode of the first PMOS tube serves as the output end of the voltage regulating circuit.
The reference voltage output by the output end of the reference voltage generating circuit is regulated under the control of the detection result signal of the control end.
The word line bias voltage generator of the present invention provides the word lines of the array structure of the SRAM with voltages obtained by a calibration step, which starts a read test from the maximum power supply voltage and performs a test, and further detecting whether the interference inversion exists in the result to adjust the output voltage of the word line bias generator, finally ensuring that the maximum output voltage of the word line bias generator is obtained under the condition of no read interference inversion, ensuring correct reading of the storage unit of the SRAM if no read interference inversion exists, and increasing the voltage of the word line to increase the reading speed of the storage unit of the SRAM, the present invention can provide the maximum voltage to the word line of the SRAM under the condition of ensuring that no read disturb occurs, therefore, the voltage of the word line of the SRAM is optimized, and the reading speed can be improved while the correct reading is ensured; meanwhile, the invention also has no influence on the clock signal and the clock control.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a circuit diagram of a memory cell of a conventional SRAM;
FIG. 2A is a timing diagram of signals when a memory cell of an SRAM is read and read normally by a conventional method;
FIG. 2B is a timing diagram of signals when a memory cell of an SRAM is read and a disturb flip occurs in the read in a conventional method;
FIG. 2C is a timing diagram of signals in a conventional method for reading a memory cell of an SRAM after lowering a word line voltage based on FIG. 2B and reading the memory cell normally;
FIG. 3 is a circuit diagram of a word line bias generator of an SRAM according to an embodiment of the present invention;
FIG. 4 is a flow chart of output voltage adjustment of a word line bias generator of an SRAM according to an embodiment of the present invention;
fig. 5 is a timing diagram of signals during output voltage adjustment of the corresponding word line bias generator of fig. 4.
Detailed Description
FIG. 3 is a circuit diagram of a word line bias generator of an SRAM according to an embodiment of the present invention; FIG. 4 is a flow chart of the output voltage Vtrim adjustment of the word line bias generator of the SRAM according to the embodiment of the present invention; FIG. 5 is a timing diagram of signals during the adjustment of the output voltage Vtrim of the word line bias generator of the SRAM of FIG. 4, in which the memory cell 101 of the SRAM includes a Q bit node and a QB bit node that are inverted with respect to each other according to the embodiment of the present invention; each memory cell 101 in the SRAM is arranged in an array structure 1; the voltage of the word line WL in the array structure 1 is provided by a word line bias generator.
Referring to fig. 1, the structure of the storage unit 101 is shown in fig. 1, the storage unit 101 of the SRAM has a 6T-type structure, and a Q-bit node and a QB-bit node that are opposite in phase are formed by coupling and connecting two CMOS inverters, in fig. 1, the two CMOS inverters of the storage unit 101 are respectively: a CMOS inverter 102a composed of a PMOS transistor MP1 and an NMOS transistor MN3, and a CMOS inverter 102b composed of a PMOS transistor MP2 and an NMOS transistor MN 4. In fig. 3, CMOS inverters 102a and 102b are shown directly.
The array structure 1 of the SRAM is as follows:
the Q bit node of each memory cell 101 is connected to the source of a first NMOS transistor MN1, the QB bit node of each memory cell 101 is connected to the source of a second NMOS transistor MN2, the drain of the first NMOS transistor MN1 of each memory cell 101 in the same column is connected to the same first bit line BL, and the drain of the second NMOS transistor MN2 of each memory cell 101 in the same column is connected to the same second bit line BLB.
The gates of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 of each memory cell 101 in the same row are both connected to the same word line WL.
The word line bias voltage generator includes: a memory cell correction column 2, a read disturb detection circuit 3, and a voltage regulation circuit.
The memory cell correction row 2 is composed of a row of the memory cells 101, and the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 of each memory cell 101 in the memory cell correction row 2 are both connected to a correction word line dmyWL; the drains of the first NMOS transistors MN1 of the memory cells 101 of the memory cell correction row 2 are connected together and to a first terminal of a precharge unit 3, and the drains of the second NMOS transistors MN2 of the memory cells 101 of the memory cell correction row 2 are connected together and to a second terminal of the precharge unit 3.
The clock signal CLK is connected to the correction word line dmyWL through the first inverter 6a and the second inverter 6 b.
The clock end of the voltage regulating circuit is connected with a clock signal CLK, and the control end of the voltage regulating circuit is connected with the output end of the reading interference detection circuit 3.
The output of the voltage regulating circuit is connected to the word line WL of the array structure 1 and to the power supply terminal of the second inverter 6 b.
In the embodiment of the present invention, the read disturb detecting circuit 3 is composed of a plurality of read disturb detecting units 31, each of the read disturb detecting units 31 is arranged in a row, and the number of the read disturb detecting units 31 included in the read disturb detecting circuit 3 is the same as the number of the memory cells 101 in the memory cell correction row 2; the number N of the memory cells 101 of the memory cell correction row 2 shown in fig. 3 in the same row is an integer as shown by XN in fig. 3; the number of the read disturb detection units 31 is also N.
Each of the read disturb detecting units 31 corresponds to one of the memory cells 101 in the memory cell correction row 2, an input terminal of each of the read disturb detecting units 31 is connected to a data node of the memory cell 101 in the corresponding memory cell correction row 2, and an output terminal of each of the read disturb detecting units 31 outputs a disturb flip detection result for the connected memory cell 101 as one bit of the detection result signal Vref tunning; since the number of the read disturb detecting units 31 is N, the detection result signal Vref tuning finally includes an N-bit signal,
each of the read disturb detecting units 31 is composed of a third inverter. Preferably, the third inverter of each read disturb detecting unit 31 is a CMOS inverter.
An input terminal of each read disturb detect unit 31 is connected to the QB bit node of the corresponding memory cell 101. In other embodiments can also be: the input terminal of each read disturb detect unit 31 is connected to the Q-bit node of the corresponding memory cell 101.
In fig. 3, the output end of each read disturb detecting unit 31 is further connected to the input end of the inverter 32, and the signal detected by each read disturb detecting unit 31 is output after the inversion of the inverter 32.
The voltage regulating circuit includes:
a reference voltage generating circuit 4, a first comparator 5, and a first PMOS transistor MP 101.
The clock terminal of the reference voltage generating circuit 4 serves as the clock terminal of the voltage regulating circuit.
The control terminal of the reference voltage generating circuit 4 serves as the control terminal of the voltage regulating circuit.
The output end of the reference voltage generating circuit 4 is connected to the first input end of the first comparator 5, the output end of the first comparator 5 is connected to the gate of the first PMOS transistor MP101, the source of the first PMOS transistor MP101 is connected to the power voltage VDD, the drain of the first PMOS transistor MP101 is connected to the second input end of the first comparator 5, and the drain of the first PMOS transistor MP101 serves as the output end of the voltage regulating circuit. In the embodiment of the present invention, an inverting input terminal of the first comparator 5 is a negative terminal, and the second input terminal of the first comparator 5 is a positive phase input terminal.
The reference voltage Vref output by the output terminal of the reference voltage generation circuit 4 is adjusted under the control of the detection result signal Vref tunning of the control terminal.
The pre-charging unit 3 comprises a second PMOS transistor MP102 and a third PMOS transistor MP103, wherein a source electrode of the second PMOS transistor MP102 and a source electrode of the third PMOS transistor MP103 are both connected to a power voltage VDD.
The drain of the second PMOS transistor MP102 serves as the first end of the precharge unit 3.
The drain of the third PMOS transistor MP103 serves as the second terminal of the precharge unit 3.
The gates of the second PMOS transistor MP102 and the third PMOS transistor MP103 are both connected to the clock signal CLK.
The pre-charging unit 3 further includes a fourth PMOS transistor MP104, a gate of the fourth PMOS transistor MP104 is connected to a gate of the second PMOS transistor MP102, a source of the fourth PMOS transistor MP104 is connected to a drain of the second PMOS transistor MP102, and a drain of the fourth PMOS transistor MP104 is connected to a drain of the third PMOS transistor MP 103.
The output voltage Vtrim of the voltage regulating circuit is adjustable, as shown in fig. 4, and the word line bias generator adjusts the output voltage Vtrim of the voltage regulating circuit finally output to the word line WL by the following correction steps:
step one, the output voltage Vtrim of the voltage regulating circuit is selected as a power supply voltage VDD.
Reading each memory cell 101 of the memory cell correction row 2 under the control of the clock signal CLK, detecting whether or not a disturb flip occurs in the reading process of each memory cell 101 of the memory cell correction row 2 through the read disturb detection circuit 3, forming a detection result signal Vref tunning, and sending the detection result signal Vref tunning to the control end of the voltage regulation circuit.
Step three, the voltage regulating circuit regulates the output voltage Vtrim of the voltage regulating circuit according to the detection result signal Vref tunning; and if the detection result signal Vref tunning is that the interference upset condition exists, the output voltage Vtrim of the voltage regulating circuit is reduced, and then the step two is repeated.
If the detection result signal Vref tunning is that there is no disturb flip-flop, the output voltage Vtrim of the voltage regulating circuit is unchanged and is the output voltage Vtrim finally output to the word line WL.
As shown in fig. 5, when the output voltage Vtrim of the voltage regulator circuit corresponding to step one is selected as the power supply voltage VDD, the maximum voltage applied to the correction word line dmyWL through the clock signal CLK is the power supply voltage VDD, and when the correction word line dmyWL is the power supply voltage VDD, it can be seen that the stored signals of the Q and QB bit nodes are subjected to disturb flip-flop after the read operation of step two, as shown by the dotted power 302. In this case, the output voltage Vtrim of the voltage regulator circuit needs to be decreased in the subsequent step, the voltage of the correction word line dmyWL is decreased when the clock signal CLK is at the high level, and then steps two and three are repeated, and the voltage of the correction word line dmyWL is decreased slightly when the clock signal CLK is at the high level every cycle, as shown by arrow line 301 in fig. 5. Finally, in the clock period corresponding to the end position, the stored signals of the Q and QB bit nodes can not be disturbed and overturned, and the correct reading of the storage unit can be ensured, so that the voltage of the word line in the array structure of the SRAM can be made.
The voltage supplied by the word line bias generator to the word lines WL of the array structure 1 of the SRAM is obtained by a calibration step, which starts a read test from the maximum power supply voltage VDD and performs a test, and further detecting whether there is a disturb flip to adjust the output voltage Vtrim of the word line bias generator, and finally ensuring that the maximum output voltage Vtrim of the word line bias generator is obtained under the condition that there is no read disturb flip, and ensuring correct reading of the memory cell 101 of the SRAM without read disturb flip, while the greater the voltage of the word line WL the faster the read rate of the memory cell 101 of the SRAM, the embodiment of the present invention can provide the maximum voltage for the word line WL of the SRAM under the condition of ensuring that no read disturb occurs, therefore, the voltage of the word line WL of the SRAM is optimized, and the reading speed can be improved while the correct reading is ensured. Meanwhile, the embodiment of the invention also has no influence on the clock signal and the clock control.
In the word line WL bias generating method of the SRAM of the embodiment of the present invention, the word line bias generator adjusts the output voltage Vtrim of the voltage adjusting circuit finally output to the word line WL by the following correction steps:
step one, the output voltage Vtrim of the voltage regulating circuit is selected as a power supply voltage VDD.
Reading each memory cell 101 of the memory cell correction row 2 under the control of the clock signal CLK, detecting whether or not a disturb flip occurs in the reading process of each memory cell 101 of the memory cell correction row 2 through the read disturb detection circuit 3, forming a detection result signal Vref tunning, and sending the detection result signal Vref tunning to the control end of the voltage regulation circuit.
Step three, the voltage regulating circuit regulates the output voltage Vtrim of the voltage regulating circuit according to the detection result signal Vref tunning; and if the detection result signal Vref tunning is that the interference upset condition exists, the output voltage Vtrim of the voltage regulating circuit is reduced, and then the step two is repeated.
If the detection result signal Vref tunning is that there is no disturb flip-flop, the output voltage Vtrim of the voltage regulating circuit is unchanged and is the output voltage Vtrim finally output to the word line WL.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A word line bias generator for an SRAM, comprising: the storage unit of the SRAM comprises a Q bit node and a QB bit node which are mutually in opposite phases; each memory cell in the SRAM is arranged into an array structure; the voltage of the word line in the array structure is provided by a word line bias voltage generator;
the word line bias voltage generator includes: a memory cell correction column, a read disturb detection circuit, a voltage regulation circuit;
the memory cell correction row is composed of a row of memory cells, and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube of each memory cell in the memory cell correction row are connected to a correction word line; the drains of the first NMOS transistors of the memory cells in the memory cell correction row are connected together and connected to a first end of a pre-charge unit, and the drains of the second NMOS transistors of the memory cells in the memory cell correction row are connected together and connected to a second end of the pre-charge unit;
a clock signal is connected to the correction word line through a first inverter and a second inverter;
the clock end of the voltage regulating circuit is connected with a clock signal, and the control end of the voltage regulating circuit is connected with the output end of the reading interference detection circuit;
an output end of the voltage regulating circuit is connected to the word line of the array structure and a power end of the second inverter;
the output voltage of the voltage regulating circuit is adjustable, and the word line bias generator adjusts the output voltage of the voltage regulating circuit which is finally output to the word line through the following correction steps:
step one, the output voltage of the voltage regulating circuit is selected as a power supply voltage;
reading each memory cell of the memory cell correction row under the control of the clock signal, detecting whether interference inversion is generated in the reading process of each memory cell of the memory cell correction row through the read interference detection circuit, forming a detection result signal and sending the detection result signal to the control end of the voltage regulation circuit;
step three, the voltage regulating circuit regulates the output voltage of the voltage regulating circuit according to the detection result signal; if the detection result signal is that the interference overturning situation exists, reducing the output voltage of the voltage regulating circuit, and then repeating the step two;
and if the detection result signal is that no interference overturning situation exists, the output voltage of the voltage regulating circuit is unchanged and is used as the output voltage finally output to the word line.
2. The word line bias generator of SRAM of claim 1, wherein: the reading interference detection circuit is composed of a plurality of reading interference detection units, each reading interference detection unit is arranged in a line, the number of the reading interference detection units included in the reading interference detection circuit is the same as the number of the storage units in the storage unit correction line, each reading interference detection unit corresponds to one storage unit in the storage unit correction line, the input end of each reading interference detection unit is connected with the data node of the storage unit in the corresponding storage unit correction line, and the output end of each reading interference detection unit outputs an interference overturning detection result of the connected storage unit and serves as one bit in the detection result signal.
3. The word line bias generator of SRAM of claim 2, wherein: each of the read disturb detecting units is composed of a third inverter.
4. The word line bias generator of SRAM of claim 3, wherein: the input end of each read interference detection unit is connected with the QB bit node of the corresponding storage unit; or the input end of each read disturb detection unit is connected with the Q-bit node of the corresponding storage unit.
5. The word line bias generator of SRAM of claim 2, wherein: the third inverter of each read disturb detect unit is a CMOS inverter.
6. The word line bias generator of SRAM of claim 1, wherein: the voltage regulating circuit includes:
the reference voltage generating circuit, the first comparator and the first PMOS tube;
a clock end of the reference voltage generating circuit is used as a clock end of the voltage regulating circuit;
the control end of the reference voltage generating circuit is used as the control end of the voltage regulating circuit;
the output end of the reference voltage generating circuit is connected with the first input end of the first comparator, the output end of the first comparator is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the power supply voltage, the drain electrode of the first PMOS tube is connected with the second input end of the first comparator, and the drain electrode of the first PMOS tube is used as the output end of the voltage regulating circuit;
the reference voltage output by the output end of the reference voltage generating circuit is regulated under the control of the detection result signal of the control end.
7. The word line bias generator of SRAM of claim 1, wherein: the pre-charging unit comprises a second PMOS tube and a third PMOS tube, and a source electrode of the second PMOS tube and a source electrode of the third PMOS tube are both connected with a power supply voltage;
the drain electrode of the second PMOS tube is used as the first end of the pre-charging unit;
the drain electrode of the third PMOS tube is used as a second end of the pre-charging unit;
and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are both connected with the clock signal.
8. The word line bias generator of SRAM of claim 7, wherein: the pre-charging unit further comprises a fourth PMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the second PMOS tube, the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube.
9. The word line bias generator of SRAM of claim 1, wherein: the storage unit of the SRAM is of a 6T-shaped structure, and a Q bit node and a QB bit node which are mutually opposite in phase are formed by coupling and connecting two CMOS inverters.
10. The word line bias generator of SRAM of claim 1, wherein: the array structure of the SRAM is as follows:
the Q bit node of each memory cell is connected with the source electrode of the first NMOS transistor, the QB bit node of each memory cell is connected with the source electrode of the second NMOS transistor, the drain electrodes of the first NMOS transistors of the memory cells in the same column are connected to the same first bit line, and the drain electrodes of the second NMOS transistors of the memory cells in the same column are connected to the same second bit line;
the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube of each memory unit in the same row are connected to the same word line.
11. A word line bias generation method of SRAM is characterized in that: the storage unit of the SRAM comprises a Q bit node and a QB bit node which are mutually in opposite phases; each memory cell in the SRAM is arranged into an array structure; the voltage of the word line in the array structure is provided by a word line bias voltage generator;
the word line bias voltage generator includes: a memory cell correction column, a read disturb detection circuit, a voltage regulation circuit;
the memory cell correction row is composed of a row of memory cells, and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube of each memory cell in the memory cell correction row are connected to a correction word line; the drains of the first NMOS transistors of the memory cells in the memory cell correction row are connected together and connected to a first end of a pre-charge unit, and the drains of the second NMOS transistors of the memory cells in the memory cell correction row are connected together and connected to a second end of the pre-charge unit;
a clock signal is connected to the correction word line through a first inverter and a second inverter;
the clock end of the voltage regulating circuit is connected with a clock signal, and the control end of the voltage regulating circuit is connected with the output end of the reading interference detection circuit;
an output end of the voltage regulating circuit is connected to the word line of the array structure and a power end of the second inverter;
the output voltage of the voltage regulating circuit is adjustable, and the word line bias generator adjusts the output voltage of the voltage regulating circuit which is finally output to the word line through the following correction steps:
step one, the output voltage of the voltage regulating circuit is selected as a power supply voltage;
reading each memory cell of the memory cell correction row under the control of the clock signal, detecting whether interference inversion is generated in the reading process of each memory cell of the memory cell correction row through the read interference detection circuit, forming a detection result signal and sending the detection result signal to the control end of the voltage regulation circuit;
step three, the voltage regulating circuit regulates the output voltage of the voltage regulating circuit according to the detection result signal; if the detection result signal is that the interference overturning situation exists, reducing the output voltage of the voltage regulating circuit, and then repeating the step two;
and if the detection result signal is that no interference overturning situation exists, the output voltage of the voltage regulating circuit is unchanged and is used as the output voltage finally output to the word line.
12. The method of generating word line bias voltage for SRAM of claim 11, wherein: the reading interference detection circuit is composed of a plurality of reading interference detection units, each reading interference detection unit is arranged in a line, the number of the reading interference detection units included in the reading interference detection circuit is the same as the number of the storage units in the storage unit correction line, each reading interference detection unit corresponds to one storage unit in the storage unit correction line, the input end of each reading interference detection unit is connected with the data node of the storage unit in the corresponding storage unit correction line, and the output end of each reading interference detection unit outputs an interference overturning detection result of the connected storage unit and serves as one bit in the detection result signal.
13. The method of generating word line bias voltage for SRAM of claim 12, wherein: each of the read disturb detecting units is composed of a third inverter.
14. The method of generating word line bias voltage for SRAM of claim 13, wherein: the input end of each read interference detection unit is connected with the QB bit node of the corresponding storage unit; or the input end of each read disturb detection unit is connected with the Q-bit node of the corresponding storage unit.
15. The method of generating word line bias voltage for SRAM of claim 11, wherein: the voltage regulating circuit includes:
the reference voltage generating circuit, the first comparator and the first PMOS tube;
a clock end of the reference voltage generating circuit is used as a clock end of the voltage regulating circuit;
the control end of the reference voltage generating circuit is used as the control end of the voltage regulating circuit;
the output end of the reference voltage generating circuit is connected with the first input end of the first comparator, the output end of the first comparator is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the power supply voltage, the drain electrode of the first PMOS tube is connected with the second input end of the first comparator, and the drain electrode of the first PMOS tube is used as the output end of the voltage regulating circuit;
the reference voltage output by the output end of the reference voltage generating circuit is regulated under the control of the detection result signal of the control end.
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