CN102867541B - Low-power consumption static memory SRAM - Google Patents
Low-power consumption static memory SRAM Download PDFInfo
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- CN102867541B CN102867541B CN201110188458.0A CN201110188458A CN102867541B CN 102867541 B CN102867541 B CN 102867541B CN 201110188458 A CN201110188458 A CN 201110188458A CN 102867541 B CN102867541 B CN 102867541B
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Abstract
The invention belongs to memory technology field, a kind of static memory SRAM system reducing leakage current is proposed, comprise read/write circuit, ECC error detection/correction circuit, voltage regulator, bias tube and memory cell array, voltage regulator controls the supply voltage that bias tube reduces or increases memory cell array; Read/write circuit, for returning to active pattern, reading cells array content when supply voltage, and is sent to ECC error detection/correction circuit by content; ECC error detection/correction circuit, for error-detection error-correction, and writes back memory cell array by the value after correcting by read/write circuit.The present invention adopts ECC to detect the cell value being in each array of SRAM under standby pattern, reducing the supply voltage of array as far as possible or raising the ground wire voltage of array, to reduce electric leakage as far as possible, realizing extremely low power dissipation when ensureing that hold does not make mistakes.
Description
Technical field
The invention belongs to memory technology field, particularly relate to a kind of low-power consumption static memory SRAM.
Background technology
As shown in Figure 4, be one section of american documentation literature US6560139B2 of prior art Intel, relate to a kind of static memory array of low-leakage current.When SRAM array is in active (read and write) pattern, the ground wire voltage of array reduces, and improves the speed of read and write access; When array is in standby, ground wire voltage is raised, to reduce electric leakage.Fig. 4 illustrate two parts of SRAM array, during access Part I, Part II is not accessed.One section of SRAM equipment about minimizing leakage current that accompanying drawing 5 is applied for for Taiwan Semiconductor Manufacturing Co., Ltd, application number is US7269055B2.When SRAM array is in active (read and write) pattern, the supply voltage of array is raised, and improves the speed of read and write access; When array is in standby, supply voltage reduces, to reduce electric leakage.And US6970374B is the combination of said two devices, reduce leakage current with this.
But, when SRAM is in standby pattern, the mode that tradition reduces probably does not arrive ultimate value, electric leakage can be reduced by reducing supply voltage further or raising ground wire voltage, but supply voltage reduces or ground wire voltage is raised too much, sram cell hold bad stability, even makes mistakes.In addition, due to the impact of technological fluctuation and temperature, different storage arrays enter standby pattern reduction supply voltage and improve the degree of ground wire voltage also can be different.
Summary of the invention
In order to achieve the above object, the present invention proposes a kind of static memory SRAM system reducing leakage current, comprise read/write circuit, ECC error detection/correction circuit, voltage regulator, bias tube and memory cell array, voltage regulator controls the supply voltage that bias tube reduces or increases memory cell array; Read/write circuit, for returning to active pattern, reading cells array content when supply voltage, and is sent to ECC error detection/correction circuit by content; ECC error detection/correction circuit, for error-detection error-correction, and writes back memory cell array by the value after correcting by read/write circuit.
Preferably, ECC error detection/correction circuit is connected with read/write circuit, and is connected with voltage regulator, and voltage regulator is connected with bias tube, and bias tube is connected with the power lead of memory cell array.
Preferably, the storage unit in memory cell array comprises power lead, ground wire, wordline, bit line and paratope line.Read/write circuit is connected with paratope line with the bit line in memory cell array.
In order to achieve the above object, the present invention proposes a kind of method reducing static memory SRAM leakage current, comprises the following steps: (1) voltage regulator controls bias tube and the supply voltage of array element is reduced to V0; (2) supply voltage returns to active pattern, and read/write circuit reads the content of unit in array, then read content is sent into ECC error detection/correction circuit, if make mistakes, adopt ECC error correction, and the value after correcting is write back array by read/write circuit, forward (4) step to; If do not make mistakes, forward (3) step to; (3) adopt voltage regulator to control bias tube and the supply voltage of array element is reduced to Δ V less of the front value once reduced, forward (2) step to; (4) supply voltage of array element is increased Δ V, array enters standby pattern.
Adopt ECC to detect the cell value being in each array of SRAM under standby pattern, reduce the supply voltage of array as far as possible when ensureing that hold does not make mistakes or raise the ground wire voltage of array, to reduce electric leakage as far as possible, realizing extremely low power dissipation.
Accompanying drawing explanation
Fig. 1 is according to one embodiment of the invention low-power consumption SRAM cells;
Fig. 2 is the static memory SRAM system reducing leakage current according to one embodiment of the invention;
Fig. 3 is the static memory SRAM system reducing leakage current according to a further embodiment of the invention;
Fig. 4 is the static memory array of prior art low-leakage current;
Fig. 5 is the SRAM equipment that prior art reduces leakage current.
Embodiment
Accompanying drawing 1 is according to one embodiment of the invention low-power consumption SRAM cells 100.Wherein 101 is power lead, and 102 is ground wire, and 103 is wordline, 104 is bit line, 105 is paratope line, and 106 is a NMOS transfer tube, and 107 is another NMOS transfer tube, 108 is a PMOS load pipe, 109 is another PMOS load pipe, and 110 is a NMOS driving tube, and 111 is another NMOS driving tube, 112 is memory node, and 113 is complementary storage node.The drain terminal of the one NMOS transfer tube 106, grid end, source are connected with bit line 104, wordline 103, memory node 112 respectively; The drain terminal of the 2nd NMOS transfer tube, grid end, source are connected with paratope line 105, wordline 103, complementary storage node 113 respectively; The drain terminal of the one PMOS load pipe, grid end, source are connected with memory node 112, complementary storage node 113, power lead 101 respectively; The drain terminal of the 2nd PMOS load pipe, grid end, source are connected with complementary storage node 113, memory node 112, power lead 101 respectively; The drain terminal of the one NMOS driving tube, grid end, source are connected with memory node 112, complementary storage node 113, ground wire 104 respectively; The drain terminal of the 2nd NMOS driving tube, grid end, source are connected with complementary storage node 113, memory node 112, ground wire 104 respectively.
Accompanying drawing 2 is the static memory SRAM system 200 reducing leakage current according to one embodiment of the invention.The element identical with in accompanying drawing 1 employs identical Reference numeral, does not repeat one by one at this.Wherein, 210 is SRAM memory cell array, and 201 is read/write circuit (SA & WD), and 202 is ECC error detection/correction circuit, and 203 is voltage regulator, and 204 is bias tubes, and 220 is extraneous power lead, and 230 is ground wire.ECC error detection/correction circuit 202 is connected with read/write circuit 201, and is connected with voltage regulator 203, and voltage regulator 203 is connected with bias tube 204.Bias tube 204 is connected with the power lead of memory cell array 210, is connected with extraneous power lead simultaneously.The ground wire of memory cell array 210 is connected with extraneous ground wire.
When supposing that memory cell array supply voltage 101 is reduced to V0, the value of all unit all can not change, and it is Δ V that voltage regulator controls each amplitude reducing array power supply voltage of bias tube 204.When certain array of SRAM enters standby, in order to make the supply voltage 101 of array element be reduced at utmost, realizing both having reduced array electric leakage, not affecting storage stability again.Specific implementation is as follows:
(1) voltage regulator 203 controls bias tube 204 and the supply voltage 101 of array element is reduced to V0.
(2) supply voltage 101 returns to active pattern, read/write circuit 201 reads the content of unit in array, then read content is sent into ECC error detection/correction circuit 202, if make mistakes, adopt ECC error correction, and the value after correcting is write back array 210 by read/write circuit 201, forward (4) step to; If do not make mistakes, forward (3) step to.
(3) adopt voltage regulator 203 to control bias tube 204 and the supply voltage 101 of array element is reduced to Δ V less of the front value once reduced, forward (2) step to.
(4) supply voltage 101 of array element is increased Δ V, array enters standby pattern.
By above-mentioned steps, minimum or close to minimum supply voltage when the array that can detect is in standby pattern, and then make the electric leakage of array little as far as possible, realize extremely low power dissipation.It should be noted that the value of Δ V is less, finally obtain supply voltage under standby pattern more close to minimum value.
Accompanying drawing 3 is the static memory SRAM system reducing leakage current according to a further embodiment of the invention.The element identical with in accompanying drawing 1 employs identical Reference numeral, does not repeat one by one at this.Wherein, 210 is SRAM memory cell array, and 201 is read/write circuit (SA & WD), and 202 is ECC error detection/correction circuit, and 203 is voltage regulator, and 304 is bias tubes, and 220 is extraneous power lead, and 230 is ground wire.ECC error detection/correction circuit 202 is connected with read/write circuit 201, and is connected with voltage regulator 203, and voltage regulator 203 is connected with bias tube 204.Bias tube 304 is connected with the ground wire of memory cell array 210, is connected with extraneous ground wire simultaneously.The power lead of memory cell array 210 is connected with extraneous power lead.
When supposing that voltage is lifted to V1 in array, the value of all unit all can not change, and it is Δ V that voltage regulator 202 controls the amplitude that bias tube 203 raises voltage 102 in array at every turn.When certain array of SRAM enters standby, in order to make ground voltage 102 be lifted at utmost, realizing both having reduced array electric leakage, not affecting storage stability again.Specific implementation is as follows:
(1) voltage regulator 203 controls bias tube 304 and the ground voltage 102 of memory cell array is lifted to V1.
(2) ground voltage 101 returns to active pattern, read/write circuit 201 reads the content of unit in array, then read content is sent into ECC error detection/correction circuit 202, if make mistakes, adopt ECC error correction, and the value after correcting is write back array 210 by read/write circuit 201, forward (4) step to; If do not make mistakes, forward (3) step to.
(3) adopt voltage regulator 203 to control bias tube 204 and the ground voltage 102 of array element is lifted to Δ V larger than the front value once raised, forward (2) step to.
(4) ground voltage 102 of array element is reduced Δ V, array enters standby pattern.
By above-mentioned steps, storage unit the highest or close to the highest ground voltage when the array that can detect is in standby pattern, and then make the electric leakage of array little as far as possible, realize extremely low power dissipation.It should be noted that the value of Δ V is less, finally obtain ground voltage under standby pattern more close to maximal value.
Although illustrate and describe the preferred embodiments of the present invention, it will be apparent for a person skilled in the art that and can make a lot of change and amendment without departing from the invention in it is wider.
Claims (10)
1. reduce a method for static memory SRAM leakage current, it is characterized in that,
Described static memory SRAM comprises: read/write circuit, ECC error detection/correction circuit, voltage regulator, bias tube and memory cell array; Voltage regulator controls the supply voltage that bias tube reduces or increases memory cell array; Read/write circuit is used for returning to active pattern, reading cells array content when supply voltage, and content is sent to ECC error detection/correction circuit, in addition, and the value write storage unit array that ECC also can correct by read/write circuit; ECC error detection/correction circuit, for error-detection error-correction, and writes back memory cell array by the value after correcting by read/write circuit;
Said method comprising the steps of:
(1) voltage regulator controls bias tube and the supply voltage of array element is reduced to V0;
(2) supply voltage returns to active pattern, and read/write circuit reads the content of unit in array, then read content is fed through ECC error detection/correction circuit, if make mistakes, adopt ECC error correction, and the value after correcting is write back array, forward (4) step to; If do not make mistakes, forward (3) step to;
(3) adopt voltage regulator to control bias tube and the supply voltage of array element is reduced to Δ V less of the front value once reduced, forward (2) step to;
(4) supply voltage of array element is increased Δ V, array enters standby pattern.
2. the method reducing static memory SRAM leakage current as claimed in claim 1, it is characterized in that, ECC error detection/correction circuit is connected with read/write circuit, and is connected with voltage regulator.
3. the method reducing static memory SRAM leakage current as claimed in claim 1, it is characterized in that, voltage regulator is connected with bias tube, and bias tube is connected with the power lead of memory cell array.
4. the method reducing static memory SRAM leakage current as claimed in claim 1, it is characterized in that, the storage unit in memory cell array comprises power lead, ground wire, wordline, bit line and paratope line.
5. the method reducing static memory SRAM leakage current as claimed in claim 1, it is characterized in that, read/write circuit is connected with paratope line with the bit line in memory cell array.
6. reduce a method for static memory SRAM leakage current, it is characterized in that,
Described static memory SRAM comprises: read/write circuit, ECC error detection/correction circuit, voltage regulator, bias tube and memory cell array; Voltage regulator controls the ground voltage that bias tube raises or reduces memory cell array; Read/write circuit, for local voltage resume to active pattern, reading cells array content, and content is sent to ECC error detection/correction circuit, and in addition, the value write storage unit array that ECC also can correct by read/write circuit; ECC error detection/correction circuit, for error-detection error-correction, and writes back memory cell array by the value after correcting by read/write circuit;
Said method comprising the steps of:
(1) voltage regulator controls bias tube and the ground voltage of memory cell array is lifted to V1;
(2) ground voltage returns to active pattern, and read/write circuit reads the content of unit in array, then read content is sent into ECC error detection/correction circuit, if make mistakes, adopts ECC error correction, and the value after correcting is write back array, forwards (4) step to; If do not make mistakes, forward (3) step to;
(3) adopt voltage regulator to control bias tube and the ground voltage of array element is lifted to Δ V larger than the front value once raised, forward (2) step to;
(4) ground voltage of array element is reduced Δ V, array enters standby pattern.
7. the method reducing static memory SRAM leakage current as claimed in claim 6, it is characterized in that, ECC error detection/correction circuit is connected with read/write circuit, and is connected with voltage regulator.
8. the method reducing static memory SRAM leakage current as claimed in claim 6, it is characterized in that, voltage regulator is connected with bias tube, and bias tube is connected with memory cell array ground wire.
9. the method reducing static memory SRAM leakage current as claimed in claim 6, it is characterized in that, the storage unit in memory cell array comprises power lead, ground wire, wordline, bit line and paratope line.
10. the method reducing static memory SRAM leakage current as claimed in claim 6, it is characterized in that, read/write circuit is connected with paratope line with the bit line in memory cell array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110188458.0A CN102867541B (en) | 2011-07-05 | 2011-07-05 | Low-power consumption static memory SRAM |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110188458.0A CN102867541B (en) | 2011-07-05 | 2011-07-05 | Low-power consumption static memory SRAM |
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| CN102867541A CN102867541A (en) | 2013-01-09 |
| CN102867541B true CN102867541B (en) | 2016-03-30 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103824590B (en) * | 2014-03-09 | 2017-02-01 | 北京工业大学 | Design for three-state ten-transistor SRAM cell circuit |
| US9846612B2 (en) | 2015-08-11 | 2017-12-19 | Qualcomm Incorporated | Systems and methods of memory bit flip identification for debugging and power management |
| US10269418B2 (en) | 2015-12-28 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Write assist circuit of memory device |
| CN108922573B (en) * | 2018-05-30 | 2020-10-02 | 上海华力集成电路制造有限公司 | Word line bias generator and method for SRAM |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404065A (en) * | 2001-08-31 | 2003-03-19 | 三菱电机株式会社 | Storage circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6560139B2 (en) * | 2001-03-05 | 2003-05-06 | Intel Corporation | Low leakage current SRAM array |
| US6970374B2 (en) * | 2004-02-24 | 2005-11-29 | United Microelectronics Corp. | Low leakage current static random access memory |
| US7269055B2 (en) * | 2006-02-13 | 2007-09-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM device with reduced leakage current |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404065A (en) * | 2001-08-31 | 2003-03-19 | 三菱电机株式会社 | Storage circuit |
Non-Patent Citations (2)
| Title |
|---|
| 45nm Low-Power Embedded Pseudo-SRAM with ECC-Based Auto-Adjusted Self-Refresh Scheme;Suk-Soo PYO等;《IEEE International Symposium on Circuits and Systems 2009.ISCAS 2009 》;20090527;第2517-2520页 * |
| Leakage Reduction of Sub-55nm SRAM Based on a Feedback Monitor Scheme for Standby Voltage Scaling;Chen Wu等;《2010 International SoC Design Conference (ISOCC)》;20101123;第315-318页 * |
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