CN204680387U - A kind of RRAM subarray structure comprising reference unit - Google Patents

Abstract

A kind of RRAM subarray structure comprising reference unit of the utility model, comprise main array and referential array, main array comprises the capable m array storage unit of n; Referential array comprises capable 2 array storage units of n; Main array is connected by the wordline arranged by row successively with the storage unit in referential array; In main array, any 1 row comprise main array bitline BL and main array source line SL, and are connected in parallel on n storage unit between main array bitline BL and main array source line SL successively; In referential array, any 1 row all can as reference unit; Often row reference unit comprises n storage unit altogether, is composed in series by two-stage n/2 storage unit parallel-connection structure; Often row reference unit comprises the first bit line RBLH, a second bit line RBLL and source line CSL, and two row reference units share source line CSL; First bit line and the second bit line are respectively connected n/2 storage unit, and two-stage n/2 storage unit parallel-connection structure is connected by CSL.

Description

A kind of RRAM subarray structure comprising reference unit

Technical field

The utility model relates to non-volatile random access memory design field, is specially a kind of RRAM subarray structure comprising reference unit.

Background technology

In recent years under the consumer market traction such as smart mobile phone, intelligent television and panel computer, flash storer was developed rapidly.But, due to the mask graph of complexity and the manufacturing cost of costliness, the crosstalk between increasing word line leakage and unit, and the reason such as in floating boom number of electrons is fewer and feweri, its size reduces ability and is greatly limited, and estimates that developing into 1znm down develops very difficult continuation.Therefore, emerging nonvolatile memory CBRAM, MRAM, PRAM, RRAM etc. more and more come into one's own, and wherein RRAM relies on high speed, Large Copacity, low-power consumption, low cost and high reliability to be considered to the strongest candidate of flash.

But, due to the impact of process voltage temperature (PVT), shown in Fig. 1, there is serious consistency problem in RRAM resistive element resistance sizes, between wafer and wafer, with between circle chip and chip, on same chip, zones of different all also exists the deviation of resistance sizes.No matter be high-impedance state or low resistance state, resistance sizes is all the normal distribution of certain limit.Therefore, for the reading circuit based on current-mode, be just difficult to provide the reference current that more satisfactory.Adopt fixed reference electric current unlikely, because it cannot follow the tracks of resistive element high-impedance state and low resistance state because the deviation brought of region and temperature.At present conventional method adopts the reference unit shared to provide reference current, as shown in Figure 2, can follow the tracks of the change of resistance along with region and temperature.But the resistance sizes of reference unit own also exists consistency problem, its reference current produced is also in normal distribution, so suitable referential array structure must be found, constriction reference current distributes, and improves read margin, thus provides reading speed and read success ratio.

Utility model content

For problems of the prior art, the utility model provides a kind of by providing self-adaptation to read reference current, and then increases read margin, improves the RRAM subarray structure comprising reference unit of reading speed and success ratio.

The utility model is achieved through the following technical solutions:

A kind of sub-memory array structure of RRAM comprising reference unit of the utility model, comprise main array and referential array, main array comprises the capable m array storage unit of n; Referential array comprises capable 2 array storage units of n, and wherein, n is positive integer, and m is positive integer; Main array is connected by the wordline arranged by row successively with the storage unit in referential array;

In main array, any 1 row comprise main array bitline BL and main array source line SL, and are connected in parallel on n storage unit between main array bitline BL and main array source line SL successively;

In referential array, any 1 row all can as reference unit; Often row reference unit comprises n storage unit altogether, is composed in series by two-stage n/2 storage unit parallel-connection structure; Often row reference unit comprises the first bit line RBLH, a second bit line RBLL and source line CSL, and two row reference units share source line CSL; First bit line RBLH is respectively connected n/2 storage unit with the second bit line RBLL, and two-stage n/2 storage unit parallel-connection structure is connected by CSL; During reading, the first bit line RBLH connects and reads voltage Vread, the second bit line RBLL ground wire GND.

Preferably, also comprise with reference to read switch RD_RER_SW<n-1:0>, and be arranged on the reference write switch WR_RER_SW<n-1:0> between main array and referential array in wordline; Three ends with reference to read switch RD_RER_SW<n-1:0> connect referential array row wordline respectively, and referential array reads word line voltage RD_RER_WL and enable signal RD_RER_EN is read in reference; The three end distributions of write switch WR_RER_SW<n-1:0> connect main array word line, referential array wordline and reference write-enable signal WR_REF_EN.

Further, when writing reference unit,

WR_RER_EN is effective, WR_RER_SW<n-1:0> opens, RD_RER_EN is invalid, RD_RER_SW<n-1:0> closes and RD_RER_WL meets GND, corresponding referential array wordline REF_WL<i> is selected to write by WL<i>, wherein, 0≤i≤n-1, n is positive integer.

Further, when reference unit is as reading reference,

WR_RER_EN is invalid, WR_RER_SW<n-1:0> closes, RD_RER_EN is effective, RD_RER_SW<n-1:0> opens and RD_RER_WL meets chip power VDD, REF_WL<n-1:0> all opens, and n reference unit forms two-stage n/2 unit structure of connecting again in parallel.

Preferably, before reading data, the storage unit in referential array is all written as low resistance state.

Compared with prior art, the utility model has following useful technique effect:

The utility model proposes a kind of RRAM subarray structure comprising reference unit, realized and string structure by every row reference unit, the optimization of parallel units number and series connection progression is utilized to limit, while saving area and simplification steering logic, self-adaptation can be provided to read reference current, thus improve reading speed and success ratio.By arranging the reference unit of two row common source lines in referential array, realizing redundancy scheme, ensure that the recoverability reading reference current.

Further, by the control of two groups of switches and corresponding control signal, can carry out read-write operation quickly and accurately to the unit in reference unit, and form referential array, structure is ingenious, and logic control is simple and convenient.

Further, reference unit all selects low resistance state unit, and constriction reference current distribution greatly, increases read margin, better improves reading speed and reads success ratio.

Accompanying drawing explanation

Fig. 1 is the RRAM memory cell structure figure of 1T1R structure in prior art.

Fig. 2 is the storage array comprising reference unit based on 1T1R storage unit in prior art.

Fig. 3 is a sub-storage array described in the utility model example.

Fig. 4 is the referential array structure of sub-storage array described in the utility model example.

Fig. 5 is the reading schematic diagram of the current mode sense amplifier based on the utility model referential array structure.

Embodiment

Below in conjunction with specific embodiment, the utility model is described in further detail, described in be to explanation of the present utility model instead of restriction.

The utility model provides a kind of sub-memory array structure of RRAM comprising reference unit, and as shown in Figure 3, it comprises main array and referential array, and main array comprises 32x128 (32 row, 128 row) storage unit.Referential array comprises 32x2 (n is capable, 2 row) storage unit, optionally wherein 1 arranges as reference unit.

Often row reference unit adopts storage unit and string structure, comprises 32 storage unit altogether, is composed in series by two-stage 16 storage unit parallel-connection structures.Often row reference unit comprises two bit lines, is respectively the first bit line RBLH, a second bit line RBLL and source line CSL, and two row reference units share source line CSL.RBLH with RBLL is respectively connected 16 storage unit, and during reading, RBLH connects and reads voltage Vread, and RBLL ground wire GND, two-stage 16 storage unit parallel-connection structures are connected by CSL.

This referential array comprises with reference to write switch WR_RER_SW<31:0> with reference to read switch RD_RER_SW<31:0>, with reference to write-enable signal WR_RER_EN, with reference to reading enable signal RD_RER_EN, with reference to reading word line voltage RD_RER_WL.When reference unit is write, WR_RER_EN is effective, WR_RER_SW<31:0> opens, RD_RER_EN is invalid, RD_RER_SW<31:0> closes and RD_RER_WL meets GND, selects REF_WL<i> (0≤i≤31) to write by WL<i> (0≤i≤n31); When reference unit is as reading reference, WR_RER_EN is invalid, WR_RER_SW<31:0> closes, RD_RER_EN is effective, RD_RER_SW<31:0> opens and RD_RER_WL meets VDD, REF_WL<3:0> all opens, and in reference unit, 32 storage unit form two-stage 16 storage unit structure of connecting again in parallel, as shown in Figure 4.

When sub-memory array structure described in the utility model is applied to the sense amplifier of current-mode, as shown in Figure 5, when referential array reads, RBLH connects and reads voltage Vread, and RBLL ground wire GND, Iref are 8I _l, become (I through current buffer CB _h+ I _l)/2, send into current mode sense amplifier CSA reference arm, and object element electric current I cell compare, if Icell is greater than (I _h+ I _l)/2, dout are " 1 ", otherwise dout is " 0 ".

Claims (5)

1. comprise the sub-memory array structure of RRAM of reference unit, it is characterized in that, comprise main array and referential array, main array comprises the capable m array storage unit of n; Referential array comprises capable 2 array storage units of n, and wherein, n is positive integer, and m is positive integer; Main array is connected by the wordline arranged by row successively with the storage unit in referential array;

In main array, any 1 row comprise main array bitline BL and main array source line SL, and are connected in parallel on n storage unit between main array bitline BL and main array source line SL successively;

In referential array, any 1 row all can as reference unit; Often row reference unit comprises n storage unit altogether, is composed in series by two-stage n/2 storage unit parallel-connection structure; Often row reference unit comprises the first bit line RBLH, a second bit line RBLL and source line CSL, and two row reference units share source line CSL; First bit line RBLH is respectively connected n/2 storage unit with the second bit line RBLL, and two-stage n/2 storage unit parallel-connection structure is connected by CSL; During reading, the first bit line RBLH connects and reads voltage Vread, the second bit line RBLL ground wire GND.

2. a kind of sub-memory array structure of RRAM comprising reference unit according to claim 1, it is characterized in that, also comprise with reference to read switch RD_RER_SW<n-1:0>, and be arranged on the reference write switch WR_RER_SW<n-1:0> between main array and referential array in wordline; Three ends with reference to read switch RD_RER_SW<n-1:0> connect referential array row wordline respectively, and referential array reads word line voltage RD_RER_WL and enable signal RD_RER_EN is read in reference; The three end distributions of write switch WR_RER_SW<n-1:0> connect main array word line, referential array wordline and reference write-enable signal WR_REF_EN.

3. a kind of sub-memory array structure of RRAM comprising reference unit according to claim 2, is characterized in that, when writing reference unit,

WR_RER_EN is effective, WR_RER_SW<n-1:0> opens, RD_RER_EN is invalid, RD_RER_SW<n-1:0> closes and RD_RER_WL meets GND, corresponding referential array wordline REF_WL<i> is selected to write by WL<i>, wherein, 0≤i≤n-1, n is positive integer.

4. a kind of sub-memory array structure of RRAM comprising reference unit according to claim 2, is characterized in that, when reference unit is as reading reference,

WR_RER_EN is invalid, WR_RER_SW<n-1:0> closes, RD_RER_EN is effective, RD_RER_SW<n-1:0> opens and RD_RER_WL meets chip power VDD, REF_WL<n-1:0> all opens, and n reference unit forms two-stage n/2 unit structure of connecting again in parallel.

5. a kind of sub-memory array structure of RRAM comprising reference unit according to claim 1, is characterized in that, before reading data, the storage unit in referential array is all written as low resistance state.