CN101276638B - Semiconductor memory device using ferroelectric device and method for refresh thereof - Google Patents

Abstract

A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region depending on a polarity state of the ferroelectric layer, a data read operation is performed by a cell sensing current value differentiated depending on the polarity state of the ferroelectric layer while a read voltage is applied to the word line and a sensing bias voltage is applied to one of the drain region and the source region, and a data write operation is performed by a polarity of the ferroelectric layer changed depending on a voltage applied to the word line, the drain region and the source region.

Description

Semiconductor memory and update method thereof with ferro-electric device

Technical field

The embodiment consistent with the present invention relates in general to semiconductor memory and the update method thereof with ferro-electric device; And more precisely, relate to the technology that transistor-field effect transistor (1T-FET) type ferroelectric memory cell with non-volatile nature is applied to dynamic RAM (DRAM).

Background technology

Usually, in order in DRAM, to store data, power supply should be provided continuously as volatile memory.When moment during power cutoff, possibly destroy the data of RAM, because the memory cell of DRAM designs based on the little charged electronics that is used for the stored charge power supply.If these charged electronics do not recharge continuously, the power of the charging before that can be destroyed.

Upgrading operation refers to such an extent that be the technology that recharges of memory chip unit.Upgrade in the circulation at each, can be to row's memory cell charging.Though the renewal operation is carried out in the storage control through system, design several chips and carry out the self refresh operation.

For example, DRAM has the self refresh control circuit so that under the situation that does not have CPU (CPU) or outside refresh circuit, carry out the self refresh operation.The self refresh method that is used to reduce power consumption has been used for portable computer.

Traditional DRAM often carries out and upgrades operation because DRAM be volatibility and have a short renewal circulation.As a result, frequent renewal operation has increased power consumption and has reduced performance.

Usually, ferroelectric RAM (FeRAM) has caused considerable concern as memory device of future generation, even because it has data processing speed fast as DRAM and after power cutoff, still can store data.

FeRAM with the structure that is similar to DRAM can comprise the capacitor of being processed by ferroelectric, so that it utilizes the high residual polarization characteristic of ferroelectric, wherein, even data still can not deleted after removing electric field.

One-transistor 1-capacitor (1T1C) type unit of traditional FeRAM comprise be configured to according to the state of word line carry out switching manipulation and with bit line be connected to the on-off element of Nonvolatile ferroelectric capacitor and be connected grid line and an end of on-off element between the Nonvolatile ferroelectric capacitor.On-off element is the nmos pass transistor through its switching manipulation of gate control signal control.

Summary of the invention

According to the present invention; Semiconductor memory with ferro-electric device is provided; This storage component part comprises; 1-TFET type memory cell, many even bitlines of arranging perpendicular to many word lines and perpendicular to many word lines and many odd bit lines of alternately arranging with many even bitlines; Wherein memory cell is connected between a pair of adjacent idol/odd bit lines of many even bitlines and many odd bit lines, and the polarity of the ferroelectric layer that is configured to change through the voltage according to word line and this paired idol/odd bit lines reads the data stream of memory cell and through storing 2n-bit data (n is a natural number) according to a plurality of polarity of writing voltage change ferroelectric layer that put on word line and this paired idol/odd bit lines.

According to the present invention; The update method of the semiconductor memory with ferro-electric device is provided; Multiple bit lines and one-transistor (1-T) field effect transistor (FET) type memory cell that this storage component part comprises many word lines arranging by line direction, arranges perpendicular to many word lines; This memory cell comprises the channel region, drain region and the source region that are formed in the substrate, be formed on the ferroelectric layer of channel region top and be formed on the word line of ferroelectric layer top; Wherein the polarization state of ferroelectric layer is according to putting on word line and the change in voltage that is connected to the pair of bit lines of memory cell; This method comprises that channel region that different channel resistances is guided to 1T-FET type memory cell with read/write data with the data of specific renewal cycle and regeneration of mature memory cell, is stored in the retention performance of the data in the memory cell with improvement.

According to the present invention; Semiconductor memory with ferro-electric device is provided; This storage component part comprises one-transistor (1-T) field effect transistor (FET) type memory cell; This memory cell comprises the channel region, drain region and the source region that are formed in the substrate, be formed on the ferroelectric layer of channel region top and be formed on the word line of ferroelectric layer top, wherein according to the polarization state of ferroelectric layer different channel resistances guided to channel region; Many word lines in the line direction arrangement; Multiple bit lines perpendicular to many word lines arrangements; Carry out the renewal control module that upgrades operation with the renewal circulation that is configured to specific; Be stored in the retention performance of the data in the memory cell with improvement, wherein memory cell is connected between a pair of adjacent bit lines of multiple bit lines and is configured to and comes read/write data through changing ferroelectric layer polarity according to the voltage that puts on word line and paired bit line.

According to the present invention; Semiconductor memory with ferro-electric device is provided; This semiconductor memory comprises one-transistor (1-T) field effect transistor (FET) type memory cell, and this memory cell comprises channel region, drain region and the source region that forms in the substrate; Be formed on the ferroelectric layer of channel region top; With the word line that is formed on the ferroelectric layer top; Wherein different channel resistances is introduced channel region, and wherein this ferro-electric device comprises according to the polarization state of ferroelectric layer: many word lines arranging on the line direction and the multiple bit lines of arranging perpendicular to many word lines and wherein memory cell be connected between a pair of adjacent bit lines of multiple bit lines and be configured to and come read/write data through the polarity that changes ferroelectric layer according to the voltage that puts on word line and paired bit line.

According to the present invention; Semiconductor memory with ferro-electric device is provided; This storage component part comprises: be formed on channel region, drain region and source region in the substrate, be formed on the ferroelectric layer of channel region top and be formed on the word line of ferroelectric layer top; Wherein carry out data read operation through the unit read current value of distinguishing according to the polarization state of ferroelectric layer; And different channel resistances is guided to channel region according to the polarization state of ferroelectric layer, read voltage and put on word line and read bias voltage and put on one of drain region and source region, and carry out data write operation with the polarity that changes ferroelectric layer through apply voltage to word line, drain region and source region.

Description of drawings

Fig. 1 is the sectional view that semiconductor memory is shown.

Fig. 2 a and 2b are the curve maps of bit line current that the read mode of semiconductor memory is shown.

Fig. 3 is the sequential chart that operation write cycle of semiconductor memory is shown.

Fig. 4 is the sequential chart that the renewal cycling of semiconductor memory is shown.

Fig. 5 is the sectional view that illustrates according to semiconductor memory of the present invention.

Fig. 6 is the curve map that illustrates according to the data retention characteristics of semiconductor memory of the present invention.

Fig. 7 is the planimetric map that illustrates according to the cell array of semiconductor memory of the present invention.

Fig. 8 illustrates according to the cell array structure of semiconductor memory of the present invention and the figure of read operation.

Fig. 9 illustrates according to the cell array structure of semiconductor memory of the present invention and the figure of data ' 0 ' write operation.

Figure 10 illustrates according to the cell array structure of semiconductor memory of the present invention and the figure of data ' 1 ' write operation.

Figure 11 is the sequential chart that illustrates according to the read operation of semiconductor memory of the present invention.

Figure 12 is the sequential chart that illustrates according to the write operation of semiconductor memory of the present invention.

Figure 13 is the figure that illustrates according to the cell array of semiconductor memory of the present invention.

Figure 14 is the figure that cell array structure according to semiconductor memory of the present invention is shown, writes driver element, sensor amplifier and register.

Figure 15 is the circuit diagram that illustrates according to the line decoder of semiconductor memory of the present invention.

Figure 16 is the oscillogram that illustrates according to the operation of the line decoder of Figure 15 of the present invention.

Figure 17 is the circuit diagram that writes driver element and sensor amplifier that illustrates according to Figure 14 of the present invention.

Figure 18 is the oscillogram that writes driver element and sensor amplifier that illustrates according to Figure 17 of the present invention.

Figure 19 is the figure that illustrates according to semiconductor memory of the present invention.

Figure 20 is the figure that the data ' 00 ' write operation according to semiconductor memory of the present invention is shown.

Figure 21 is the figure that the data ' 01 ' write operation according to semiconductor memory of the present invention is shown.

Figure 22 is the figure that the data ' 01 ' write operation according to semiconductor memory of the present invention is shown.

Figure 23 is the figure that the data ' 11 ' write operation according to semiconductor memory of the present invention is shown.

Figure 24 is the figure according to the read operation of the left bit data of semiconductor memory of the present invention.

Figure 25 is the figure according to the read operation of the right bit data of semiconductor memory of the present invention.

Figure 26 is the sequential chart that illustrates according to the write cycle of semiconductor memory of the present invention.

Figure 27 is the renewal round-robin sequential chart that illustrates according to semiconductor memory of the present invention.

Figure 28 is the planimetric map that illustrates according to the cell array of semiconductor memory of the present invention.

Figure 29 illustrates according to the cell array structure of semiconductor memory of the present invention and the figure of R-bit data read operation.

Figure 30 is the figure that illustrates according to the left bit data read operation of semiconductor memory of the present invention.

Figure 31 is the figure that illustrates according to data ' 0000... ' write operation of semiconductor memory of the present invention.

Figure 32 is the figure that illustrates according to data ' 0101... ' write operation of semiconductor memory of the present invention.

Figure 33 is the figure that illustrates according to data ' 1010... ' write operation of semiconductor memory of the present invention.

Figure 34 is the figure that illustrates according to data ' 1111... ' write operation of semiconductor memory of the present invention.

Figure 35 is the sequential chart that illustrates according to the read operation of semiconductor memory of the present invention.

Figure 36 is the sequential chart that illustrates according to the write operation of semiconductor memory of the present invention.

Figure 37 is the figure that illustrates according to the cell array of semiconductor memory of the present invention.

Figure 38 is the figure that illustrates according to semiconductor memory of the present invention.

Figure 39 is the figure that writes level that illustrates according to the n-bit memory cell of semiconductor memory of the present invention.

Figure 40 is the figure that illustrates according to the read current level of the n-bit memory cell of semiconductor memory of the present invention.

Figure 41 is the figure that illustrates according to the low data write operation of semiconductor memory of the present invention.

Figure 42 is the figure that illustrates according to the 2n-position write operation of semiconductor memory of the present invention.

Figure 43 is the sequential chart that illustrates according to operation write cycle of semiconductor memory of the present invention.

Figure 44 is the planimetric map that illustrates according to the cell array of semiconductor memory of the present invention.

Figure 45 illustrates according to the cell array structure of semiconductor memory of the present invention and the figure of right n bit data read operation.

Figure 46 illustrates according to the cell array structure of semiconductor memory of the present invention and the figure of left n bit data read operation.

Figure 47 is the figure that illustrates according to the low data write operation of semiconductor memory of the present invention.

Figure 48 is the figure that illustrates according to the 2n-bit data write operation of semiconductor memory of the present invention.

Figure 49 illustrates according to the electric current sense amplifier array of semiconductor memory of the present invention and the figure of reference unit.

Figure 50 is the circuit diagram that illustrates according to the sensor amplifier of Figure 49 of the present invention.

Figure 51 is the sequential chart that illustrates according to the read operation of semiconductor memory of the present invention.

Figure 52 is the sequential chart that illustrates according to the write operation of semiconductor memory of the present invention.

Figure 53 is the figure that illustrates according to the cell array of semiconductor memory of the present invention.

Embodiment

Fig. 1 is the sectional view that semiconductor memory is shown.

One-transistor (1-T) field effect transistor (FET) type ferroelectric memory cell comprises p-type channel region, N type drain region 2 and the N type source region 3 that is formed in the P-type district substrate 1.Ferroelectric layer 4 is formed on the channel region top, and word line 5 is formed on ferroelectric layer 4 tops.

For stablizing of technology, buffer insulation layer 6 can be formed between channel region and the ferroelectric layer 4.That is to say, form buffer insulation layer 6 to eliminate technology and the materials variances between channel region and ferroelectric layer 4.

Data are read and write to the semiconductor memory response according to the channel resistance of the memory cell that the polarization state of ferroelectric layer 4 is distinguished.

When the polarity of ferroelectric layer 4 caused that positive charge gets into raceway groove, memory cell can become the high resistance channel state of ending.On the other hand, when the polarity of ferroelectric layer 4 caused that negative charge gets into raceway groove, memory cell can become the low resistance state of conducting.Thereby ferroelectric storage unit can select the polarity of ferroelectric layer 4 in this unit write data, and it is non-volatile to make memory cell become.

Fig. 2 a and 2b are the curve maps that illustrates according to the bit line current of the read mode of semiconductor memory of the present invention.

Shown in Fig. 2 a, magnitude of voltage is set at word line read voltage Vrd when P-type channel region conduction and cut-off.Adopt word line read voltage Vrd, when the channel region conducting, the bit line BL electric current of maximum flows, and when channel region by the time, minimum bit line BL electric current is mobile.

Shown in Fig. 2 b, when the voltage that changes bit line BL and when applying identical word line read voltage Vrd, memory cell has different bit line BL current values according to the value that is stored in the cell data in the memory cell.That is to say that when data " 0 " when being stored in memory cell, a large amount of bit line BL electric currents flow along with the increase of bit line BL voltage.When data " 1 " when being stored in memory cell, although bit line BL electric current does not change and the increase of bit line BL voltage still can be flowed on a small quantity.

Fig. 3 is the sequential chart that operation write cycle of semiconductor memory according to an embodiment of the invention is shown.

In cycle t0, cell data is read and is exaggerated in whole unit of selected row address, and is stored in the register.In cycle t1,, therefore do not know which data storage is in the existing memory unit because data " 0 " write in whole memory cells.As a result, in order to know which data storage in the existing memory unit, before data " 0 " write store unit, data " 0 " are stored in the register.

In cycle t1, data " 0 " can be written in whole unit of selected row address.In cycle t2, the data that are stored in the register can write and be stored in the memory cell more again, and new external data can writing unit in.In cycle t2, because data " 0 " perhaps write new data " 1 " so write data " 0 " at cycle t1 before and be stored in the unit.

Fig. 4 is the sequential chart that illustrates according to the renewal cycling of semiconductor memory of the present invention.

In cycle t0, in whole unit of selected row address, can read and the amplifying unit data, and be stored in the register.In cycle t1, execution renewal " 0 " is operated in the corresponding unit with the row address that data " 0 " is stored in again selection.In cycle t2, execution renewal " 1 " is operated in the corresponding unit with the row address that data " 1 " is stored in again selection.

Fig. 5 is the figure that illustrates according to semiconductor memory of the present invention.

Semiconductor memory comprises weld pad array 100, renewal control module 110, row address register 120, row sequential logic 130, line decoder 140, cell array 150, read/write control module 160, column decoder 170, column address register 180, row sequential logic 190, update mode information register 200, sensor amplifier, register, write driver 210, I/O logic 220, I/O register 230, I/O impact damper 240 and I/O pin two 50.

Upgrade control module 110 and comprise update controller 111 and refresh counter 112.Cell array 150 can comprise the 1T-FET type unit of a plurality of Fig. 1.

Weld pad array 100 comprises a plurality of weld pad PAD, and each weld pad is configured to receive row address and column address so that along with the time changes OPADD.Update controller 111 is exported update signal REF and is used to respond ras signal/RAS, cas signal/CAS, read/write instruction R, and/W controls with the renewal control signal and upgrades the renewal enable signal REF_EN that operates.

Update signal REF that refresh counter 112 response applies from update controller 111 and the renewal control signal count update circulation that applies from update mode information register 200 are with output counting address CA.Update controller 111 will be upgraded operation information with refresh counter 112 and export in the update mode information register 200 with the renewal count information.

Row address register 120 receives row address and the interim memory address that comes from weld pad array element 100.The output signal of row address register 120 responsive trip sequential logics 130 and row address RADD is outputed to line decoder 140 from the read RWCON that read/write control module 160 applies.

Row sequential logic 130 response ras signal/RAS control the storage operation and the address output timing of row address register 120.The row address RADD that line decoder 140 decoding applies from row address register 120 is to output to the address cell array 150.

The read RWCON that read/write control module 160 response ras signal/RAS, cas signal/CAS and read/write instruction R ,/W will be used to control read/write operation outputs to row address register 120 so that control column decoder 170 and sensor amplifier, register and write driver 210.

Column decoder 170 is according to the control of read/write control module 160, and the column address that decoding applies from column address register 180 is to output to I/O logic 220 with this address.The column address that the interim storage of column address register 180 receives from weld pad array 100 is so that export this address to column decoder 170 according to the control of row sequential logic 190.

The storage operation and the address output timing of row sequential logic 190 response cas signals/CAS control column address register 180.When activating update signal REF, register 210 will Update Information according to the control of row sequential logic 190 and export memory cell to.

Lastest imformation register 200 is the non-volatile registers that are configured to store the parameter relevant with upgrading operation.Shutdown timing information and other parameter informations of lastest imformation register 200 storage update count informations, system or internal storage.

In upgrading operation, update mode information register 200 is based on parameter information output renewal control information.Shutting down sequential, the information of upgrading control module 111 and refresh counter 112 is sent to update mode information register 200, and storage and the relevant information of external command that receives from I/O impact damper 240.The information that is stored in the update mode information register 200 through I/O impact damper 240 and I/O pin two 50 exports system controller 300 to.

Sensor amplifier S/A read and the amplifying unit data to distinguish data " 1 " and data " 0 ".When the writing data into memory unit, write driver W/D response writes data and produces driving voltage so that driving voltage is provided to bit line.Register REG is stored in the data of reading among the sensor amplifier S/A temporarily, and in write operation, data is stored in the memory cell again.

I/O logic 220 is according to output signal and read/write instruction R from column decoder 170 ,/W read the data that are stored in the cell array 150 and with data storage in cell array 150.I/O logic 220 comprises array selecting signal C/S, and the data that response output enable signal/OE will be stored in the cell array 150 export data I/O register 230 to.

The reading of data of I/O impact damper 240 buffer-stored in I/O register 230 is to export buffered data to I/O pin two 50.I/O impact damper 240 bufferings write data buffered data is exported to I/O register 230 through what I/O pin two 50 received.The information that I/O buffering 240 will be stored in the update mode information register 200 through I/O pin two 50 exports system controller 300 to.

I/O pin two 50 will export system controller 300 to through data bus from the data that I/O impact damper 240 receives, and perhaps will export I/O impact damper 240 to through data bus from the data of system controller 300.

Read/write operation like following explanation semiconductor memory.

Weld pad array 100 receives row address and column address through a plurality of weld pad PAD, and exports the address to row address register 120 and column address register 180.

Row address register 120 is exported through time division multiplexing (timing multiplexing) method according to the control of row sequential logic 130 and row sequential logic 190 with column address register 180 has row address and the column address of the given time difference.

Row address register 120 can be provisionally and ras signal/RAS stores synchronized row address, and can export row address RADD to line decoder 140.When the output row address, column address register 180 interim memory row addresses.

The row address that row address register 120 is selected to receive from weld pad array 100 in normal running is to export the address to line decoder 140.When under new model more, activating when upgrading enable signal REF_EN, the counting address CA that row address register 120 is selected to receive from refresh counter 112 is to export the address to line decoder 140.

Column address register 180 is stored and the synchronous column address of cas signal/CAS provisionally, and exports column address to column decoder 170.When the output column address, row address register 120 interim storage line addresses.

Under read mode, when activating output enable signal/OE and activating reading command R, the data based I/O logic 220 that is stored in the cell array 150 outputs to I/O register 230.On the other hand, writing under the pattern, when un-activation output enable signal/OE and activation write instruction/W, according to I/O logic 220 with data storage in cell array 150.

Hereinafter, state the update method of bright semiconductor memory as follows.

When applying the renewal operational order; Update controller 111 will be carried out the update signal REF that upgrades operation and export refresh counter 112 to; And responding ras signal/RAs, cas signal/CAS, read/write instruction R ,/W will upgrade enable signal REF_EN with the renewal control signal and export row address register 120 to.

Circulation exports row address register 120 to will count address CA to the update signal REF that refresh counter 112 responses apply from update controller 111 with renewal control signal count update.

Be stored in the row address register 120 from the counting address CA of refresh counter 112 outputs.The data that row sequential logic 190 response cas signal/CAS will be stored in the column address register 180 export column decoder 170 to.When activating sensor amplifier S/A, will be stored in the writing unit array 150 that Updates Information among the register REG through I/O logic 220.

Update signal REF can be a control signal of utilizing ras signal/RAS and cas signal/CAS.That is to say, when update signal REF is to use the control signal of ras signal/RAS and cas signal/CAS, behind the usefulness elder generation/CAS/the RAS method (/CBR) carry out renewal to operate.

Being used to carry out under the normal mode that reads with write operation, activate ras signal/RAS quickly than cas signal/CAS, so that carry out normal runnings according to row sequential logic 130 and row sequential logic 190.When activating ras signal/RAs in the ban, activate the outer row address so that activate sensor amplifier S/A.When activating cas signal/CAS, activate the outer array address.

Under new model more, the cas signal/CAS that upgrades control module 111 read-around ratio ras signals/RAS transmission earlier is to activate update signal REF.That is to say,, upgrade control module 111 and judge that more new model is upgraded enable signal REF_EN to activate when upgrading control module 111 read-around ratio ras signals/RAS earlier during the cas signal of transmission/CAS.

When enable signal REF_EN is upgraded in activation, row address register 120 responds the counting address CA that produces according to refresh counter 112 and carries out the renewal operation, and ends the route of normal mode.Row address register 120 can be read the synchronous transmission of cas signal/CAS and ras signal/RAS to activate update signal REF.

Although the update method of use/CBR method is shown for example with embodiments of the invention, also can be through having self refresh, upgrading automatically or the several different methods of timing is carried out and upgraded operation.

Under new model more, can be according to word line WL as the counting address CA selected cell array 150 of the output signal of refresh counter 112.As a result, read and be amplified in the data that have the corresponding unit of 1T-FET structure in the cell array 150, and with this data storage at sensor amplifier register REG.New data write unit array 150, the data that perhaps are stored among the register REG are stored in the cell array 150 again.

Hereinafter, like the update method of following explanation according to the semiconductor memory of the conducting/shutoff of power supply.

When power supply is switched on and is turned off as the system power supply of the DRAM of volatile memory, upload the data of storer so that begin new renewal operation.That is to say, when the system power supply conducting, require to upload the data of storer.

Yet in non-volatile according to an embodiment of the invention ferroelectric memory device, when power turn-on and shutoff system power supply, update mode information register 200 can judge whether surpass update time.

When surpassing update time, upload the data of storer so that begin new renewal operation.On the other hand, when not surpassing update time, update time is effectively so that continue in preceding renewal operation.

Update mode information register 200 is stored in parameter relevant with upgrading operation in the non volatile register.The shutdown time sequence information of update mode information register 200 storage update count informations, system or internal storage and other non-volatile parameter informations.In update mode information register 200, the additional power supply sensing element (not shown) read-out system or the conduction and cut-off state of internal storage.

When power cutoff, read the data that are stored in the update mode information register 200 and upgrade lapse of time to calculate.Renewal lapse of time can be stored among the mode register set MRS or control in system level.

Renewal lapse of time that response renewal control signal is calculated transfers to and upgrades control module 111 and control renewal operation.As a result, in this embodiment, even also need not to upload during power turn-on and upgrade relevant information.

Update method comprises distributed update method and pulse update method.

In the distributed update method, carry out the renewal operation with identical time distribution, in refresh counter 112 so that the counting address CA that response is counted can upgrade whole unit in update time.

That is to say, when renewal 8k is capable, represent each distributed update operating cycle through (total update time)/8k.As a result, have only that the unit just can be initialised when data write all word line WL.

In the pulse update method, in cycling time is upgraded in paroxysm, carry out 8k continuously and upgrade circulation.Each pulse refers to each and upgrades circulation, and in the read/write operation cycle of sensitizing pulse not, carries out normal running.

In the update method of Nonvolatile ferroelectric memory device, description below clock control operation.

Whether update mode information register 200 recognition system power supplys turn-off, and event memory.When power remove, the system timer in the using system, and also the internal storage timer ends, so that operation is upgraded in control.System timer is used the battery storage date and time, and requires the continuous conducting of power supply.

On the other hand, when not having power cutoff, use the internal storage timer of operation separately so that operation is upgraded in control inside.

Conducting/off state according to power supply is selected one of external system timer or internal storage timer through I/O data pins 250.That is to say, comprise that the update mode information register 200 of the storage component part of internal storage timer passes through I/O impact damper 240 and I/O pin two 50 and data bus swap data.The system CPU that comprises system timer is through data bus and storage component part swap data.

When through the exchanges data power cutoff between storage component part and system controller 300, carry out the renewal operation with the external system timer of the continuous conducting of its power supply.When power turn-on, carry out the renewal operation with the internal storage timer.

As a result, the state regardless of the conducting/shutoff of the power supply of memory chip all keeps upgrading circulation and memory data effectively.Upgrading between the circulation, the memory chip power supply is turned off with the reduction power consumption, and only in the renewal circulation chip power is provided.

Fig. 6 illustrates the curve map of basis according to the data retention characteristics of the semiconductor memory of embodiments of the invention.

Along with time lapse, the cell data of traditional semiconductor memory is degenerated and is caused data to keep the restriction in life-span.As a result, along with time lapse, reduce corresponding to the bit line BL electric current of cell data " 1 " and " 0 ".

Yet, when power remove, when bit line BL electric current reduces, carry out the renewal operation with the given cycle, thereby the cell data of storage degeneration is to improve data retention characteristics again in the given time.

Surpass when presetting desired value when the data retention characteristics of memory cell is reduced to, thereby drive refresh circuit with initial state memory cell data again.The degeneration limit object time of unit becomes update time so that in update time, operate whole unit.

According to semiconductor memory of the present invention is the DRAM with non-volatile nature.The conducting of power supply/turn-off time increases and is provided with as the total data retention time, makes to carry out continually to upgrade operation, thereby reduces power consumption and improve performance.

Fig. 7 illustrates the planimetric map of basis according to the cell array of the semiconductor memory of embodiments of the invention.

Cell array is included in many word line WL that line direction is arranged.Arrange multiple bit lines BL perpendicular to many word line WL (column direction).A plurality of unit C can be arranged in the zone that many word line WL and multiple bit lines BL intersect.

Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>alternately arrange respectively at different layers with even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.When a unit C is connected to two bit lines BL, prevent that the area of bit line BL from increasing.

That is to say that even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are formed on upper strata or the lower floor of odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9 >.Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are formed on upper strata or the lower floor of even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.

Unit C comprises word line WL and the two bit lines BL that arrange at different layers.For example, unit C comprises word line WL < 0 >, contacts even bitlines BL < 2>and the odd bit lines BL < 3>that BLC connects through bit line.

Fig. 8 illustrates basis according to the cell array structure of the semiconductor memory of embodiments of the invention and the figure of read operation.

Many word line WL at line direction according to given being spaced.Multiple bit lines BL arranges perpendicular to many word line WL, that is, and and on column direction.A plurality of unit C are arranged in the zone that many word line WL and multiple bit lines BL intersect.

Unit C with 1-T FET structure is connected to word line WL < 0>and is formed on bit line BL < 0 >, the BL < 1>in the different layers.Although use according to embodiments of the invention word line WL < 0>and bit line BL < 0 >, BL < 1>be shown for example, can apply the present invention to remaining word line WL < 1 >, WL < 2>... with remaining bit line to BL < 2 >, BL < 3>....

Unit C has the grid that is connected paired bit line BL < 0 >, drain electrode and source electrode between the BL < 1>and is connected to word line WL < 0 >.The paired bit line BL < 0 >, the BL < 1>that are arranged in the different layers are connected to sensor amplifier S/A, write driver W/D and register REG.

Sensor amplifier S/A read and the amplifying unit data so that data " 1 " and data " 0 " are distinguished, so that sensor amplifier S/A is connected to right bit line BL < 0 >, BL < 1 >.In order to produce reference current, sensor amplifier S/A is through reference voltage terminal ref transmission reference voltage.

When the writing data into memory unit, configuration write driver W/D is to form driving voltage so that driving voltage is provided to bit line BL according to writing data.Write driver W/D is connected to right bit line BL < 0 >, BL < 1 >.Register REG as the temporary storage element of the data that are used for interim memory sense amplifier S/A is connected to right bit line BL < 0 >, BL < 1 >.

Under the read mode of cell array,, ground voltage GND is put on unselected word line WL < 1 >, WL < 2>with reading the word line WL < 0>that voltage puts on selection.

The bias voltage Vsen that reads that will be used for the read current of sensing element C puts on the paired bit line BL < 0>that is connected to unit C, the bit line BL < 0>of BL < 1 >.Ground voltage is put on bit line BL < 1 >.

Unit read current Isen flows according to the store status of cell data.As a result, the electric current that in paired bit line BL < 0 >, BL < 1 >, flows dissimilates according to the polarity of ferroelectric layer 4, so that read the cell data that is stored among the unit C.

That is to say, put on word line WL < 0>when reading voltage Vrd, when reading bias voltage Vsen and putting on bit line BL < 0>and ground voltage and put on bit line BL < 1 >, sensor amplifier S/A reads out in the value of the unit read current Isen that flows among the bit line BL < 0 >.

When the channel region of memory cell ended, the value of sensing element read current Isen was so that can read the data " 1 " that are stored in the memory cell.On the other hand, when the channel region conducting, the value of sensing element read current Isen is so that can read the data " 0 " that are stored in the memory cell.

Fig. 9 illustrates basis according to the cell array structure of embodiments of the invention semiconductor memory and the figure of data " 0 " write operation.

When writing data " 0 ", the supply voltage VDD that surpasses threshold voltage Vc that changes ferroelectric polar character is put on the word line WL < 0>of selection and ground voltage GND is put on unselected word line WL < 1 >, WL < 2 >.Ground voltage puts on paired bit line BL < 0 >, the BL < 1>that is connected to unit C.

Read voltage Vrd less than threshold voltage Vc, and supply voltage VDD is greater than threshold voltage Vc.Read bias voltage Vsen less than reading voltage Vrd.

Polarization ferroelectric material when the channel region conducting of memory cell.As a result, data ' 0 ' write store unit.That is to say, when supply voltage VDD puts on word line WL < 0>and ground voltage and puts on paired bit line BL < 0 >, BL < 1 >, according to the polarization communication channel district of ferroelectric layer 4 so that data " 0 " can the write store unit.

Figure 10 is the cell array structure of semiconductor memory according to an embodiment of the invention and the figure of data ' 1 ' write operation.

When writing data " 1 ", negative read voltage-Vrd and put on selected word line WL < 0 >, and ground voltage GND puts on unselected word line WL < 1 >, WL < 2 >.

Read voltage Vrd and put on paired bit line BL < 0 >, the BL < 1>that is connected to unit C.

Just reading drain electrode and source electrode that voltage Vrd puts on unit C, bearing and read the grid that voltage-Vrd puts on unit C.As a result, the channel region of the voltage cut-off memory cell that is higher than threshold voltage Vc of the polarization through changing ferroelectric layer 4, so that data ' 1 ' can be written into memory cell.

Put on word line WL < 0>and read voltage Vrd when putting on paired bit line BL < 0 >, BL < 1>at the negative voltage-Vrd that reads, according to the polarization of ferroelectric layer 4 by channel region so that data ' 1 ' can be written into memory cell.The voltage that is lower than threshold voltage Vc put on data ' 0 corresponding to selected row ' the unit in case keep data ' 0 '.

Figure 11 illustrates the sequential chart of the read operation of semiconductor memory according to an embodiment of the invention.

At cycle t1, selected word line WL < 0>from ground connection GND level transitions for reading voltage Vrd level, and bit line BL from ground connection GND level transitions to reading bias voltage Vsen level.Sensor amplifier S/A reads and amplifies the value of the unit read-out voltage Isen that flows through bit line BL, and this value is stored among the register REG.

Figure 12 is the sequential chart that illustrates according to the write operation of the semiconductor memory of the embodiment of the invention.

At cycle t1, selected word line WL < 0>from ground connection GND level transitions for reading voltage Vrd level, and bit line BL from ground connection GND level transitions to reading bias voltage Vsen level.In whole unit of selected row, sensor amplifier S/A reads and amplifies the value of the unit read current Isen that flows through bit line BL, and this value is stored among the register REG.

At cycle t2, selected word line WL < 0>is a supply voltage VDD level from reading voltage Vrd level transitions, and bit line BL is from reading bias voltage Vsen level transitions to reading voltage Vrd or ground voltage GND level.As a result, data ' 0 ' can be written into whole unit of selected row.

At cycle t3, selected word line WL < 0>reads voltage-Vrd level from supply voltage VDD level transitions to negative, and bit line BL maintains and reads voltage Vrd or ground voltage GND level.Being stored in data among the register REG writes and is stored in the memory cell again or can write new outside and apply data.

Because cycle t1 write earlier data ' 0 ', so keep data " 0 " or cycle t3 write data ' 1 '.

Figure 13 illustrates the figure of the cell array of semiconductor memory according to an embodiment of the invention.

Cell array is included in many word line WL that line direction is arranged.Multiple bit lines BL arranges (on column direction) perpendicular to many word line WL.Each is configured in the zone that many word line WL and multiple bit lines BL intersect a plurality of unit C.

Be used for bit line BL0 (W), BL1 (W), BL2 (W), the BL3 (W) of write operation and be used for each alternately disposing at the bit line BL0 of different layers read operation (R), BL1 (R), BL2 (R), BL3 (R).When a unit C is connected to two bit lines BL, prevent that the area of bit line BL from increasing.

That is to say that bit line BL0 (R), BL1 (R), BL2 (R), BL3 (R) are formed on upper strata or the lower floor of bit line BL0 (W), BL1 (W), BL2 (W), BL3 (W).The bit line BL0 (W) of odd column direction, BL1 (W), BL2 (W), BL3 (W) are formed on bit line BL0 (R), BL1 (R), the BL2 (R) of even column direction, upper strata or the lower floor of BL3 (R).

Unit C comprises word line WL and the two bit lines BL that are arranged in different layers.For example, unit C comprises word line WL < 0>and the bit line BL0 (W), the BL0 (R) that are connected through bit line contact BLC.

Figure 14 is the cell array structure that semiconductor memory according to an embodiment of the invention is shown, the figure that writes driver element W/D, sensor amplifier S/A and register REG.

Sensor amplifier S/A read and the amplifying unit data to distinguish data " 1 " and data " 0 " so that sensor amplifier S/A is connected to every reading bit line BL (R).The data of the interim memory sense amplifier S/A of register REG, and be connected to reading bit line BL (R).Sensor amplifier S/A and register REG are connected to the I/O circuit IO into data bus ,/IO.

When the writing data into memory unit, configuration write driver W/D is to form driving voltage so that driving voltage is provided to writing bit line BL (W) according to writing data.Write driver W/D is connected to and writes bit line BL (W).

Figure 15 illustrates the circuit diagram of the line decoder 140 of semiconductor memory according to an embodiment of the invention.

Line decoder 140 is controlled the voltage level that is provided to word line WL according to the input of row address.Line decoder 140 comprises row-address decoder unit 400, voltage supply unit 410 and word line driving unit 430.

Row-address decoder unit 400 comprises that being configured to that NAND is carried out in the input of row address operates so that the NAND grid ND1 of output enable signal ENB.

Voltage supply unit 410 is included as a plurality of nmos pass transistor N1～N3 of on-off element.The nmos pass transistor N1 that is connected between the first voltage V1 terminal and the word line driving unit 430 has the grid that receives voltage control signal V1C.

The nmos pass transistor N2 that is connected between the second voltage V2 terminal and the word line driving unit 430 has the grid that receives voltage control signal V2C.The nmos pass transistor N3 that is connected between tertiary voltage V3 terminal and the word line driving unit 430 has the grid that receives voltage control signal V3C.

The first voltage V1, the second voltage V2 and the tertiary voltage V3 that offers word line WL reads voltage Vrd, supply voltage VDD and the negative voltage-Vrd that reads.

As shown in Figure 8, in read mode, reading voltage Vrd and can offer selected word line WL < 0>as the first voltage V1.As shown in Figure 9, when writing data ' 0 ' time, can offer selected word line WL < 0>as the supply voltage VDD of the second voltage V2.Shown in figure 10, when writing data ' 1 ' time, can offer selected word line WL < 0>as the negative voltage-Vrd that reads of tertiary voltage V3.

Word line driving unit 430 comprises word line driving element, drop down element and the phase inverter IV1 that is connected between voltage supply unit 410 and the word line WL.Word line WL is connected to the nmos pass transistor N4 of word line driving element and is the nmos pass transistor N5 of drop down element.

Nmos pass transistor N5 has the grid of reception enable signal ENB of 400 outputs from the row-address decoder unit.Phase inverter IV1 counter-rotating enable signal ENB is with output enable signal EN.Nmos pass transistor N4 has the grid that receives enable signal EN.

Figure 16 is the oscillogram of operation that the line decoder 140 of Figure 15 is shown.

At cycle t0, when the line of input address, ENB activates to low level with enable signal.As a result, nmos pass transistor N5 remain off and nmos pass transistor N4 conducting.When activation voltage control signal V_1C, nmos pass transistor N1 conducting is to provide the first voltage V1 to word line WL.

At cycle t1, enable signal ENB maintains low level.As a result, nmos pass transistor N5 remain off, and nmos pass transistor N4 conducting.When activation voltage control signal V2C, nmos pass transistor N2 conducting is to provide the second voltage V2 to word line WL.

At cycle t2, enable signal ENB maintains low level.As a result, nmos pass transistor N5 remain off, and nmos pass transistor N4 conducting.When activation voltage control signal V3C, nmos pass transistor N3 conducting is to provide tertiary voltage V3 to word line WL.

After cycle t2, when not having the line of input address, enable signal ENB is activated at high level.As a result, nmos pass transistor N5 conducting is to provide ground voltage to word line WL.

Figure 17 is the circuit diagram that writes driver element W/D and sensor amplifier S/A that Figure 14 is shown.

Sensor amplifier S/A comprises column selector 500, balanced unit 510, register cell 520, pull-up unit 530, amplifying unit 540, amplifies and activate control module 550, load unit 560,562 and bias control unit 570,572.

Column selector 500 comprises nmos pass transistor N6, N7.Be connected I/O circuit IO ,/IO and lead-out terminal OUT, the nmos pass transistor N6 the between/OUT, N7 have the public grid that receives array selecting signal YS.

Balanced unit 510 comprises PMOS transistor P1～P3.PMOS transistor P1 is connected between supply voltage vdd terminal and the lead-out terminal OUT.PMOS transistor P3 is connected between supply voltage vdd terminal and the lead-out terminal/OUT.PMOS transistor P2 is connected lead-out terminal OUT, between/the OUT.PMOS transistor P1～P3 has the public grid that receives sensor amplifier equalizing signal SEQ.

Register cell 520 comprises PMOS transistor P4, P5 and nmos pass transistor N8, the N9 with a pair of anti-phase latch structure.PMOS transistor P4, P5 and nmos pass transistor N8, N9 cross-couplings.In this embodiment, with register cell 520 register REG is shown for example.

Pull-up unit 530 comprises PMOS transistor P6.The PMOS transistor P6 that is connected between two nodes of sensor amplifier has the grid that receives sensor amplifier equalizing signal SEQ.

Amplifying unit 540 comprises nmos pass transistor N10, N11.Be connected nmos pass transistor N10 between nmos pass transistor N8, the N12 and have the grid of receiving element voltage Vcell.The nmos pass transistor N11 that is connected between nmos pass transistor N6, the N9 has the grid that receives reference voltage Vref.

The amplification that is connected between amplifying unit 540 and the ground voltage terminal activates the grid that control module 550 has reception sensor amplifier enable signal SEN.

Load unit 560 comprises PMOS transistor P7.The PMOS transistor P7 that is connected between power supply voltage terminal and the bit line BL (R) has the grid that receives load voltage Vload.

Load unit 562 comprises PMOS transistor P8.The PMOS transistor P8 that is connected between power supply voltage terminal and the reference voltage Vref terminal has the grid that receives load voltage Vload.

Bias control unit 570 comprises nmos pass transistor N13.The nmos pass transistor N13 that is connected between cell voltage Vcell terminal and the bit line BL (R) has the grid that receives clamping voltage VCLMP.

Bias control unit 572 comprises nmos pass transistor N14.The nmos pass transistor N14 that is connected between reference voltage Vref terminal and the reference current Iref terminal has the grid that receives clamping voltage VCLMP.

Word line driving unit W/D is connected between lead-out terminal OUT and the write control unit 580.Write control unit 580 comprises nmos pass transistor N15.Be connected the nmos pass transistor N15 that writes between driver element W/D and the bit line BL (W) and have the grid that receives write control signal WCS.

Figure 18 is the oscillogram that writes driver element and sensor amplifier S/A that Figure 17 is shown.

If clamping voltage VCLMP increases, nmos pass transistor N13 conducting is with the bit line current Icell of transmission master unit.If clamping voltage VCLMP increases, nmos pass transistor N14 conducting is with transmission reference current Iref.

Load unit 560,562 comprises PMOS transistor P7, the P8 through load voltage Vload control.The load value of PMOS transistor P7, P8 converts electric current I cell and the reference current Iref of bit line BL into cell voltage Vcell and reference voltage Vref.

Amplify activation control module 550 through sensor amplifier enable signal SEN control.Activate amplifying unit 540 according to amplifying the state that activates control module 550.Amplifying unit 540 comes amplifying unit voltage Vcell and reference voltage Vref with the gain of nmos pass transistor N10, N11.

During the pre-charge cycle, two nodes of sensor amplifier are precharged to high level, thereby improve first amplification characteristic of sensor amplifier S/A according to the operation of pull-up unit 530.The voltage that in amplifying unit 540, amplifies is transmitted and is stored in the register cell 520.When activating sensor amplifier enable signal SEN, register cell 520 memory sense amplifiers write data.

Register cell 520 response array selecting signal YS and input/output line IO ,/IO swap data.The gain that register cell 520 amplifies amplifying unit 540 is to improve the offset characteristic of sensor amplifier S/A.During the pre-charge cycle, balanced unit 510 is precharged to high level with the output signal of register cell 520.

When activating array selecting signal YS, the nmos pass transistor N6 of column selector 500, N7 conducting are so that selectively with I/O circuit IO ,/IO is connected to lead-out terminal OUT ,/OUT.When write control signal WCS activates, write driver element W/D with I/O circuit IO, the data transmission of/IO is to bit line BL (W), and the data transmission that perhaps will be stored in register cell 520 is to bit line BL (W).

Figure 19 illustrates the figure of semiconductor memory according to an embodiment of the invention.

In one embodiment, 1-T FET type ferroelectric memory cell comprises and is used to store 1 left side bit memory cell 10 and be used to store the right bit memory cell 20 of 1, so that in the unit, store dibit.Hereinafter, position, the left side be called ' the L-position ' and position, the right be called ' the R position '.

L-bit memory cell 10 comprises channel region and the ferroelectric layer 4 that is arranged on based on the left part of the channel region of unit, so that storage data ' 1 ' perhaps ' 0 '.R-bit memory 20 comprises channel region and the ferroelectric layer 4 that is arranged on based on the right part of the channel region of unit, so that storage data ' 1 ' perhaps ' 0 '.

When reading the data that are stored in L-bit memory cell 10, N type district 2 is as the source region, and N type district 3 is as the drain region.When reading the data that are stored in the R-bit memory cell 20, N type district 3 is as the source region, and N type district 2 is as the drain region.One of N type district 2,3 can be drain region or source region.

Under the pattern that writes of memory cell, data can side by side be written in L-bit memory cell 10 and the R-bit memory cell 20.Under read mode, the data that are stored in L-bit memory cell 10 and the R-bit memory cell 20 can not side by side read.

L-bit memory cell 10 is through being applied to grid region (channel region) and being set to the valid data storage area as the zone of the polar switching of the voltage ferroelectric layer 4 between the N type district 2 in source region.R-bit memory cell 20 is through being applied to grid region (channel region) and being set to the valid data storage area as the zone of the polarity of the voltage ferroelectric layer 4 between the N type district 3 in source region.

Because weak raceway groove bias voltage puts on the zone between L-bit memory cell 10 and the R-bit memory cell 20, so the data of wanting do not read or write, but the invalid data that does not influence the read/write operation of data is stored.According to put on Lou/bias voltage in source region can change the width corresponding to the memory block of L-bit memory cell 10 and R-bit memory cell 20.

Figure 20 illustrates the figure of the data of semiconductor memory ' 00 ' write operation according to an embodiment of the invention.

For with in data ' 0 ' be stored in L-bit memory cell 10 and the R-bit memory cell 20, supply voltage VDD puts on word line 5.Ground voltage GND puts on N type leakage/source region 2,3.According to the polarity of ferroelectric layer 4 make negative charge get into channel region in case write data ' 00 '.

Figure 21 illustrates the figure of the data of semiconductor memory ' 01 ' write operation according to an embodiment of the invention.

For with data ' 0 ' be stored in L-bit memory cell 10 with data ' 1 ' be stored in the R-bit memory cell 20, negatively read voltage-Vrd and put on word line 5.Ground voltage GND puts on N type leakage/source region 2, and is just reading voltage Vrd and put on N type leakage/source region 3.

Make negative charge get into the channel region of L-bit memory cell 10 according to the polarity of ferroelectric layer 4, so as to write data ' 0 '.Make positive charge get into the channel region of R-bit memory cell 20 according to the polarity of ferroelectric layer 4, so as to write data ' 1 '.

Figure 22 illustrates the figure of the data of semiconductor memory ' 10 ' write operation according to an embodiment of the invention.

For with data ' 1 ' be stored in L-bit memory cell 10 with data ' 0 ' be stored in the R-bit memory cell 20, negatively read voltage-Vrd and put on word line 5.Just reading voltage Vrd and putting on N type leakage/source region 2, ground voltage GND puts on N type leakage/source region 3.

Polarity according to ferroelectric layer 4 is introduced the channel region of L-bit memory cell 10 with positive charge, so as to write data ' 1 '.According to the polarity of ferroelectric layer 4, negative charge is introduced the channel region of R-bit memory cell 20 so that write data ' 0 '.

Figure 23 illustrates the figure of the data of semiconductor memory ' 11 ' write operation according to an embodiment of the invention.

For with data ' 1 ' be stored in L-bit memory cell 10 with data ' 1 ' be stored in the R-bit memory cell 20, negatively read voltage-Vrd and put on word line 5.Just read voltage Vrd and putting on N type leakage/source region 2,3.According to the polarity of ferroelectric layer 4, positive charge is introduced channel region so that write data ' 11 '.

Figure 24 is the figure that illustrates according to the read operation of the L-bit data of embodiments of the invention semiconductor memory.

In order to read the data that are stored in the L-bit memory cell 10, read voltage Vrd and put on word line 5.Ground voltage GND puts on N type leakage/source region 2, and reads bias voltage Vsen and put on N type leakage/source region 3.Read out in the mobile unit read current of channel region to read the data that are stored in the L-bit memory cell 10.

Figure 25 illustrates the figure of the read operation of the R-bit data of semiconductor memory according to an embodiment of the invention.

In order to read the data that are stored in the R-bit memory cell 20, read voltage Vrd and put on word line 5.Read bias voltage Vsen and put on N type leakage/source region 2, and ground voltage GND puts on N type leakage/source region 3.Read out in the mobile unit read current of channel region to read the data that are stored in the R-bit memory cell 20.

Figure 26 illustrates the sequential chart of the write cycle of semiconductor memory according to an embodiment of the invention.

At cycle t0, in whole unit of the row address of selecting, read and amplify the R-bit data, and be stored in the register.At cycle t1, in whole unit of the row address of selecting, read and amplify the L-bit data, and be stored in the register.

At cycle t2, because data " 0 " are written into whole storeies, so do not know which data storage is in the existing memory unit.As a result, in order to know which data storage in the existing memory unit, in data " 0 " write store unit before, data " 0 " are stored in the register.

In cycle t2, data " 0 " are written into whole unit of selected row address.At cycle t3, the data that under new model more, are stored in the register are write again and are stored in memory cell, in the perhaps new external data writing unit.At cycle t2,,, perhaps write data " 1 " so preserve data " 0 " because write data " 0 " previously at cycle t1.

Figure 27 illustrates the renewal round-robin sequential chart of semiconductor memory according to an embodiment of the invention.

At cycle t0, in whole unit of the row address of selecting, read and amplify the R-bit data, and be stored in the register.At cycle t1, in whole unit of the row address of selecting, read and amplify the L-bit data, and be stored in the register.

At cycle t2, carry out to upgrade in whole unit of " 0 " operation with the row address that L-position or R-bit data " 0 " is stored in again selection.At cycle t3, carry out to upgrade in whole unit of " 1 " operation with the row address that L-position or R-bit data " 1 " is stored in again selection.

Figure 28 illustrates the planimetric map of the cell array of semiconductor memory according to an embodiment of the invention.

Cell array is included in many word line WL that line direction is arranged.Multiple bit lines BL arranges (on column direction) perpendicular to many word line WL.A plurality of unit C are separately positioned on the zone that many word line WL and multiple bit lines BL intersect.

Configuration odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are with storage R-position.Configuration even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are with storage L-position.Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>and even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>alternately arrange each at different layers.When a unit C is connected to two bit lines BL, prevent that the area of bit line BL from increasing.

That is to say that even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are formed on upper strata or the lower floor of odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9 >.Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are formed on upper strata or the lower floor of even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.

Unit C comprises word line WL and the two bit lines BL that are arranged in different layers.For example, unit C comprises word line WL < 0 >, contacts even bitlines L-BL < 2>and the odd bit lines R-BL < 3>that BLC connects through bit line.

Figure 29 is the figure of read operation that cell array structure and the R-bit data of semiconductor memory according to an embodiment of the invention are shown.

Many word line WL at line direction according to given being spaced.Many idol/odd bit lines L-BL, R-BL arrange perpendicular to many word line WL, that is, and and on column direction.A plurality of unit C lay respectively at many word line WL and many idol/odd bit lines L-BL, the zone that R-BL intersects.

Unit C with 1-T FET structure is connected to word line WL < 0>and is formed on idol/odd bit lines L-BL < 0 >, the R-BL < 1>of different layers.Although word line WL < 0>and idol/odd bit lines L-BL < 0 >, R-BL < 1>are shown in an embodiment of the present invention for example, the present invention can be applied to all the other word line WL < 1 >, WL < 2>... with the paired L-BL < 2>of all the other bit lines, R-BL < 3>....

Unit C has the grid that is connected paired bit line L-BL < 0 >, drain electrode and source electrode between the R-BL < 1>and is connected to word line WL < 0 >.The paired bit line L-BL < 0 >, the R-BL < 1>that are arranged in different layers are connected to sensor amplifier S/A, write driver W/D and register REG.That is to say that every bit lines B is connected to sensor amplifier S/A, write driver W/D and register REG singly.

Sensor amplifier S/A read and the amplifying unit data so that data " 1 " and data " 0 " are distinguished, so that sensor amplifier S/A is connected to right bit line L-BL < 0 >, R-BL < 1 >.In order to produce reference current, sensor amplifier S/A is through reference voltage terminal ref transmission reference voltage.

When the writing data into memory unit, configuration write driver W/D is to form driving voltage so that driving voltage is provided to bit line BL according to writing data.Write driver W/D is connected to right bit line L-BL < 0 >, R-BL < 1 >.Register REG as the interim memory element that is used for memory sense amplifier S/A is connected to right bit line L-BL < 0 >, R-BL < 1 >.

Under the read mode of the R-of cell array bit data, will read voltage Vrd and be applied to selection word line WL < 0 >, and ground voltage GND will be applied to non-selection word line WL < 1 >, WL < 2 >.The bias voltage Vsen that reads that will be used for the read current of sensing element C puts on the bit line L-BL < 0>that is connected to unit C.Ground voltage GND is put on the bit line R-BL < 1>that is connected to unit C.

Unit read current Isen flows according to the store status of cell data.As a result, the electric current that in paired bit line L-BL < 0 >, R-BL < 1 >, flows dissimilates so that read the cell data that is stored among the unit C according to the polarity of ferroelectric layer 4.

That is to say; Put on word line WL < 0>when reading voltage Vrd; When reading bias voltage Vsen and putting on bit line L-BL < 0>and ground voltage and put on bit line R-BL < 1 >, sensor amplifier S/A reads out in the value of the unit read current Isen that flows among the bit line R-BL < 1>to read the R-bit data.

When the channel region of memory cell ended, the value of sensing element read current Isen was so that can read the data " 1 " that are stored in the R-bit memory cell 20.On the other hand, when the channel region conducting, the value of sensing element read current Isen is so that can read the data " 0 " that are stored in the R-bit memory cell 20.

Figure 30 illustrates the figure of the left bit data read operation of semiconductor memory according to an embodiment of the invention.

Under the read mode of L-bit data, with reading the word line WL < 0>that voltage Vrd puts on selection, and ground voltage GND is put on unselected word line WL < 1 >, WL < 2 >.Ground voltage GND is put on the bit line L-BL < 0>that is connected to unit C.The bias voltage Vsen that reads that is used for the read current of sensing element C puts on the bit line R-BL < 1>that is connected to unit C.

Unit read current Isen flows according to the store status of cell data.As a result, the electric current that in paired bit line L-BL < 0 >, R-BL < 1 >, flows dissimilates so that read the cell data that is stored among the unit C according to the polarity of ferroelectric layer 4.

That is to say; Put on word line WL < 0>when reading voltage Vrd; Ground voltage GND puts on bit line L-BL < 0>and reads bias voltage Vsen when putting on bit line R-BL < 1 >, and sensor amplifier S/A reads out in the value of the unit read current Isen that flows among the bit line L-BL < 0>to read the L-bit data.

When the channel region of memory cell ended, the value of sensing element read current Isen was so that can read the data " 1 " that are stored in the L-bit memory 10.On the other hand, when the channel region conducting, the value of sensing element read current Isen is so that can read the data " 0 " that are stored in the L-bit memory 10.

Figure 31 illustrates the figure of data ' 0000... ' write operation of semiconductor memory according to an embodiment of the invention.

When writing data ' 0000 ' time, the supply voltage VDD that surpasses threshold voltage Vc that changes ferroelectric polar character is applied to selection word line WL < 0 >, and ground voltage GND is applied to unselected word line WL < 1 >, WL < 2 >.Ground voltage is applied to whole one-tenth pairs of bit line L-BL, the R-BL that is connected to unit C.

Read voltage Vrd less than threshold voltage Vc, and supply voltage VDD is greater than threshold voltage Vc.Read bias voltage Vsen less than reading voltage Vrd.

When the channel region conducting of memory cell, make the ferroelectric material polarization.As a result, data ' 0000... ' write store unit.That is to say that when supply voltage VDD put on word line WL < 0>and ground voltage and puts on paired bit line L-BL, R-BL, channel region was according to the polarization conducting of ferroelectric layer 4, so that data ' 0000... ' can be written into memory cell.

Figure 32 is the figure that illustrates according to data ' 0101... ' write operation of embodiments of the invention semiconductor memory.

When writing data ' 0101 ' time, negatively read voltage-Vrd and put on selected word line WL < 0 >, and ground voltage GND puts on unselected word line WL < 1 >, WL < 2 >.Ground voltage puts on the bit line L-BL that is connected to unit C.Just read voltage Vrd and putting on the bit line R-BL that is connected to the unit.

Just read the negative voltage-Vrd that reads that voltage Vrd puts on the N type leakage/source region 3 of bit line R-BL and surpass the threshold voltage Vc of the reversing make ferroelectric layer 4 and putting on grid.As a result, when the channel region of memory cell ends, the ferroelectric material polarization.

The voltage that is lower than threshold voltage Vc put on the bit line L-BL of selected row so that data ' 0 ' be kept at L-bit memory cell 10 and data ' 1 ' write R-bit memory cell 20.Negative read voltage-Vrd and put on word line WL < 0 >, and ground voltage and just reading voltage Vrd and put on paired L-BL, R-BL.Polarization according to ferroelectric layer 4 ends channel region so that data ' 0101... ' can the write store unit.

Figure 33 illustrates the figure of data ' 1010... ' write operation of semiconductor memory according to an embodiment of the invention.

When writing data ' 1010 ' time, negatively read voltage-Vrd and put on selected word line WL < 0 >, and ground voltage GND puts on unselected word line WL < 1 >, WL < 2 >.Just reading voltage Vrd and putting on the bit line L-BL that is connected to unit C, and ground voltage puts on the bit line R-BL that is connected to unit C.

Just reading voltage Vrd and putting on the N type leakage/source region 2 of bit line L-BL, and the negative voltage-Vrd that reads that surpasses the threshold voltage Vc of the reversing that makes ferroelectric layer 4 puts on grid.As a result, when the channel region of memory cell ends, the ferroelectric material polarization.

The voltage that is lower than threshold voltage Vc put on the bit line R-BL of selected row so that data ' 0 ' be kept at R-bit memory cell 20 and data ' 1 ' write L-bit memory cell 10.Negative voltage-the Vrd that reads puts on word line WL < 0>and is just reading voltage Vrd and ground voltage puts on paired L-BL, R-BL.Polarization according to ferroelectric layer 4 ends channel region so that data ' 1010... ' can the write store unit.

Figure 34 is the figure that illustrates according to data ' 1111... ' write operation of embodiments of the invention semiconductor memory.

When writing data ' 1111 ' time, negatively read voltage-Vrd and put on selected word line WL < 0 >, and ground voltage GND puts on unselected word line WL < 1 >, WL < 2 >.Ground voltage puts on whole paired bit line L-BL, the R-BL that is connected to unit C.

As a result, when the channel region of memory cell ends, the ferroelectric material polarization.Negative read voltage-Vrd and put on word line WL < 0 >, and just reading voltage Vrd and put on paired L-BL, R-BL.Polarization according to ferroelectric layer 4 ends channel region so that data ' 1111... ' can the write store unit.

Figure 35 illustrates the sequential chart of the read operation of semiconductor memory according to an embodiment of the invention.

At cycle t1, selected word line WL < 0>from ground connection GND level transitions for read voltage Vrd level and bit line L-BL from ground connection GND level transitions to reading bias voltage Vsen level to read the R-bit data.Sensor amplifier S/A reads and amplifies the value of the unit read current Isen that flows through bit line L-BL, and the cell data of reading bit line R-BL also is stored in it among register REG.

At cycle t2, selected word line WL < 0>from ground connection GND level transitions for read voltage Vrd level and bit line BL from ground connection GND level transitions to reading bias voltage Vsen level to read the L-bit data.Sensor amplifier S/A reads and amplifies the value of the unit read current Isen that flows through bit line R-BL, and the cell data of reading bit line L-BL and it is stored among the register REG.

Figure 36 illustrates the sequential chart that writes/upgrade operation of semiconductor memory according to an embodiment of the invention.

At cycle t1, selected word line WL < 0>from ground connection GND level transitions for read voltage Vrd level and bit line L-BL from ground connection GND level transitions to reading bias voltage Vsen level.Sensor amplifier S/A reads and amplifies the value of the unit read current Isen that flows through bit line L-BL, and the cell data of reading bit line R-BL and it is stored among the register REG.

At cycle t2, selected word line WL < 0>from ground connection GND level transitions for read voltage Vrd level and bit line R-BL from ground connection GND level transitions to reading bias voltage Vsen level.Sensor amplifier S/A reads and amplifies the value of the unit read current Isen of the bit line L-BL that flows through in whole unit of select row, and the cell data of reading bit line L-BL and it is stored among the register REG.

At cycle t3, selected word line WL < 0>is a supply voltage VDD level from ground connection GND level transitions, and paired bit line L-BL, R-BL are from reading bias voltage Vsen level transitions to reading voltage Vrd or ground voltage GND level.As a result, data ' 0 ' can write whole unit of selected row.

At cycle t4, selected word line WL < 0>reads voltage-Vrd level from supply voltage VDD level transitions for negative, and paired bit line L-BL, R-BL remain on and read voltage Vrd or ground voltage GND level.Being stored in data among the register REG writes and is stored in the memory cell again or can write new outside and apply data.

Because before cycle t1 or t2 write data ' 0 ', so cycle t3 keep data ' 0 ' or write data ' 1 '.

Figure 37 is the figure that illustrates according to the cell array of the semiconductor memory of the embodiment of the invention.

Cell array is included in many word line WL that line direction is arranged.Multiple bit lines BL arranges (on column direction) perpendicular to many word line WL.A plurality of unit C are configured in the zone that many word line WL and multiple bit lines BL intersect respectively.

Configuration odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are with storage R-position.Configuration even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are with storage L-position.Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>alternately arrange at different layers respectively with even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.When a unit C is connected to two bit lines BL, prevent that the area of bit line BL from increasing.

That is to say that even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are formed on upper strata or the lower floor of odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9 >.Bit line BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are formed on upper strata or the lower floor of bit line BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.

Unit C comprises word line WL and the two bit lines BL that are arranged in different layers.For example, unit C comprises word line WL < 0 >, contacts even bitlines L-BL < 2>and the odd bit lines R-BL < 3>that BLC connects through bit line.

Figure 38 illustrates the figure of semiconductor memory according to an embodiment of the invention.

One-transistor (1-T) field effect transistor (FET) type ferroelectric memory cell comprises and is used to store the left n bit memory cell 10 of n-position and be used to store the right n bit memory cell 20 of n position, so that will in the unit, store 2n-position (n is a natural number).Hereinafter, left n-position is called ' the L-n position ', right n position is called ' the R-n position '.

L-n bit memory cell 10 comprises channel region and is arranged on the ferroelectric layer 4 of left part based on the channel region of unit, so that store the n-bit data.R-n bit memory cell 20 comprises channel region and is arranged on the ferroelectric layer 4 of right part based on the channel region of unit, so that store the n-bit data.

When reading the data that are stored in Ln-bit memory cell 10, N type district 2 is as the source region, and N type district 3 is as the drain region.When reading the data that are stored in the R-n bit memory cell 20, N type district 3 is as the source region, and N type district 2 is as the drain region.One of N type district 2,3 can be drain region or source region.Under the pattern that writes of memory cell, data can side by side write L-n bit memory cell 10 and R-n bit memory cell 20.Under read mode, the data that are stored in L-n bit memory cell 10 and the R-n bit memory cell 20 can not side by side read.

L-n bit memory cell 10 is through being applied to grid region (channel region) and being set to the valid data storage area as the zone of the polar switching of the voltage ferroelectric layer 4 between the N type district 2 in source region.R-n bit memory cell 20 is through being applied to grid region (channel region) and being set to the valid data storage area as the zone of the polar switching of the voltage ferroelectric layer 4 between the N type district 3 in source region.

Because weak raceway groove bias voltage puts on the zone between L-n bit memory cell 10 and the R-n bit memory cell 20, the data that are intended to do not read or write, but the invalid data that does not influence the read/write operation of data is stored.According to put on Lou/bias voltage in source region can change the width corresponding to the memory block of L-n bit memory cell 10 and R-n bit memory cell 20.

Figure 39 illustrates the figure that writes level of the n-bit memory cell of semiconductor memory according to an embodiment of the invention.

Need 2n to write voltage level storage n-bit data.That is to say, write voltage VW0, VW1 ..., VWm, VWn be used for storing data " 00..00 ", " 00..01 " ..., " 11..00 ", " 11..11 ".

Figure 40 illustrates the figure of the read current level of the n-bit memory cell of semiconductor memory according to an embodiment of the invention.

Require a plurality of reference levels electric current I ref (0)～Iref (m) read n-bit data " 00..00 ", " 00..01 " ..., " 11..00 ", " 11..11 ".For example, when data ' 3 ' when being stored in memory cell, according to the level that is stored in the cell data in the memory cell, 8 different read-out voltages put on bit line (perhaps sub-bit-line).

The voltage of reading through bit line is divided into 2n data level in main bit line, for example " 111 ", " 110 " ..., " 001 ", " 000 ".2n level and 2n-1 datum relatively also amplify.

Figure 41 illustrates the figure of the low data write operation of semiconductor memory according to an embodiment of the invention.

For with in data ' 0 ' be stored in L-n bit memory cell 10 and the R-n bit memory cell 20, supply voltage VDD puts on word line 5.Ground voltage GND puts on N type leakage/source region 2,3.According to the polarity of ferroelectric layer 4 make negative charge get into channel region in case write data ' 0 '.

Figure 42 is the figure that illustrates according to the 2n-position write operation of embodiments of the invention semiconductor memory.

In order the n-bit data to be stored in L-n bit memory cell 10 and the R-n bit memory cell 20, negatively to read voltage-Vrd and put on word line 5.N write voltage VW1 ..., one of VWm, VWn put on N type leakage/ source region 2,3.

Figure 43 illustrates the sequential chart in cycle write cycle of semiconductor memory according to an embodiment of the invention.

At cycle t0, in whole unit of the row address of selecting, read and amplify the R-n bit data, and be stored in the register.At cycle t1, in whole unit of the row address of selecting, read and amplify the L-n bit data, and be stored in the register.

At cycle t2, because data " 0 " write whole storeies, so do not know which data storage is in the existing memory unit.As a result, in order to know which data storage in the existing memory unit, in data " 0 " write store unit before, data " 0 " are stored in the register.

In cycle t2, data " 0 " write whole unit of selected row address.At cycle t3, under new model more, be stored in data in the register and write and be stored in again in the memory cell again and in the new external data writing unit.At cycle t2, because write data " 0 " previously, so preserve data at cycle t1 " 0 " and write new 2-n bit data.

Figure 44 illustrates the planimetric map of the cell array of semiconductor memory according to an embodiment of the invention.

Cell array is included in many word line WL that line direction is arranged.Multiple bit lines BL arranges (on column direction) perpendicular to many word line WL.A plurality of unit n-bit location C are configured in the zone that many word line WL and multiple bit lines BL intersect respectively.

Configuration odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are with storage R-n position.Configuration even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are with storage L-n position.Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>alternately arrange at different layers respectively with even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.When a unit C is connected to two bit lines BL, prevent that the area of bit line BL from increasing.

That is to say that even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are formed on upper strata or the lower floor of odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9 >.Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are formed on upper strata or the lower floor of even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.

Unit n-bit location C comprises word line WL and the two bit lines BL that are arranged in different layers.For example, unit C comprises word line WL < 0 >, contacts even bitlines L-BL < 2>and the odd bit lines R-BL < 3>that BLC connects through bit line.

Figure 45 is the figure of read operation that cell array structure and the R-n bit data of semiconductor memory according to an embodiment of the invention are shown.

Many word line WL at line direction according to given being spaced.Many idol/odd bit lines L-BL, R-BL arrange perpendicular to many word line WL, that is, and and on column direction.A plurality of unit n-bit location C lay respectively at the zone that many word line WL and many idol/odd bit lines L-BL, R-BL intersect.

Unit C with 1-T FET structure is connected to word line WL < 0>and is formed on idol/odd bit lines L-BL < 0 >, the R-BL < 1>of different layers.Although use according to embodiments of the invention word line WL < 0>and idol/odd bit lines L-BL < 0 >, R-BL < 1>be shown for example, can apply the present invention to remaining word line WL < 1 >, WL < 2>..., and remaining bit line to L-BL < 2 >, R-BL < 3>....

Unit n-bit location C has the grid that is connected paired bit line L-BL < 0 >, drain electrode and source electrode between the R-BL < 1>and is connected to word line WL < 0 >.Each column select switch C/S is connected to paired bit line L-BL < 0 >, the R-BL < 1>that is arranged in the different layers.That is to say that each bit line BL is connected to the column select switch C/S that is connected to data bus DB singly.According to the activation of column select switch C/S, signal transmits between bit line BL and data bus DB.

When reading the R-n bit data, read voltage Vrd and put on and select word line WL < 0>and ground voltage GND to put on unselected word line WL < 1 >, WL < 2 >.The bias voltage Vsen that reads that is used for the read current of sensing element n-bit location C puts on the bit line L-BL < 0>that is connected to unit n-bit location C.Ground voltage GND puts on bit line R-BL < 1 >.

Unit read current Isen flows according to the store status of cell data.As a result, the electric current that in paired bit line L-BL < 0 >, R-BL < 1 >, flows dissimilates so that read the cell data that is stored among the unit C according to the polarity of ferroelectric layer 4.

That is to say; Put on word line WL < 0>when reading voltage Vrd; When reading bias voltage Vsen and putting on bit line L-BL < 0>and ground voltage and put on bit line R-BL < 1 >, sensor amplifier S/A reads out in the value of the unit read current Isen that flows among the bit line R-BL < 1>to read the R-n bit data.

Figure 46 illustrates the cell array structure of semiconductor memory and the figure of L-n bit data read operation according to an embodiment of the invention.

When reading the L-n bit data, read voltage Vrd and put on and select word line WL < 0>and ground voltage GND to put on unselected word line WL < 1 >, WL < 2 >.Ground voltage GND puts on the bit line L-BL < 0>that is connected to unit n-bit location C.The bias voltage Vsen that reads that is used for the read current of sensing element n-bit location C puts on bit line R-BL < 1 >.

Unit read current Isen flows according to the store status of cell data.As a result, the electric current that in paired bit line L-BL < 0 >, R-BL < 1 >, flows dissimilates so that read the cell data that is stored among the unit n-bit location C according to the polarity of ferroelectric layer 4.

That is to say; Put on word line WL < 0>when reading voltage Vrd; Ground voltage GND puts on bit line L-BL < 0>and reads bias voltage vsen when putting on bit line R-BL < 1 >, and sensor amplifier S/A reads out in the value of the unit read current Isen that flows among the bit line L-BL < 0>to read the L-n bit data.

Figure 47 illustrates the figure of the low data write operation of semiconductor memory according to an embodiment of the invention.

When writing data ' 0 ' time, the supply voltage VDD that applies the threshold voltage Vc that surpass to change ferroelectric polar character is to selecting word line WL < 0 >, and applies ground voltage GND to unselected word line WL < 1 >, WL < 2 >.Ground voltage is applied to whole paired bit line L-BL, the R-BL that is connected to unit n-bit location C.

Read voltage Vrd less than threshold voltage Vc, and supply voltage VDD is greater than threshold voltage Vc.Read bias voltage Vsen less than reading voltage Vrd.

When the channel region of conducting memory cell, make the ferroelectric material polarization.As a result, data ' 0000... ' write store unit.That is to say, when supply voltage VDD puts on word line WL < 0>and ground voltage and puts on paired bit line L-BL, R-BL, channel region according to the polarization conducting of ferroelectric layer 4 so that data ' 0000... ' can the write store unit.

Figure 48 illustrates the figure of the 2n-bit data write operation of semiconductor memory according to an embodiment of the invention.

Writing in the pattern of 2n-bit data, negative read that voltage-Vrd puts on selected word line WL < 0>and ground voltage GND puts on unselected word line WL < 1 >, WL < 2 >.Negative voltage-the Vrd that reads has and reads voltage Vrd absolute value of a size, and absolute value is the magnitude of voltage with anti-phase.Write one of voltage VW1～VWn and put on paired bit line L-BL, the R-BL that is connected to unit n-bit location C.

Write N type leakage/ source region 2,3 that one of voltage VW1～VWn puts on paired bit line L-BL, R-BL with the storage desired data.For example, the voltage that is lower than threshold voltage Vc puts on even bitlines L-BL so that data ' 0 ' be kept in the L-n bit memory cell 10 of memory cell, data ' 1 ' write R-n bit memory cell 20.

Figure 49 illustrates basis according to the electric current sense amplifier array of the semiconductor memory of embodiments of the invention and the figure of reference unit.

Semiconductor memory comprises analog processor 400, digital-to-analog (D/A) converter 410, sense amplifier array 500, digital processing unit 510 and reference unit REF (0)～REF (n).Write voltage drive unit and comprise analog processor 400 and D/A converter 410.Data are read unit pack and are drawn together sense amplifier array 500, digital processing unit 510 and reference unit REF (0)～REF (n).

Analog processor 400 output simulating signal to D/A converters 410.D/A converter 410 will be that digital signal writes (storage again) voltage VW0～VWn to data bus DB so that produce 2n from the analog signal conversion that analog processor 400 receives.

Sense amplifier array 500 comprises 2n-1 sensor amplifier S/A.A plurality of sensor amplifier S/A will relatively also amplify from data bus DB data current Idata value that applies and reference levels electric current I ref (the 0)～Iref (m) that applies from reference unit REF (0)～REF (n).

Sensor amplifier S/A needs 2n-1 reference levels electric current I ref (0)～Iref (m) to read the 2n data at read mode.As a result, sensor amplifier S/A is connected to 2n-1 reference unit REF (0)～REF (n) singly.The digital signal that digital processing unit 510 outputs receive from sense amplifier array 500.

Figure 50 is the circuit diagram that the sensor amplifier S/A of Figure 49 is shown.

Sensor amplifier S/A comprises precharge unit 501 and amplifying unit 502.Precharge unit 501 comprises the PMOS transistor P9～P11 with the public grid that receives equalizing signal SEQ.PMOS transistor P9, P10 are connected supply voltage vdd terminal and lead-out terminal OUT, between/the OUT.PMOS transistor P11 is connected lead-out terminal OUT, between/the OUT.When activating equalizing signal SEQ, the sub-OUT of precharge unit 501 balanced output terminals ,/OUT.

Amplifying unit 502 comprises that the formation cross-couplings latchs PMOS transistor P12, P13 and the nmos pass transistor N16～N19 of amplifier.PMOS transistor P12 and nmos pass transistor N16, N18 are connected in series between supply voltage vdd terminal and the ground voltage terminal GND.PMOS transistor P13 and nmos pass transistor N17, N19 are connected in series between supply voltage vdd terminal and the ground voltage terminal GND.

The public grid of PMOS transistor 12 and nmos pass transistor N16 is connected to lead-out terminal/OUT.The public grid of PMOS transistor P13 and nmos pass transistor N17 is connected to lead-out terminal OUT.

Nmos pass transistor N18, N19 have the public grid that receives sensor amplifier enable signal SEN.Put on data bus DB from the data current Idata of sensor amplifier S/A output.Put on reference unit REF from the reference levels electric current I ref of sensor amplifier S/A output.

Figure 51 illustrates the sequential chart of the read operation of semiconductor memory according to an embodiment of the invention.

At cycle t1, selected word line WL < 0>from ground connection GND level transitions for reading voltage Vrd level, and bit line L-BL from ground connection GND level transitions to reading bias voltage Vsen level to read the R-n bit data.Sensor amplifier S/A read and amplify the unit read-out voltage Isen that flows through bit line L-BL value and reading bit line R-BL cell data and it is stored among the register REG.

At cycle t2, selected word line WL < 0>from ground connection GND level transitions for reading voltage Vrd level, and bit line R-BL from ground connection GND level transitions to reading bias voltage Vsen level to read the L-n bit data.Sensor amplifier S/A read and amplify the unit read-out voltage that flows through bit line R-BL value and readout bit line L-BL cell data and it is stored among the register REG.

Figure 52 illustrates the sequential chart that writes/upgrade operation of semiconductor memory according to an embodiment of the invention.

At cycle t1, selected word line WL < 0>from ground connection GND level transitions for reading voltage Vrd level, and bit line L-BL from ground connection GND level transitions to reading bias voltage Vsen level.Sensor amplifier S/A read and amplify the bit line L-BL in all unit of the row of selecting that flows through unit read-out voltage Isen value and readout bit line R-BL cell data and it is stored among the register REG.

At cycle t2, selected word line WL < 0>from ground connection GND level transitions for read voltage Vrd level and bit line R-BL from ground connection GND level transitions to reading bias voltage Vsen level.Sensor amplifier S/A read and amplify the bit line R-BL that flows through in whole unit of select row unit read-out voltage Isen value and readout bit line L-BL cell data and it is stored among the register REG.

At cycle t3, word line WL < 0>is that supply voltage VDD level and bit line L-BL or bit line R-BL are from reading bias voltage Vsen level transitions to reading voltage Vrd or ground voltage GND level from reading voltage Vrd level transitions.As a result, data ' 0 ' can write whole unit of selected row.

At cycle t4, selected word line WL < 0>reads voltage-Vrd level and bit line L-BL or bit line R-BL and maintains on the ground voltage GND level for negative from supply voltage VDD level transitions.Being stored in data among the register REG writes and is stored in the memory cell again or write new outside and apply data.

Because cycle t3 write in advance data ' 0 ', so cycle t4 keep data ' 0 ', and write the 2n-bit data according to writing voltage VW1～VWn.

Figure 53 is the figure that illustrates according to the cell array of embodiments of the invention semiconductor memory.

Cell array is included in many word line WL that line direction is arranged.Multiple bit lines BL arranges (on column direction) perpendicular to many word line WL.A plurality of unit C are configured in the zone that many word line WL and multiple bit lines BL intersect respectively.

Configuration odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are with storage R-position.Configuration even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are with storage L-position.Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>alternately arrange at different layers respectively with even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.When a unit C is connected to two bit lines BL, prevent that the area of bit line BL from increasing.

That is to say that even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8>are formed on upper strata or the lower floor of odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9 >.Odd bit lines BL < 1 >, BL < 3 >, BL < 5 >, BL < 7 >, BL < 9>are formed on upper strata or the lower floor of even bitlines BL < 0 >, BL < 2 >, BL < 4 >, BL < 6 >, BL < 8 >.

Unit n-bit location C comprises word line WL and the two bit lines BL that are arranged in different layers.For example, unit C comprises word line WL < 0 >, contacts even bitlines L-BL < 2>and the odd bit lines R-BL < 3>that BLC connects through bit line.

As stated; According to the embodiment of the invention; 1T-FET type ferroelectric memory cell with the non-volatile nature that is applied to DRAM is carried out the cell data that renewal operation with period demand is degenerated with storage again; And improve data retention characteristics,, also do not destroy lastest imformation even during power cutoff.

1T-FET type ferroelectric memory cell with the non-volatile nature that is applied to DRAM is stored in dibit in the unit, thereby reduces cellar area.

1T-FET type ferroelectric memory cell with the non-volatile nature that is applied to DRAM is stored in the 2n-position in the unit, thereby reduces cellar area.

1T-FET type ferroelectric memory cell is not carried out continually and is upgraded operation, and data hold time comprises power turn-on/turn-off time, thereby reduces power consumption and improve performance.

Even 1T-FET type ferroelectric memory cell is carried out the renewal operation so that when power cutoff, also keep lastest imformation according to the parameter information that is stored in the non volatile register.

According to the above embodiment of the present invention be illustrating property be not restrictive.Various variations and equivalent are possible.Sedimentation type, etch-polish and patterning step that the present invention does not receive here to describe limit.The present invention also is not limited to the semiconductor devices of any particular type.For example, the present invention can be implemented on dynamic RAM (DRAM) device or nonvolatile memory device.Other increase, deletion, or revise in view of the present invention and be conspicuous and be intended to drop in the scope of appended claim.

The application based on and the interests of the korean patent application No.10-2006-00135179,00135181,00135182 that requires to submit on Dec 27th, 2006 and on June 29th, 2007,10-2007-0065033,0065034,0065008 right of priority.The full content of these applications form is by reference introduced this paper.

Claims (23)

1. semiconductor memory comprises:

Be formed on channel region, drain region and source region in the substrate, said substrate has floating state;

Be formed on the ferroelectric layer of this channel region top; With

Be formed on the word line of this ferroelectric layer top,

Wherein different channel resistances is introduced this channel region in polarization state according to this ferroelectric layer; Reading voltage puts on this word line and reads bias voltage when putting on this drain region with one of this source region; Carry out data read operation and carry out data write operation with the polarity that changes this ferroelectric layer through the unit read current value of distinguishing according to the polarization state of this ferroelectric layer through voltage being put on this word line, this drain region and this source region.

2. according to the semiconductor memory of claim 1, wherein the maximal value of the voltage in this drain region and this source region or minimum value are set to conducting or read the magnitude of voltage of voltage by this of this channel region.

3. according to the semiconductor memory of claim 1, wherein when low data write this ferroelectric layer, supply voltage puts on this word line and ground voltage puts on this drain region and this source region.

4. according to the semiconductor memory of claim 1, wherein when high data write this ferroelectric layer, the negative voltage that reads puts on this word line and this and reads voltage and put on this drain region and this source region.

5. semiconductor memory comprises:

Comprise the 1-T FET type memory cell in the channel region, drain region and the source region that are formed in the substrate, said substrate has floating state;

Be formed on the ferroelectric layer of this channel region top; With

Be formed on the word line of this ferroelectric layer top, wherein different channel resistances introduced this channel region according to the polarization state of this ferroelectric layer,

Wherein this semiconductor memory comprises:

Many word lines in the line direction arrangement; With

The multiple bit lines of arranging perpendicular to these many word lines and

Wherein this memory cell is connected between a pair of adjacent bit lines of this multiple bit lines and is configured to and comes read/write data through the polarity that changes this ferroelectric layer according to the voltage that is applied to this word line and paired bit line.

6. according to the semiconductor memory of claim 5, wherein this multiple bit lines comprises the odd bit lines and the even bitlines of alternately arranging, and odd bit lines is respectively formed at different layers with even bitlines.

7. according to the semiconductor memory of claim 5; Wherein in this memory cell, put on this word line when reading voltage; When reading bias voltage and putting on one of paired bit line and ground voltage and put on another of paired bit line, through the unit read current value reading of data that in paired bit line, flows.

8. according to the semiconductor memory of claim 5, wherein this memory cell also comprises:

Be configured to amplify the sensor amplifier of the data of reading through this multiple bit lines; With

Be configured to store the register of the data of amplifying through this sensor amplifier.

9. according to Claim 8 semiconductor memory, wherein this sensor amplifier comprises:

Be configured to selectively this register is connected to the column selection unit of I/O circuit;

Be configured to compensate the balanced unit of this register;

Be configured to draw the pull-up unit of this register node;

Be configured to the amplifying unit of amplifying unit voltage and reference voltage;

The amplification that is configured to control the activation of this amplifying unit activates control module;

Be configured to the load unit of this cell voltage of load and this reference voltage; With

Be configured to control the electric current of this multiple bit lines and the bias control unit of reference current.

10. according to Claim 8 semiconductor memory comprises that also the data that are configured to data that are stored in register or I/O circuit provide the driver element that writes to this multiple bit lines.

11. according to the semiconductor memory of claim 5, wherein when low data write this memory cell, supply voltage puts on this word line and ground voltage puts on this paired bit line.

12. according to the semiconductor memory of claim 5, wherein when high data write this memory cell, the negative voltage that reads puts on this word line and is just reading voltage and puts on this paired bit line.

13. according to the semiconductor memory of claim 5, also comprise the input that is configured to according to row address, control offers the line decoder of the voltage levvl of this word line.

14. according to the semiconductor memory of claim 13, wherein this line decoder comprises:

Be configured to row-address decoder unit according to this row address output enable signal;

Be configured to the response voltage control signal and the voltage supply unit to this word line be provided corresponding voltage; With

Be configured to be applied to the voltage of this voltage supply unit, control the word line driving unit of the voltage levvl of this word line according to this enable signal of response.

15. the semiconductor memory with ferro-electric device, this storage component part comprises:

The 1-T FET type memory cell that comprises the channel region, drain region and the source region that are formed in the substrate;

Be formed on the ferroelectric layer of this channel region top;

Be formed on the word line of this ferroelectric layer top, wherein different channel resistances introduced this channel region according to the polarization state of this ferroelectric layer;

Many word lines in the line direction arrangement;

Multiple bit lines perpendicular to these many word lines arrangements; With

Be configured to carry out the renewal control module that upgrades operation, thereby improve the retention performance that is stored in the data in this memory cell with specific renewal circulation,

Wherein this memory cell is connected between a pair of adjacent bit lines of this multiple bit lines and is configured to and comes read/write data through the polarity that changes this ferroelectric layer according to the voltage that puts on this word line and paired bit line,

Wherein this renewal control module comprises:

Be configured to store and be used to control the non-volatile parameter information of this renewal operation and the update mode information register of output renewal control signal;

Be configured to respond this renewal control signal output update signal and the renewal control signal generation unit that is used to carry out the renewal enable signal that upgrades operation;

Be configured to respond this update signal count update circulation so that the refresh counter of output counting address;

With

Being configured to respond this renewal enable signal selects this counting address so that will count the row address register that the address exports line decoder to.

16., also comprise the register that is configured to provide to this memory cell with Updating Information according to the semiconductor memory of claim 15.

17., also comprise the row sequential logic that is configured in this renewal operation, activate this register according to the semiconductor memory of claim 16.

18. the update method with semiconductor memory of ferro-electric device, this storage component part comprises: at many word lines of line direction arrangement; Multiple bit lines perpendicular to these many word lines arrangements; With the 1-T FET type memory cell that comprises the channel region, drain region and the source region that are formed in the substrate; Be formed on the ferroelectric layer of this channel region top; With the word line that is formed on this ferroelectric layer top, wherein according to the polarization state of this ferroelectric layer of voltage change that puts on this word line and the pair of bit lines that is connected to this memory cell, this method comprises:

This channel region of 1T-FET type memory cell is introduced different channel resistances to read and/or to write data; With

Be stored in the data in this memory cell with specific renewal cycle and regeneration of mature, thereby improve the retention performance that is stored in the data in this memory cell, wherein this step of updating comprises:

Read these data of being stored in this memory cell with this data storage in register;

To hang down data and write this memory cell; With

The data that are stored in this register are write this memory cell perhaps high data are write this memory cell with the low data that keep being stored in this memory cell.

19. the semiconductor memory with ferro-electric device, this storage component part comprises:

N 1-T FET type memory cell, wherein n is a natural number; With

Many even bitlines of arranging perpendicular to many word lines and odd bit lines, the even summation odd bit lines is alternately arranged,

Wherein each memory cell is connected between a pair of adjacent idol/odd bit lines of these many even bitlines and these many odd bit lines; And the polarity of the ferroelectric layer that is configured to change through the voltage of reading according to this word line and paired idol/odd bit lines is read the data current of this memory cell and through a plurality ofly writing the polarity that voltage changes this ferroelectric layer and store 2 bit data with n level according to what putting on this word line and paired idol/odd bit lines.

20. the semiconductor memory according to claim 19 also comprises:

Being configured to provides the voltage drive unit that writes to paired idol/odd bit lines with these a plurality of voltages that write; With

Be configured to read the data sensing element of this data current according to the voltage that puts on this word line and paired idol/odd bit lines.

21. according to the semiconductor memory of claim 20, wherein this writes voltage drive unit and comprises:

Be configured to export the analog processor of simulating signal; With

The output conversion of signals that is configured to this analog processor is a digital signal so that export this a plurality of D/A converters that write voltage.

22. according to the semiconductor memory of claim 20, wherein these data are read unit pack and are drawn together:

Be configured to and the sense amplifier array of amplifying this data current and a plurality of reference levels current ratio;

Be configured to export the digital processing unit of the output signal of this sense amplifier array; With

Be configured to generate respectively a plurality of reference units of these a plurality of reference levels electric currents.

23. according to the semiconductor memory of claim 19, wherein this memory cell comprises:

Be configured to store the left n-bit memory of the left n-bit data that applies through this even bitlines; With

Be configured to store the right n-bit memory of the right n-bit data that applies through this odd bit lines.

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