KR19990016845A - Ferroelectric Semiconductor Memory Devices - Google Patents

Abstract

A ferroelectric semiconductor memory device is disclosed. The semiconductor memory device is a semiconductor memory device in which a capacitor using a ferroelectric is formed on a gate to enable a RAM operation, and a power consumption is reduced by reducing a write voltage and a write time by removing a reference cell.

Description

Ferroelectric Semiconductor Memory Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a nonvolatile semiconductor memory device having a capacitor made of ferroelectric material.

In general, semiconductor memory devices may be broadly classified into volatile memory devices and nonvolatile memory devices. Dynamic random access memory (DRAM) or SRAM (hereinafter referred to as SRAM) belonging to a volatile memory device has a characteristic in which input data is destroyed when the power is turned off. Read only memory, erasable and programmable read only memory (hereinafter referred to as EPROM), flash memory, and the like have characteristics such that once input data is maintained even after power off. Recently, as the application fields of semiconductor memory devices have been expanded, a large-capacity memory manufacturing technology has been developed. As a result, the integration of DRAM and SRAM has been greatly improved, but the problem of erasing data at power-off has not been solved. In addition, although the ROM, Ipyrom or flash memory device has an advantage of preserving data when the power is off, the input time is long and the life of the device is shortened because electrons are injected into the gate insulating film to input data. The effect is that the power consumption is increased.

Ferroelectric semiconductor memory devices (hereinafter referred to as FRAMs) have recently been developed in the art to solve the above-mentioned problems. FRAM refers to an erasable memory device using ferroelectrics, and materials used for ferroelectrics are ferroelectric materials including lead zirconium titanate (PZT), barium titanate (Ba ₂ TiO ₄ ), rochelle salt (sodium titanate sodium), and the like. These materials have spontaneous polarization and hysteresis exists between polarization and electric field strength. Therefore, the ferroelectric semiconductor memory device can be used as a nonvolatile memory device because if the voltage is applied to a certain voltage, spontaneous polarization is generated and the state is maintained even after removing the applied voltage.

In order to provide a thorough understanding of the present invention, the hysteresis characteristics of the ferroelectric material will be described in more detail with reference to FIG. 1.

Referring to FIG. 1, the X axis represents the electric field density and the Y represents polarization or charge. Ec is the voltage that inverts the charge. When a positive voltage is initially applied higher than Ec, the amount of charge saturates in the form of a curve from peak 0 to a. After falling to A instead of falling to A, the state of data 1 represented by the point A is maintained. However, if a negative voltage lower than -Ec is applied, the charge is inverted and reaches point b. If the supply of electric field is stopped at this point, the charge falls to point B, and the state of data 0 is also maintained. In other words, the on / off of the transistor is determined according to the direction of polarization induced in the ferroelectric capacitor located above the gate. That is, when polarization is at point A, the transistor is turned on by data 1; when polarization is inverted and is at point B, the transistor is turned off by data 0.

The FRAM having such ferroelectric capacitors is connected to one transistor to form one memory cell. However, in an FRAM having one capacitor / 1 transistor, an integration problem has arisen due to the size of the capacitors constituting the memory cell and the reference cell. In addition, a problem arises in that a ferroelectric material deteriorates during a read operation, thereby shortening the life of the device. In order to solve this problem, a prior art has been disclosed in the art of manufacturing a capacitor near the gate of the transistor to improve the integration degree and to enable non-destructive read out operation. However, the improved prior art has a problem that it is difficult to completely solve the problems of long input and output time and high power consumption. In addition, the importance of the integration of the reference cell is still important.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a method of manufacturing a ferroelectric semiconductor memory device capable of a RAM operation.

Another object of the present invention is to provide a method of manufacturing a ferroelectric semiconductor memory device capable of high speed operation and reducing power consumption.

It is still another object of the present invention to provide a method for manufacturing a ferroelectric nonvolatile semiconductor memory device capable of removing a reference cell.

1 is a graph showing the hysteresis characteristics of ferroelectrics.

2 is a detailed circuit diagram of a ferroelectric unit memory V in accordance with an embodiment of the present invention.

3A and 3B are equivalent circuit diagrams of the lead of FIG.

4 is a detailed circuit diagram of a memory array of a ferroelectric memory device according to an embodiment of the present invention.

A ferroelectric semiconductor memory device according to the present invention for achieving the above objects,

A pass transistor that functions as a switch by connecting a bit line to a source and a word line to a gate, and a gate and a lower electrode of the pass transistor are connected to each other. A ferroelectric capacitor having a nonvolatile characteristic connected to the bit line in common and connected to a write select line in common with the drain and the upper electrode of the pass transistor; a drain and the ferroelectric capacitor in the pass transistor; A diode which is commonly connected to the upper electrode of the cathode, and functions as a rectifying device having a read select line and an anode connected thereto, and a light select line applied to the drain of the pass transistor. A ferroelectric semiconductor having a memory fin array connected to an upper electrode of the ferroelectric capacitor It provides a memory device.

Other objects and novel features of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.

2 is a circuit diagram illustrating a unit memory VII of a ferroelectric semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2, a pass transistor connected to a source and a word line connected to a gate and serving as a switch, and a gate and a lower electrode of the pass transistor connected to each other are commonly connected to the bit line. A ferroelectric capacitor having a nonvolatile characteristic, in which a top electrode is connected to a drain of a pass transistor and commonly connected to a light selection line, a cathode is commonly connected to a drain and a top electrode of the pass transistor, and a lead select line and an anode are connected to each other. A diode functioning as a rectifying element and a light selection signal applied to the drain of the pass transistor are connected to the upper electrode of the ferroelectric capacitor.

3A to 3B are equivalent circuit diagrams of a unit n in a read operation by a voltage applied to the selection line of FIG. 2.

First, referring to FIG. 3A, an operation of reading data 1 in a read operation is performed. When the transistor 1 is turned on by the polarization of the ferroelectric, the polarization of the ferroelectric positioned above the gate of the pass transistor is A in FIG. 1. If, the word line W / L ₁ is floating and a positive voltage is applied to the lead select line RS / L ₁ so that current flows through the bit line B / L ₁ to read data. At this time, the current is controlled by the width of the inversion layer of the pass transistor rather than the voltage applied to the select line. In addition, when the data 1 is read, when a voltage is applied to the position of the node D, current due to the voltage flows to the bit line B / L ₁ . At this time, the voltage difference between node D and node B does not appear.

Referring to FIG. 3B, an operation of reading data 0 during read operation is performed. When pass transistor 1 is turned off due to polarization of the ferroelectric, the word line W / L ₁ is floated and the lead select line RS / L ₁ Positive voltage is applied, but the sensing method of the data varies depending on the magnitude of the applied voltage. That is, the voltage applied to the selection line is applied to the capacitor between the gate and the substrate and the ferroelectric capacitor, respectively. At this time, when the capacitor between the gate and the substrate becomes small, most of the voltage is applied to the gate. Therefore, when the voltage applied to the gate is below the threshold voltage, the pass transistor is turned off and no current flows. However, when the voltage of the select line is applied to the gate, the pass transistor is turned on and a large current flows. Therefore, data division is distinguished by the amount of current flowing through the bit line B / L ₁ . In addition, when the data 0 is read, when the voltage of the selection line is applied to the position of the node D, since the MOS transistor is turned off at the position of the node C, the voltage is divided into the node D and the node B and the node B and the node C.

Meanwhile, referring to the write operation, the following erase operation should be performed before the write operation. To the word line W / L ₁ is, and is applied initially to 0 volt, light selection line WS / L _1, the voltage V applied to the _WS and the write selection line WS / L voltage voltage ferroelectric capacitor 2 as applied to the _first Is applied to make the existing polarization state constant. At this time, the voltage applied to the write select line WS / L ₁ must be equal to or higher than the threshold voltage Ec, and the pass transistor 1 is turned on because the state of the polarization A of the hysteresis curve in FIG. The write operation is performed after the erase operation. When writing data 0, when voltage Vw is applied to word line W / L ₁ and a voltage of 0 Volt is applied through bit line B / L ₁ , the polarization of the ferroelectric is inverted by the voltage applied to the gate of the pass transistor. The result is the residual polarization-A state of FIG. 1 and the pass transistor is turned off. At this time, the voltage applied to the word line should be greater than or equal to the threshold voltage Ec. When the data 1 is written, the voltage Vw is applied to the word line W / L ₁ , and the voltage is applied through the pass transistor 1 when the voltage is applied through the bit line B / L 1. However, if the difference between the voltage applied to the word line W / L ₁ and the voltage applied through the bit line B / L ₁ is less than or equal to the threshold voltage, that is, the negative constant field Ec, the polarization is not inverted and the pass transistor is turned on. Keep it. In this case, the voltage applied to the bit line B / L ₁ should be lower than the voltage applied to the word line W / L ₁ by the threshold voltage Vth. In this way, data 1 and data 0 are distinguished and entered.

According to the present invention described above, a ferroelectric capacitor may be formed on the gate to manufacture a semiconductor memory device capable of a RAM operation.

In addition, by forming a ferroelectric capacitor on the gate, it is possible to manufacture a semiconductor memory device capable of high-speed operation and reduced power consumption.

In addition, a semiconductor memory device capable of removing the reference cell can be manufactured.

Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (6)

In a semiconductor memory device, A pass transistor functioning as a switch having a bit line connected to the source and a word line connected to the gate; A ferroelectric capacitor having a nonvolatile characteristic in which a gate and a lower electrode of the pass transistor are commonly connected to the bit line, and a drain and an upper electrode of the pass transistor are commonly connected to a light selection line; A diode having a cathode connected to a node at which a drain of the pass transistor and an upper electrode of the ferroelectric capacitor is connected to the light selection line, and a lead selection line and an anode connected to each other; And a write select signal applied to a drain of the pass transistor is connected to an upper electrode of the ferroelectric capacitor. 2. The operation of claim 1, wherein the data 1 is read in V, wherein the pass transistor is turned on by polarization of the ferroelectric, and a positive voltage is applied to a lead select line so that current flows through the bit line to read data. A ferroelectric semiconductor memory device. 2. The method of claim 1, wherein the data 0 is read at V, wherein the pass transistor is turned off due to polarization of the ferroelectric, and the sensing method of the data varies according to the magnitude of an applied voltage applied to a lead select line. A ferroelectric semiconductor memory device. The method of claim 1, wherein the writing of the data 0 at 쎌 is performed by applying a constant voltage to a word line and a voltage of 0 V to a bit line after an erase operation to turn on the pass transistor by making an existing polarization state constant. The polarization of the ferroelectric is inverted by the voltage applied to the gate, the pass transistor is turned off so that the data 0 is written. 2. The method of claim 1, wherein the writing of data 1 in the pulse is performed by a difference between the voltage applied to the word line and the voltage applied to the bit line after the erase operation of turning on the pass transistor by making the existing polarization state constant. If the voltage is less than the voltage, the polarization is not inverted, so that the pass transistor is turned on so that the data 1 is written. The ferroelectric semiconductor memory device of claim 1, wherein the diode is made of any one of a device such as a pn junction and a MOS transistor.