JP2003085998A - Semiconductor memory and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can perform confirmation of presence or absence of a short circuit of word lines and pairs of bit lines in a manufacturing process and specifying a short circuit part, in wafer state and to provide its test method. SOLUTION: This memory is provided with a first power source VBL which can be connected to a plurality of pairs of bit line BL- L/BL- L through transistors and which gives the prescribed potential to each pair of bit line when connected, and a second power source VBL1 which can be connected to a local IO line, can be connected to the prescribed pair of bit line by selection of a column selection line CSL by an external address, and which gives the prescribed potential when connected, and in pre-charge operation of a test mode, the first power source is separated from each pair of bit line, while voltage is applied to the prescribed pair of bit line from the second power source, a bit line short-circuiting to a word line WL is specified by measuring a leak current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of testing the same, and more particularly to a semiconductor memory device and a method of testing the same that can identify a short-circuited portion between a word line and a bit line pair.

[0002]

2. Description of the Related Art FIG. 15 is a schematic diagram showing a structure of a plurality of memory cell array blocks forming a part of a chip of a conventional semiconductor memory device and adjacent sense amplifier bands.
5 to 5 are memory cell array blocks, and A to D are adjacent sense amplifier bands. As is well known, one memory cell array block includes a plurality of word lines (for example, 256 lines) and a plurality of bit line pairs (for example, 256 lines).
Books) and are arranged in a matrix. FIG. 15 shows adjacent sense amplifier bands B and C (sense amplifiers B and C) of the memory cell array block 2 (memory cell array 2) including the selected word line and other sense amplifier bands A and D (sense amplifiers A and D). , Memory cell array blocks 1, 3 (memory cell arrays 1, 3) and 4, 5 having only non-selected word lines. The sense amplifiers B and C on both sides of the memory cell array block 2 including the selected word line are activated, and the other sense amplifiers are inactivated and are precharged.

FIG. 16 shows a memory cell array block 1 including only the non-selected word lines and sense amplifier bands B and C (sense amplifiers B and C) adjacent to the memory cell array block 2 (memory cell array 2) including the selected word line WLn. Three
(Memory cell arrays 1 and 3) and a BLI signal (BLI_
L1, BLI_L2, BLI_L3, BLI_R0, BLI_R1, BLI_R2) and BLEQ signal
It is a block diagram of (BLEQ0, BLEQ1, BLEQ2) and VBL signal. An MC shown at the intersection of the word line (WLn, WLn + 1) and the bit line pair (BL, / BL) is a memory cell. Sense amplifier is word line
It has a function of amplifying the data read to one of the bit line pairs (BL or / BL) connected to the memory cell MC selected by (WLn). In FIG. 16, when each word line of one memory cell array block is in the non-selected state, the BLEQ signals (BLEQ0, BLEQ1, B
LEQ2) is active (“H”) and the sense amplifier is inactive. Each bit line pair of one memory cell array block is controlled by the BLEQ signal (for example, BL_R / B in FIG. 17).
The internal power supply VBL is connected via L_R) and the transistors Tr.10 and Tr.11 of FIG. Also, when one word line is selected (“H”) in one memory cell array block, the BLEQ signals (BLEQ1, BLEQ2) on both sides of it are inactive (“L”) and the sense amplifier Is active. BL
Since the EQ signal is inactive, each bit line pair of one memory cell array block is disconnected from the internal power supply VBL.

FIG. 17 is a circuit diagram showing a structure corresponding to the memory cell arrays 2 and 3 and the sense amplifier C of FIGS. 15 and 16. The memory cell array 2 has word lines WL0 and WL1.
And a bit line pair BL_L / BL_L and a memory cell including transistors Tr.22 and Tr.23 provided at their intersections,
Similarly, the memory cell array 3 has memory cells including word lines WL2 and WL3, bit line pair BL_R / BL_R, and transistors Tr.24 and Tr.25 provided at the intersections thereof. The sense amplifier C is a PMOS-side sense amplifier including transistors Tr.3 and Tr.4 and an activation signal / SAEP applied to the transistor Tr.16 connected to this sense amplifier via S2P.
, An NMOS-side sense amplifier including transistors Tr.7 and Tr.8, and an activation signal circuit including an activation signal SAEN given to the transistor Tr.17 connected to this sense amplifier via S2N. Have and.

Transistors Tr.1, Tr.2 and Tr.12, Tr.13
Is a transistor that opens and closes the connection between the memory cell arrays 2 and 3 and the sense amplifier C, and CSL is a bit line pair BL_L / BL_L
And the column line selection signal that controls ON / OFF of the transistors Tr.5 and Tr.6 that connect BL_R / BL_R and the local IO line pair LIO / LIO. Tr.14 and Tr.15 are the local IO line pair LIO / LIO. This is a transistor that connects to the internal power supply VBL, and its on / off is controlled by the IO equalization signal IOEQ. Also,
Tr.18 and Tr.19 are local IO line pair LIO / LIO and global IO
A transistor that connects the line pair GIO / GIO, whose on / off is controlled by the RESEL signal. Tr.10 and Tr.11 are internal power supplies
A transistor that connects the VBL and the bit line pair, whose on / off is controlled by BLEQ that is an equalizing signal of the bit line pair. Also, Tr.20 and Tr.21 are transistors that connect the internal power supply VBL and the global IO line pair GIO / GIO.
ON / OFF is controlled by a signal. After the GIO line pair, data input / output with the outside is possible. The selected word line WLn in FIG. 16 is shown as WL0 in FIG. 17, BLI_L2 in FIG. 16 is shown as BLI_L in FIG. 17, and BLI_R2 in FIG. 16 is shown as BLI_R in FIG.

FIG. 18 is a timing chart of each signal shown in FIG. The part displayed as precharge is
The sense amplifier C is in the active state, and the sense amplifier C is in the active state in the portion indicated as the active state. The signals for activating the sense amplifier C are the above-mentioned / SAEP and SAEN,
The / SAEP signal is "L" when the sense amplifier C is in the active state, the SAEN signal is "H", and the / SAEP signal is "H" and the SAEN signal is "L" when the sense amplifier C is inactive. It is. In the active state in FIG. 18, the selected word line in FIG.
Since the transistors Tr.1 and Tr.2 are turned on when the BLI_L signal on the side of the memory cell array 2 including WL0 is activated (“H”), the memory cell array 2 and the sense amplifier C are connected. Also, when the RESEL signal is "H", the transistor Tr.18,
Since Tr.19 is turned on, the LIO line pair and the GIO line pair are connected. In this state, by selecting the bit line pair connected to the LIO line pair by the CSL signal, the transistors Tr.5 and Tr.6 are turned on while the CSL signal is selected (“H”). The cell, bit line pair, LIO line pair, GIO line pair, and external input / output are connected.

The BLI_R signal on the side of the memory cell array 3 including the non-selected word lines WL2 and WL3 is inactive ("L"),
Since the transistors Tr.12 and Tr.13 are turned off, the memory cell array 3 and the sense amplifier C are separated. Figure 1
In the precharge operation at 8, the BLI_L and BLI_R in FIG. 17 are activated (“H”), so that the transistors Tr.1 and T
The r.2, Tr.12, and Tr.13 are turned on, and the memory cell array 2 and the memory cell array 3 are connected to the sense amplifier C. At that time, the sense amplifier C is in the inactive state, and the word line WL of each of the memory cell array 2 and the memory cell array 3 is
0, WL1, WL2, WL3 are in the non-selected state. Since the RESEL signal is "L" and transistors Tr.18 and Tr.19 are off, LIO
The line pair and GIO line pair are in a separated state. All CSL signals are non-selected. Further, since the transistors Tr.10 and Tr.11 are turned on in the active state of the BLEQ signal, the internal power supply VBL, the memory cell array 2 and the memory cell array 3 are connected.

[0008]

Since the conventional semiconductor memory device is configured as described above, when the bit line pair and the word line of the semiconductor memory device are short-circuited by a foreign substance or the like during the manufacturing process. In the precharge state in which the sense amplifier is stopped, a defect appears remarkably. That is, in the precharge state, the word line is unselected (“L”) and the bit line pair and the memory cell are electrically separated from each other, and the bit line pair is equalized to the internal power supply VBL. Therefore, if there is such a short-circuited portion as described above, a current flows from the bit line pair to the word line, so that the potential VBL of the bit line pair becomes lower than that in the normal state. This state is S
It is conceivable that the longer the time when AEN is "L" and / SAEP is "H" and the sense amplifier is not operating, the more noticeable. As a means of easily checking this state from the outside, there is a method of monitoring the internal power supply VBL.

FIG. 19 shows a circuit configuration in which the potential of the internal power supply VBL during precharge can be externally measured in a wafer state. In this figure, 10
17 is a circuit for generating the internal power supply VBL in FIG. 17, which is a power supply internally generated so as to have a predetermined potential from the external power supply when there is no leak defect. SW1 and SW2 are switches connected to the external and internal terminals of VBL10, and SW3 is V
BL10 and a switch connected in parallel to a series connection body of both switches SW1 and SW2, 20 is a switch SW1 in a wafer state
The external VBL terminal (PAD) connected to the outer end of the VBL 10 generates the potential of the VBL 10 generated internally (VBL generation circuit) by the external VBL terminal (PAD) 20.
Can be measured above. Other transistors and signals are the same as or equivalent to those shown in FIG.
The same reference numeral as 7 is assigned and the description thereof is omitted.

External VBL terminal (PAD) 20 to VBL 10
When measuring the potential of, the switch SW1 and SW2 are closed and the switch SW3 is opened, as shown in FIG. Further, in the pre-charge state in the test mode, to check whether or not the bit line pair and the word line are short-circuited, each switch of FIG. 19 is set to the state shown in FIG. That is, the potentials of the external VBL terminal (PAD) 20 and the bit line pair are the same in the state where the switches SW1 and SW2 are opened, the switch SW3 is closed, the internal VBL generation circuit 10 is stopped, and the bit line pair is disconnected. External VBL terminal (PAD) 20 using
By applying a voltage to the external VBL pin (PAD) 20 and measuring the current flowing through it, the BL in all memory cell arrays is
With the EQ signal, it is possible to check all bit line pairs connected to VBL for a short circuit with the word line. If there is no short, the current value of the external VBL terminal (PAD) 20 is 0,
If there is a short-circuited portion, the current value will be a value other than zero. Figure 2
Data 1 indicates the result of measuring the current flowing through the external VBL terminal (PAD) 20 by applying a voltage to the external VBL terminal (PAD) 20 in the test mode. The horizontal axis represents the VBL potential applied from the outside, and the vertical axis represents the current value IBL flowing through the external VBL terminal (PAD) 20. The polarity of the current value is external V in the + direction
The current flows from the BL terminal (PAD) 20 toward the inside, and the-direction is the current flowing from the inside toward the external VBL terminal (PAD) 20.

When the measurement is performed using the above test mode, if there is no short-circuit between the plurality of bit line pairs and the word line and it is normal, the current value is 0 even if a voltage is applied to the external VBL terminal (PAD) 20. Becomes Since the internal VBL circuit 10 is stopped and the sense amplifier is also stopped, the potentials of the external VBL terminal (PAD) 20 and the bit line pair are the same. IBL is 0 because there is no element other than VBL that fixes the potential of the bit line pair. FIG. 22 shows the current path. Next, in the abnormal case where any bit line pair and any word line are short-circuited, when a voltage is applied to the external VBL terminal (PAD) 20, the IBL changes with polarity as shown in FIG. To do. IBL is 0 when VBL is 0V because all word lines are "L".
Then, it is shown that IBL increases in the + direction as the potential of VBL is increased in the + direction. FIG. 23 shows the current path. It shows a situation in which a current path is formed at a short point between a bit line pair and a word line.

As described above, it can be confirmed that there is a short circuit between the word line and the bit line pair depending on the IBL state in the test mode. However, when precharging, multiple bit line pairs
Since BL or / BL is connected to the external VBL terminal (PAD) 20, there is a problem that a defective bit line or word line cannot be specified. The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device and a test method therefor capable of identifying a short-circuited portion between a word line and a bit line pair. To do.

[0013]

A semiconductor memory device according to the present invention includes a memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix and memory cells are arranged at respective intersections. , A plurality of sense amplifiers that can be connected to each bit line pair of this memory cell array block, and a plurality of sense amplifiers that can be connected to each bit line pair through a transistor, and a predetermined potential is applied to each bit line pair at the time of connection. Is connected to the first power supply for supplying a local IO line, and also to a predetermined bit line pair by selecting a column selection line by an external address, and a predetermined potential is applied at the time of connection. A second power supply, disconnecting the first power supply from each bit line pair during precharge operation in the test mode, and supplying power to the predetermined bit line pair from the second power supply. It was applied, in which so as to identify the bit lines are short-circuited with the word line by measuring the leakage current.

The semiconductor memory device according to the present invention also includes
A first power supply includes a first internal voltage generating circuit, an external terminal of the first internal voltage generating circuit, a switch connected to the internal terminal, and an external connection connected to a switch of the external terminal. A second power source and a second internal voltage generating circuit, the first internal voltage generating circuit and another switch connected in parallel to the series connection body of both switches connected thereto. An external terminal of the second internal voltage generating circuit and a switch respectively connected to the internal terminal; a second external connecting terminal connected to a switch of the external terminal of the second internal voltage generating circuit; Between the internal voltage generating circuit of No. 2 and another switch connected in parallel to the series connection body of both switches connected to the internal voltage generating circuit, and the switch of the internal terminal of the second internal voltage generating circuit and the local IO line pair. Connected icon And the size transistor, local IO
And a transistor connected between the line pair and the bit line pair and controlled by the column line selection signal.

The semiconductor memory device according to the present invention also includes
A plurality of word lines and a plurality of bit line pairs are arranged in a matrix, and a memory cell array block in which memory cells are arranged at respective intersections, and each bit line pair of this memory cell array block can be connected. It is equipped with a plurality of sense amplifiers and a power supply adapted to be connected to each bit line pair via a transistor and applying a predetermined potential to each bit line pair at the time of connection. It connects to a bit line pair, selects a predetermined word line, applies a voltage from a power supply, and measures the leak current to identify the word line short-circuited with the bit line pair.

The semiconductor memory device according to the present invention also includes
The power supply is an internal voltage generation circuit, an external terminal of the internal voltage generation circuit and a switch respectively connected to the internal terminal, an external connection terminal connected to the switch of the external terminal, the internal voltage generation circuit and it Another switch connected in parallel relation to the series connection body of both connected switches,
An equalizing transistor connected between the other switch and the local IO line pair, and a transistor connected between the local IO line pair and the bit line pair and controlled by the column line selection signal. is there.

A semiconductor memory device testing method according to the present invention includes a memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix, and memory cells are arranged at respective intersections, and this memory. A plurality of sense amplifiers that can be connected to each bit line pair of the cell array block and a plurality of sense amplifiers that can be connected to each bit line pair through transistors, and that apply a predetermined potential to each bit line pair at the time of connection; No. 1 power source and a local IO line, and a second bit line pair which is connected to a predetermined bit line pair by selecting a column selection line by an external address and which provides a predetermined potential at the time of connection. In a semiconductor memory device including a power supply, a column line selection signal after disconnecting the first power supply from each bit line pair during a precharge operation in a test mode. Therefore, a predetermined bit line pair is selected, a voltage is applied from the second power supply to the predetermined bit line pair, and the leak current is measured to identify the bit line short-circuited with the word line. Is.

The semiconductor memory device testing method according to the present invention further includes a memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix and memory cells are arranged at respective intersections. A plurality of sense amplifiers that can be connected to each bit line pair of this memory cell array block are connected to each bit line pair through transistors, and a predetermined potential is applied to each bit line pair when connected. In a semiconductor memory device provided with a power supply for supplying, a power supply is connected to each bit line pair, a predetermined word line is selected, a voltage is applied from the power supply, and a leak current is measured during a precharge operation in a test mode. Thus, the word line short-circuited with the bit line pair is specified.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of the first embodiment, and shows the configuration corresponding to the memory cell arrays 2 and 3 and the sense amplifier C, as in FIG. Further, FIG. 2 is a timing chart during the precharge operation in the test mode. In FIG. 1, parts that are the same as or correspond to those in FIG. 17 is different from FIG. 17 in that the power supply VBL1 of the equalizing circuit is a power supply different from the internal power supply VBL, and a voltage is applied from this power supply to a specific bit line pair so that a short circuit between the word line and the bit line pair can be detected. That is the point. First, the connection between the power supply VBL1 and a specific bit line pair will be described. During the precharge operation, as shown in FIG. 2, the BLI_L and BLI_R signals are in the activated state (“H”).
Since Tr.1, Tr.2, Tr.12, and Tr.13 of FIG. 1 are turned on, the sense amplifier C and the memory cell arrays 2 and 3 are connected. BL in one memory cell array block
Transistor T with EQ signal inactive ("L")
By turning off r.10 and Tr.11, the bit line pair is disconnected from the internal power supply VBL, and the power supply VBL1 of the equalizing circuit connected to a plurality of LIO line pairs and the external address are selected.
One bit line pair connected by the CSL signal is connected via the LIO line pair. This makes it possible to specify the bit line pair connected to VBL1. The word line at that time is in a non-selected state (“L”).

FIG. 3 is a circuit configuration diagram showing a method of equalizing the bit line pair in the normal precharge operation of the first embodiment. In this figure, parts that are the same as or correspond to those in FIG. 19 are given the same reference numerals, and descriptions thereof will be omitted. Also,
Reference numeral 11 is a circuit for generating the power supply VBL1 of the equalizing circuit in FIG. A switch connected in parallel to the series connection body, and 21 is an external VBL1 terminal (PAD) connected to the outer end of the switch SW4 in a wafer state. The VBL generating circuit for generating the internal voltage VBL is connected to each bit line pair in one memory cell array block, and the internal voltage VBL1
The VBL1 generation circuit 11 for generating the transistor is a transistor Tr.14, Tr.
Connected to multiple LIO wire pairs through 15.

Since the CSL signal is in the non-selected state ("L"), the transistors Tr.5 and Tr.6 in FIG.
The generation circuit 10 and the VBL1 generation circuit 11 are separated.
The VBL generation circuit 10 and the external VBL terminal (PAD) 20 are connected, and the VBL1 generation circuit 11 and the external VBL1 terminal (PAD) 21 are connected. FIG. 4 shows a method of equalizing the bit line pairs during the precharge operation in the test mode of the first embodiment. By opening the switches SW1, SW2 and SW4, SW5 and closing the switches SW3 and SW6, the VBL generation circuit 10
Stop and are disconnected from the bit line pair. Further, the VBL1 generating circuit 11 also stops and is disconnected from the LIO line pair. One bit line pair selected (“H”) by CSL signal and external
VBL1 terminal (PAD) 21 is transistor Tr.14, Tr.15 and LIO
It will be connected through a pair of wires.

A voltage is applied from the external VBL1 terminal (PAD) 21 in order to detect a short-circuited portion between the bit line pair and the word line, and a leakage portion where a current flows to the bit line pair selected by the CSL signal. Whether there is an external VBL1
It can be determined by the current value of the terminal (PAD) 21. Figure 5
Shows the measurement results. The contents will be described later. FIG. 6 shows a current path (current does not flow) in a normal state where the word line and the selected bit line pair are not short-circuited. Selected bit line pair BL or / BL
Since there is no leak path to the word line, the external VBL1 pin
When a voltage is applied to (PAD) 21 and the current flowing through the terminal is measured, it becomes 0. This has the characteristics shown as normal in FIG. Further, FIG. 7 shows a current path in an abnormal state where the word line and the selected bit line pair are short-circuited. When a voltage is applied to the external VBL1 terminal (PAD) 21 and the current flowing through the terminal is measured, the characteristics shown in FIG. That is, when the potential of VBL1 is increased, the word line shorted through the selected bit line pair
Current flows to (0V). Therefore, during precharge operation, select the bit line pair by the external address and select the external VBL1 pin (P
By applying a voltage from AD) 21 and measuring the current value, it is possible to identify the short-circuited portion of the word line and bit line pair.

Embodiment 2. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 8 shows the second embodiment.
2 is a circuit diagram showing the configuration of FIG. 1, showing the configuration corresponding to the memory cell arrays 2 and 3 and the sense amplifier C, as in FIG. Further, FIG. 9 is a timing chart during the precharge operation in the test mode. In FIG. 8, those parts which are the same as or correspond to those in FIG. 17 are designated by the same reference numerals, and a description thereof will be omitted. In the precharge operation, BLI_L and BLI_R are in the activated state (“H”) as shown in FIG.
Since the transistors Tr.1, Tr.2, Tr.12 and Tr.13 are turned on, the sense amplifier C is connected to the memory cell array 2 and the memory cell array 3. In the second embodiment, the BLEQ signal in one memory cell array block is activated (“H”) and the transistors Tr.10 and Tr.11 are turned on, so that each bit line pair and internal power supply are turned on. The word line is selected (“H”) while being connected to VBL.

FIG. 10 is a circuit diagram showing a method of equalizing the bit line pairs during the normal precharge operation of the second embodiment. In this figure, parts that are the same as or correspond to those in FIG. 19 are given the same reference numerals, and descriptions thereof will be omitted. The VBL generation circuit 10 for generating the internal voltage VBL is connected to each bit line pair in one memory cell array block and also connected to the external VBL terminal (PAD) 20. FIG. 11 shows
FIG. 6 is a circuit configuration diagram showing an equalizing method of bit line pairs during a precharge operation in a test mode. Switch SW
By opening 1 and SW2 and closing the switch SW3, the VBL generating circuit 10 is disconnected from the bit line pair, and the bit line pair and the external VBL terminal (PAD) 20 are connected.

Apply a voltage from the external VBL terminal (PAD) 20,
By measuring the value of the current flowing from the selected word line WL to the external VBL terminal (PAD) 20, it is possible to identify the short-circuited portion between the word line and the bit line pair. FIG. 12 shows the measurement result. The contents will be described later. Figure 1
3 shows a current path in a normal state where the selected word line and the bit line pair are not short-circuited. Since the bit line pair BL or / BL is electrically floating, when a voltage is applied to the external VBL terminal (PAD) 20 and the current IBL flowing through the terminal is measured, it becomes zero. This is the characteristic shown as normal in FIG. FIG. 14 shows a current path in an abnormal state where the selected word line and the bit line pair are short-circuited. As shown in FIG. 12 when WL = “H” at the time of abnormality, when VBL is 0V, the potential difference with the shorted word line becomes the maximum, so the current IBL flowing to the external VBL terminal (PAD) 20 is inside the chip. Flow from the external VBL terminal (PAD) 20. Next, when the potential of VBL is increased, the potential difference with the shorted word line decreases, so the current decreases as shown in FIG. 12 and becomes the same as the potential of the word line with VBL shorted. Then, IBL becomes 0. In this way, at the time of precharge operation in the test mode, the word line is short-circuited with the bit line by selecting the word line and measuring the current value by applying the voltage from the external VBL terminal (PAD) 20. can do.

[0026]

According to the semiconductor memory device and the test method of the present invention, a memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix and memory cells are arranged at respective intersections, A plurality of sense amplifiers that can be connected to each bit line pair of this memory cell array block are connected to each bit line pair through transistors, and a predetermined potential is applied to each bit line pair when connected. A first power supply to be applied and a local IO line are connected, and a column select line is selected by an external address so that a predetermined bit line pair can be connected to the first power supply to give a predetermined potential at the time of connection. And a second power supply for disconnecting the first power supply from each bit line pair and supplying a predetermined bit line pair from the second power supply during the precharge operation in the test mode. Was applied, because of so as to identify the bit lines are short-circuited with the word line by measuring the leakage current, it is possible to identify the short points of word lines and bit line pairs in a wafer state. As a result, the defective word line or bit line can be replaced with a normal one, and the yield of the semiconductor memory device can be improved.

The semiconductor memory device and the test method according to the present invention further include a memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix and memory cells are arranged at respective intersections. A plurality of sense amplifiers that can be connected to each bit line pair of this memory cell array block are connected to each bit line pair through transistors, and a predetermined potential is applied to each bit line pair when connected. The bit line is connected to each bit line pair during the precharge operation in the test mode to select a predetermined word line, apply a voltage from the power source, and measure the leak current. Since the word line short-circuited with the pair is specified, the word line short-circuited with the bit line pair can be specified in the wafer state. As a result, the defective word line or bit line can be replaced with a normal one, and the yield of the semiconductor memory device can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing diagram during a precharge operation in a test mode according to the first embodiment.

FIG. 3 is a circuit configuration diagram showing a method of equalizing a bit line pair during a normal precharge operation of the first embodiment.

FIG. 4 is a circuit configuration diagram showing a method of equalizing a bit line pair during a precharge operation in a test mode according to the first embodiment.

FIG. 5 is a diagram showing measurement results of current according to the first embodiment.

FIG. 6 is an explanatory diagram showing a current path in a normal state in which a word line and a selected bit line pair are not short-circuited in the first embodiment.

FIG. 7 is an explanatory diagram showing a current path in an abnormal state in which a word line and a selected bit line pair are short-circuited in the first embodiment.

FIG. 8 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 9 is a timing diagram during a precharge operation in a test mode according to the second embodiment.

FIG. 10 is a circuit configuration diagram showing an equalizing method of a bit line pair during a normal precharge operation of the second embodiment.

FIG. 11 is a circuit configuration diagram showing an equalizing method of bit line pairs during a precharge operation in a test mode of the second embodiment.

FIG. 12 is a diagram showing current measurement results according to the second embodiment.

FIG. 13 is an explanatory diagram showing a current path in a normal state in which a selected word line and a bit line pair are not short-circuited in the second embodiment.

FIG. 14 is an explanatory diagram showing a current path in an abnormal state in which a selected word line and a bit line pair are short-circuited in the second embodiment.

FIG. 15 is a schematic diagram showing a configuration of a memory cell array block and a sense amplifier band of a conventional semiconductor memory device.

FIG. 16 is a configuration diagram including a memory cell array block, a sense amplifier band, and a signal line of a conventional semiconductor memory device.

FIG. 17 is a circuit diagram showing a configuration of a conventional semiconductor memory device.

FIG. 18 is a timing chart during operation of the conventional semiconductor memory device.

FIG. 19 is a monitor circuit using an external terminal for the VBL potential during precharging of a conventional semiconductor memory device.

FIG. 20 is a circuit diagram showing a method of detecting the presence / absence of a short circuit between a word line and a bit line pair during a precharge operation in a test mode of a conventional semiconductor memory device.

FIG. 21 is a diagram showing measurement results of current in a conventional semiconductor memory device.

FIG. 22 is an explanatory diagram showing a current path in a normal state in which a word line and a bit line pair are not short-circuited in the conventional semiconductor memory device.

FIG. 23 is an explanatory diagram showing a current path in an abnormal state in which a word line and a bit line pair are short-circuited in a conventional semiconductor memory device.

[Explanation of symbols]

2, 3 memory cell array, C sense amplifier,
10 VBL generation circuit, 11 VBL1 generation circuit,
20 External VBL terminal (PAD), 21 External VBL1 terminal (PA
D), BL_L / BL_L, BL_R / BL_R bit line pair, WL
0, WL1, WL2, WL3 Word line, LIO / LIO Local IO
Line pair, VBL, VBL1 Internal power supply.

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Claims (6)

[Claims] 1. A memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix, and memory cells are arranged at respective intersections, and each bit line pair of the memory cell array block is connected. A plurality of sense amplifiers configured to obtain, and a first power supply that supplies a predetermined potential to each bit line pair at the time of connection, and a local IO line. And a second power supply for applying a predetermined potential at the time of connection, which is connected to a predetermined bit line pair by selecting a column selection line by an external address. During the charging operation, the first power source is disconnected from each bit line pair, and a voltage is applied from the second power source to a predetermined bit line pair to measure the leak current. The semiconductor memory device being characterized in that so as to identify the bit lines are short-circuited with more word lines. 2. The first power supply includes a first internal voltage generating circuit, an external terminal of the first internal voltage generating circuit, a switch connected to the internal terminal, and an external terminal. An external connection terminal connected to the switch; and another switch connected in parallel to the first internal voltage generation circuit and a series connection body of both switches connected to the first internal voltage generation circuit, wherein the second power source comprises: A second internal voltage generation circuit,
An external terminal of the second internal voltage generating circuit and a switch connected to the internal terminal, respectively, and a second external connecting terminal connected to a switch of the external terminal of the second internal voltage generating circuit, Another switch connected in parallel to the second internal voltage generating circuit and a series connection body of both switches connected thereto, a switch of an internal terminal of the second internal voltage generating circuit, and a local IO line pair. 2. An equalizing transistor connected between the line I and line, and a transistor connected between the local IO line pair and the bit line pair and controlled by a column line selection signal. Semiconductor memory device. 3. A memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix and memory cells are arranged at respective intersections, and each bit line pair of the memory cell array block is connected. Pre-charge in a test mode, comprising a plurality of sense amplifiers configured to obtain the above-mentioned bit lines, a power supply configured to be connected to each of the bit line pairs via a transistor, and applying a predetermined potential to each bit line pair at the time of connection. At the time of operation, the power supply is connected to each bit line pair, a predetermined word line is selected, a voltage is applied from the power supply, and a leak current is measured to detect a word line short-circuited with the bit line pair. A semiconductor memory device characterized by being specified. 4. The power supply includes an internal voltage generation circuit, an external terminal of the internal voltage generation circuit, a switch connected to the internal terminal, and an external connection terminal connected to the switch of the external terminal. , Another switch connected in parallel to the internal voltage generation circuit and a series connection body of both switches connected to the internal voltage generation circuit, an equalizing transistor connected between the another switch and the local IO line pair, 4. The semiconductor memory device according to claim 3, further comprising a transistor connected between the local IO line pair and the bit line pair and controlled by a column line selection signal. 5. A memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix and memory cells are arranged at respective intersections, and each bit line pair of the memory cell array block is connected. A plurality of sense amplifiers configured to obtain, and a first power supply that supplies a predetermined potential to each bit line pair at the time of connection, and a local IO line. A semiconductor memory device having a second power supply which is adapted to be connected to a predetermined bit line pair by selection of a column selection line by an external address and which provides a predetermined potential at the time of connection. During the precharge operation in the test mode, after disconnecting the first power supply from each bit line pair, a predetermined bit line pair is selected by the column line selection signal. In addition, a voltage is applied from the second power supply to a predetermined bit line pair and the leak current is measured to identify the bit line short-circuited with the word line. Test method. 6. A memory cell array block in which a plurality of word lines and a plurality of bit line pairs are arranged in a matrix and memory cells are arranged at respective intersections, and each bit line pair of the memory cell array block is connected. In a semiconductor memory device comprising a plurality of sense amplifiers that are configured to obtain, and a power supply that is configured to be connected to each of the bit line pairs through a transistor and that applies a predetermined potential to each bit line pair at the time of connection, During the precharge operation in the test mode, after connecting the power supply to each bit line pair, selecting a predetermined word line, applying a voltage from the power supply and measuring the leak current, short-circuit the bit line pair. The method for testing a semiconductor memory device is characterized in that a specified word line is specified.