KR101616262B1 - Circuit and Method for Generating Sense Amp Enable Signal for Static RAM, and Static RAM Comprising the same Circuit - Google Patents

Abstract

A sense amplifier enable signal generating circuit and a method thereof for a static random access memory (SRAM), and a static RAM including the generating circuit are disclosed. The sense amplifier enable signal generation circuit of the present invention does not need to have a separate replica or dummy word line by using at least one cell column selected from the cell arrays of the ram as a trace cell column. The sense amplifier enable signal generation circuit of the present invention generates a tracking signal TRKBL by tracking the voltage variation in the bit line of the tracking cell column when one of the word lines is driven to a logic high to initiate a read operation, And generates a sense amplifier enable signal using the tracking signal.

Description

Technical Field [0001] The present invention relates to a sense amplifier enable signal generating circuit for a static RAM, and a static random access memory (DRAM)

The present invention is not limited to the use of actual memory cells that are operated by the original word lines, rather than replicate cells or dummy cells that partially modify the actual memory cells operating by the replicated word lines, A sense amplifier enable signal generating circuit for generating a sense amplifier enable signal by tracking voltage fluctuation, a method thereof, and a static RAM provided with the generating circuit.

The demand for high-speed access to embedded memory and low power consumption continues to grow. The same is true for the design of static random access memory (SRAM) (hereinafter referred to as "SRAM"). The high-speed access and low-power processing in SRAM is specifically related to the exact timing of the sense amplifier enable (SAE) signal that drives the sense amplifier.

In the memory reading process, if the sense amplifier is enabled too early before the bit line is fully matured, the differential voltage of the bit line pair becomes insufficient , The sense amplifier may not be able to accurately read the data value stored in the corresponding cell. Therefore, the sense amplifier enable signal must be provided in such a state that the difference voltage between the two bit lines is larger than the offset voltage of the sense amplifier.

However, if the sense amplifier is excessively delayed and enabled, not only the access time is prolonged but also the voltage difference in the bit line becomes unnecessarily large, thereby unnecessary power consumption becomes large. Considering the access time, it is good that the sense amplifier is enabled as soon as possible, but it is not desirable to enable it too early, as mentioned above. As such, the precise timing of the sense amplifier enable signal has a decisive influence on not only memory performance but also power consumption.

Of the methods for increasing the accuracy of the sense amplifier enable signal, a technique that has been attracting attention in the past is the 'replica bit line tracking (RBL) using a replica bit line (RBL)' or a 'dummy bit line Method '. In this method, a replica column or a dummy column for tracking the Variation part of the memory operation is added to the cell array, and the bit line of the replica column is referred to as a 'replica bit line (RBL)' .

The specific replica cell in the replica column is activated with a separate control signal (e.g., a separate dummy word line) so that the replica bit line RBL tracks the voltage variation of the original bit line BL as it is. Since the replica cell participating in tracking uses the original memory cell in some modification and operates under the same conditions, it is possible to generate an accurate sense amplifier enable signal despite the so-called process voltage-temperature variation ≪ / RTI > On the other hand, since a separate dummy word line must be used, all the replica cells in the replica column except for the replica cell participating in tracking are independent of tracking and are formed through a separate re-routing process in the manufacturing process.

For example, Korean Patent Publication No. 2310-0127276 (entitled " Enhanced Bit Line Tracking in High Performance Memory Compilers ") discloses a method of tracking using dummy bit lines.

Referring to FIG. 1, the memory of the present invention further includes a dummy column connected to the dummy bit line DBL in addition to the original memory cell 114, and a dummy word line DWL, which is a separate control signal, A dummy pull-down device 116, which is operated by the dummy word line DWL and the dummy bit line DBL, is also provided. The dummy pull down device 116 is a replica cell designed to operate identically to the original memory cell 114.

The dummy word line DWL is also activated when one of the word lines is activated so that the corresponding pull down device 116 is activated and the voltage of the precharged dummy bit line DBL is applied to the pull down device 116. [ Lt; / RTI > The control module 120 generates a sense amplifier enable signal at a point of time when a voltage of the dummy bit line DBL falls below a predetermined threshold voltage and a predetermined gate delay is added again. At this time, the predetermined threshold voltage for the dummy bit line is designed to be lower than the offset voltage of the sense amplifier 130, and the gate delay is adjusted to generate an accurate sense enable signal.

However, since the voltage at the bit line BL and the voltage at the dummy bit line DBL do not actually vary equally and it is difficult to match the gate delay for reasons such as the manufacturing process, the accurate timing of the sense amplifier enable signal Tracking is impossible. Meanwhile, the invention of FIG. 1 suggests a method of enabling a dummy word line before an actual word line in order to solve this problem. However, the same is true for this method, in which a separate dummy pull-down device is used which is operated by a separate dummy word line.

Since the tracking arrangements including the dummy bit line (DBL), the dummy word line (DWL), and the dummy cell are formed by the re-routing process among the recent high-integration SRAM fabrication methods, the shape of the dummy cell is different from that of the original memory cell . Therefore, in the case of the duplicate bit line scheme, there is always a problem that the dummy bit line DBL may not be able to substantially replicate the original bit line BL.

[Related Technical Literature]

1. Korean Patent Publication No. 2310-0127276 (entitled Improved Bit Line Tracking in High Performance Memory Compilers)

It is an object of the present invention to track voltage fluctuations in a bit line or a bit line bar using actual memory cells operated by original word lines without using duplicate cells or dummy cells operated by replicated word lines Thereby generating a sense amplifier enable signal for a static RAM and a method of generating the same.

It is another object of the present invention to provide a static ram having its generating circuit.

In order to achieve the above object, a sense amplifier enable signal generation circuit for a static random access memory (SRAM) according to the present invention uses a cell column selected from among the cell arrays of the RAM (hereinafter referred to as a first tracking cell column). A plurality of tracking cells of the first tracking cell column are individually accessed by a plurality of word lines for the cell array.

Accordingly, the sense amplifier enable signal generation circuit of the present invention includes the first tracking cell column, a first bit line pair disposed in the first tracking cell column and precharged, a tracking signal generation unit, .

The tracking signal generator is connected to one bit line selected from the first bit line pair. When a voltage at a node connected to the selected bit line is lower than a predetermined reference voltage A tracking signal is generated. The tracking signal generator is designed to have the reference voltage at a logic threshold voltage.

The control signal generator uses the tracking signal to generate a sense amplifier enable signal SAE.

According to an embodiment, the sense amplifier enable signal generation circuit may further utilize at least one other tracking cell column. Other tracking cell columns are also selected from the cell array and have a plurality of tracking cells that are individually accessed by the plurality of word lines. The bit lines selected from the other bit line pairs of the other tracking cell columns are also connected to the node to contribute to the tracking of the cell operation.

In this case, the sense amplifier enable signal generating circuit may further include a pass gate circuit portion for interrupting the connection between the selected bit lines of the bit line pair and the node separately from the first bit line pair have.

On the other hand, the tracking cells must be written to provide a discharge path for the selected bit line during a read operation.

As a specific example, the tracking signal generating unit may include a pull-up PMOS transistor having the gate connected to the node and turned on at the reference voltage, and an inverter for inverting the output of the drain terminal of the PMOS transistor to output the tracking signal Can be implemented.

According to another embodiment of the present invention, a control signal generating method for a static random access memory (SRAM) is disclosed. The method of the present invention is characterized in that when one word line of a plurality of word lines of the RAM is operated for a read operation of a cell, among the plurality of trace cells of the first trace cell column included in the cell array of the RAM, A first step of simultaneously accessing a tracking cell mapped to a word line; Generating a tracking signal at a time when a voltage of a selected bit line of the first bit line pair of the first tracking cell column becomes a predetermined reference voltage or less, Is recorded; And a third step of generating a sense amplifier enable signal (SAE) using the tracking signal.

On the other hand, the scope of the present invention is also applied to a static RAM having the above-described sense amplifier enable signal generating circuit.

The sense amplifier enable signal generating circuit for a static RAM according to the present invention uses a cell column selected from among the original cell arrays arranged in the memory, so there is no need to dispose a separate tracking cell. There is no need to arrange a duplicate or dummy word line since the word line for the original cell array is used as it is. Best of all, since the original cell is used intact, the tracking cell becomes a replica cell substantially identical to the original cell.

In addition, when a certain row in the memory is defective and the corresponding row is replaced with a redundancy row, the tracking cells arranged in the corresponding row may be used for tracking the cells included in the redundant row. Therefore, in the conventional method of using a plurality of separate dummy tracking cells, there is no problem that the entire memory is defective when the corresponding tracking cell is failed.

According to the present invention, since the plurality of tracking cells included in the tracking cell column are individually accessed by the original word line to participate in tracking of the cell operation, the variation according to the relative position of the cell, And the sense amplifier enable signal is less affected by processor-voltage-temperature variations. Thus, the variation of the tracking cell, which is conventionally operated by the dummy word line, with respect to the relative position with respect to the original cell is eliminated.

The sense amplifier enable signal generating circuit of the present invention can use a plurality of cell columns to freely adjust the generation timing of the sense amplifier enable signal and can also control the generation timing of the sense amplifier enable signal when the specific cell of the specific cell or its column is defective Can be replaced with any other tracing cell column.

Naturally, there is no need for a separate re-routing process for generating a dummy word line.

FIG. 1 is a cross-sectional view of the prior art shown in FIGS. 1 and 2 of Korean Patent Publication No. 2310-0127276,
2 is a conceptual diagram of a static random access memory (SRAM) having a sense amplifier enable signal generating circuit according to the present invention,
3 is a circuit diagram of a tracking signal generating unit according to an embodiment of the present invention,
Fig. 4 is a timing chart provided in the operation description of the generator circuit of Fig. 2,
5 is a circuit diagram of a tracking signal generating unit according to another embodiment of the present invention, and Fig.
6 is a conceptual diagram of a static RAM having a sense amplifier enable signal generating circuit according to another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail with reference to the drawings.

2, the static RAM 200 of the present invention includes a cell array 10, a row decoder 20, a column decoder 30, a sense amplifier 30, (Sense Amp) 50. The static RAM 200 of the present invention operates in the same manner as a normal static RAM.

For example, all the bit lines and bit line bars in the cell array 10 are precharged before the read operation. When an address and a read command are inputted from the outside for a read operation to a specific cell 11k, the row decoder 20 decodes them and the word line WLk of the cell 11k is operated Assert), and the column decoder 30 selects the corresponding column to designate the corresponding cell 11k. Here, the assertion of the word line means that the word line is driven to a logic high.

When the word line WLk operates, the isolated bit line BL-i and the bit line bar BLB-i are connected to the cell 11k. The bit line BL-i and the bit line bar BLB-i are connected to the cell 11k to generate a voltage distribution, and the bit line BL-i and the bit line BLB the sense amplifier 50 detects the differential voltage of the cell 11k and reads the value of the cell 11k.

At this time, the sense operation of the sense amplifier 50 is started by a sense amplifier enable (SAE) signal. The static RAM 200 of the present invention includes a sense amplifier enable signal generating circuit for generating a sense amplifier enable signal at an appropriate time.

The sense amplifier enable signal generation circuit is a circuit for generating a sense amplifier enable signal by using an actual memory cell operated by a original word line without using a separate dummy word line or a replica word line, Bit line bar) to generate a sense amplifier enable signal. To this end, the sense amplifier enable signal generation circuit may include at least one tracking cell column and at least one bit line pair arranged in at least one tracking cell column.

Hereinafter, when the cell array 10 has an mxn matrix structure, at least one tracking cell column included in the sense amplifier enable signal generation circuit is expressed as selected from n cell columns, but may be cell columns that are not included in the mxn cell array and are additionally disposed.

In the example of FIG. 2, the sense amplifier enable signal generation circuit includes a first trace cell column 210 and a first bit line pair BL -T1, BLB-T1). In addition, the sense amplifier enable signal generation circuit includes a precharger 230, a tracking signal generator 250, and a control signal generator 270.

The first tracking cell column 210 is selected from the cell array 10 of the static RAM 200 and tracks the variation in operation of the static RAM 200. Since the first tracking cell column 210 is generated at the same time in the same process as the production of the other cell columns of the manufacturing normal cell array 10, when the cell array 10 has an m × n matrix structure 1 tracking cell column 210 includes m tracking cells including tracking cells 210a through 210m.

Each of the tracking cells 210a to 210m of the first tracking cell column 210 is accessed and operated by the original word lines WL0 to WLm for the cell array 10 so that the tracking cells used for tracking 210k belong to the same row as the cell 11k in which the current read operation is performed, so that tracking of the corresponding cell 11k becomes more practical. For example, since the distance between the tracking cell 210k and the tracking signal generator 250 and the distance between the actually operating cell 11k and the sense amplifier 50 are almost the same, the variation tracking of the operation is more practical Effectively.

The first bit line pairs BL-T1 and BLB-T1 arranged in the first tracking cell column 210 are not connected to the column decoder 30. [ And is connected to the tracking signal generator 250 via the precharger 230.

However, only one bit line selected from the first bit line pairs BL-T1 and BLB-T1 of the first tracking cell column 210 is used as a tracking signal generating unit 250 based on the tracking signal generating unit 250, And it may be any bit line of the first bit line pair BL-T1, BLB-T1. Accordingly, the remaining one that does not participate in the tracking of the tracking signal generator 250 is always driven to the logic high state. FIG. 2 shows an example in which the first bit line BL-T1 is connected to the tracking signal generator 250. FIG.

The tracking cells of the first tracking cell column 210 must have data written to provide a discharge path for the selected bit line. For example, when the first bit line BL-T1 contributes to the generation of the tracking signal, since the tracking signal generator 250 tracks the voltage variation in the first bit line BL-T1, Each of the tracking cells 210a through 210m of the column 210 must have a logic '0' value before entering a read operation. To this end, a logic '0' is written to each of the tracking cells 210a to 210m of the first tracking cell column 210 when the word line for a writing operation is operated, The circuit may further include a circuit for turning the bit line BL-T1 to ground, or a circuit for writing the tracking cells 210a to 210m collectively to a logic 0 using an initialization signal during power- As shown in FIG.

Conversely, when the first bit line bar BLB-T1 contributes to the generation of the tracking signal, since the tracking signal generator 250 tracks the voltage variation in the first bit line bar BLB-T1, Each of the tracking cells 210a through 210m of the column 210 must have a logical '1' value before entering a read operation. To this end, a logic '1' is written to each of the tracking cells 210a to 210m of the first tracking cell column 210 when the word line for the writing operation is operated, It may further comprise a circuit for making the bit line bar BLB-T1 logic-low.

The precharger 230 precharges the first bit line pair BL-T1 and BLB-T1 according to the initialization signal. However, the 'selected bit line' among the first bit line pairs BL-T1 and BLB-T1 is precharged in conjunction with the initialization signal, but the remaining one bit line is always kept at a logic high. For example, as shown in FIG. 2, when the first bit line BL-T1 is selected, the first bit line bar BLB-T1 is always driven to logic high without being interlocked with the initialization signal.

Here, the initialization signal may be a so-called equalization signal (BLEQ) or the like. The first bit line BL-T1 is precharged in the same manner as the normal cell column 11 of the cell array 10 is precharged by using the equalization signal BLEQ.

2, the precharger 230 includes a first inverter 231 for inverting the equalization signal BLEQ, a PMOS transistor 233 connected to the first bit line BL-T1, And a PMOS transistor 235 connected to the bar BLB-T1. The output of the first inverter 231 is connected to the gate of the PMOS transistor 233 and the power source voltage Vdd is applied to the source terminal and the first bit line BL- Is coupled such that the first bit line BL-T1 is precharged to logic high only when the equalization signal BLEQ is a logic high. The power source voltage Vss (Vss << Vdd, Vss is generally ground) is connected to the gate of the PMOS transistor 235, the power source voltage Vdd is applied to the source terminal, the first bit line bar (BLB-T1) So that the first bit line bar BLB-T1 is always precharged to a logic high.

The tracking signal generator 250 is connected to the 'selected bit line' via the node a and tracks the voltage variation in the selected bit line during the read operation.

In the example of FIG. 2, the tracking signal generator 250 is connected to the first bit line BL-T1 through the node a, and when one of the word lines WL0 to WLm is operated for a read operation And tracks voltage variations at node (a) connected to the precharged first bit line (BL-T1). When a word line is operated, a first bit line (BL-T1) is connected to a tracking cell, a voltage drop occurs between the first bit line (BL-T1) and a tracking cell, The unit 250 generates the tracking signal TRKBL when the voltage of the first bit line BL-T1 falls to a predetermined reference voltage.

Here, the reference voltage should be designed so that the timing of generation of the tracking signal TRKBL reaches the voltage difference target value of the data line (Target Delta DL in FIG. 4), and can be implemented using the PMOS or the threshold voltage of the NMOS transistor have.

The tracking signal generator 250 provides the generated tracking signal TRKBL to the control signal generator 270.

FIG. 3 shows the structure of a basic tracking signal generator 250. Referring to FIG. 3, the tracking signal generator 250 includes a pull-up PMOS transistor 401. The first bit line BL-T1 is connected to the gate of the pull-up PMOS transistor 401 through the node a, and the drain terminal outputs the primary tracking signal TRKBL_N. At this time, the reference voltage tracked by the tracking signal generator 250 is generated by the threshold voltage of the PMOS transistor 401. For example, when the voltage difference target value of the data line is 300V, the threshold voltage of the PMOS transistor 401 is preferably Vdd-300V.

The tracking signal generator 250 may include a second inverter 403 and an NMOS transistor 405a to drive the primary tracking signal TRKBL_N. NPOS transistor 405a is controlled by an initialization signal (e.g., BLEQ) input to the gate terminal.

The second inverter 403 inverts the primary tracking signal TRKBL_N to finally output the tracking signal TRKBL. When the read operation ends, the pull-down NPOS transistor 405a is turned on again to return the primary tracking signal TRKBL_N back to logic low.

The control signal generator 270 generates various control signals using the tracking signal TRKBL. For example, during a read operation, the control signal generator 270 generates a sense amplifier enable signal SAE that drives the sense amplifier 50 using the tracking signal TRKBL.

<Read operation of the sense amplifier enable signal generation circuit: Fig. 4>

Hereinafter, the operation of the sense amplifier enable signal generation circuit will be described focusing on the operation of the tracking signal generation unit 250 in the read operation with reference to FIG. The operation of FIG. 4 will be described mainly on the reading process of the general cell 11k including the cell array 10. FIG.

The bit line BL-i and the bit line bar BLB-i of the general cell 11k are precharged by the equalizing signal BLEQ in the logic high state as in the normal reading operation. The first bit line pairs BL-T1 and BLB-T1 are also precharged to a logical high by the precharger 230. However, the first bit line BLB-T1 always maintains a logic high state, and the first bit line BL-T1 is precharged as the equalization signal BLEQ returns to logic high.

To start the read operation, the word line WLk is operated immediately after the equalization signal BLEQ becomes logic low at the logic high state, and the bit line BL-i and the bit line bar BLB-i are connected to the cell And a voltage difference is generated between the bit line BL-i and the bit line BLB-i, as shown in FIG. 4, The voltage difference also occurs in the line DL and the data line bar DLB. It is most preferable that the sense amplifier enable signal is activated when the voltage difference target value (Target Delta DL) of the data line is reached and the sense amplifier 50 is sensed.

When the word line WLk is operated, the first bit line BL-T1 of the first tracking cell column 210 is also connected to the tracking cell 210k, and the first bit line BL- The voltage begins to drop as the voltage is distributed to the tracking cell 210k. The PMOS transistor 401 of the tracking signal generator 250 starts to turn on according to the voltage of the first bit line BL-T1, and the voltage of the first bit line BL- And generates a first tracking signal TRKBL_N which is a logic high when the threshold voltage is completely turned on and a second inverter 403 inverts the first tracking signal TRKBL_N to generate a logic low tracking signal TRKBL .

Thereafter, the control signal generator 290 generates a sense amplifier enable signal to the sense amplifier 50 so that the sense amplifier 50 can sense the voltage difference between the data line DL and the data line bar DLB Delta DL). The word line pulse (Word Line Pulse) can also be converted to a logic low according to the tracking signal TRKBL.

It is necessary to appropriately adjust the timing at which the sense amplifier 50 is operated in consideration of the fact that it is difficult to accurately match the data line voltage difference target value (Target Delta DL) with the threshold voltage of the PMOS transistor 401 in practice. The tracking reference voltage of the tracking signal generator 250 can be adjusted as shown in FIG. 5 in order to advance the time when the sense amplifier 50 is operated.

&Lt; Other Embodiments of the Tracking Signal Generation Unit: Fig. 5 &

5, the tracking signal generator 250 includes, in addition to the pull-up PMOS transistor 401 and the second inverter 403, at least one of the PMOS transistors 401 and 403 disposed between the drain terminal of the PMOS transistor 401 and the ground. Down NPOS transistor 405 to adjust the logic threshold voltage of the tracking signal generator 250. [

5 shows an example having two cascade-connected NMOS transistors 405a and 405b. NPOS transistors 405a and 405b are controlled by an initialization signal (for example, BLEQ) input to the gate terminal. During the read operation, the pull-down NPOS transistors 405a and 405b are turned off to increase the logic threshold voltage so that the time point at which the PMOS transistor 401 is turned on is advanced. Thus, even if the voltage drop rate at the first bit line BL-T1 is the same, the PMOS transistor 401 is turned on earlier and the primary tracking signal TRKBL_N and the tracking signal TRKBL are also generated sooner .

According to an embodiment, PMOS transistors 407 and 409 may be further included between the input of the second inverter 403 and the power supply voltage Vdd. The PMOS transistor 407 is controlled by the equalization signal BLEQ connected to the gate terminal, and the PMOS transistor 409 controls the tracking signal TRKBL by feeding back the signal to the gate terminal. The PMOS transistors 407 and 409 accelerate the low enable timing of the tracking signal TRKBL.

&Lt; Method of using a plurality of tracking cell columns: Fig. 6 &

As described above, the sense amplifier enable signal generation circuit of the present invention can use a plurality of trace cell columns. In this case, the voltage drop rate at the node (a) becomes faster, and the timing at which the sense amplifier enable signal SAE is generated is advanced.

Referring to FIG. 6, the sense amplifier enable signal generation circuit of the present invention further includes a second tracking cell column 211 in addition to the first tracking cell column 210.

The second tracking cell column 211 is also selected from the cell array 10 of the static RAM 200 in the same manner as the first tracking cell column 210 so that the variation portion of the operation of the static RAM 200 Track. Since the second tracking cell column 211 is generated at the same time in the same process as the other cell columns of the manufacturing normal cell array 10 at the same time, when the cell array 10 has an m × n matrix structure 2 tracking cell column 211 includes m tracking cells including tracking cells 211a, 211i, and 211m. Each trace cell 211a, 211i and 211m of the second trace cell column 211 is also accessed and operated by the original word lines WL0 to WLm for the cell array 10. [ And the second bit line pair BL-T2 and BLB-T2 are arranged in the second tracking cell column 211.

One of the second bit line pairs BL-T2 and BLB-T2 is connected to the node a and is connected to the tracking signal generating unit 250 to contribute to generation of the tracking signal TRKBL. However, if the first bit line BL-T1 is connected to the node a in the first tracking cell column 210, the second bit line BL-T2 of the second tracking cell column 211 is connected to the node a and if the first bit line bar BLB-T1 in the first tracking cell column 210 is connected to the node a, then in the second tracking cell column 211, It is preferable for the operation control that the bar BLB-T2 is connected to the node a.

In FIG. 6, the first bit line BL-T1 and the second bit line BL-T2 are connected to the common node a. At this time, the first bit line bar BLB-T1 and the second bit line bar BLB-T2 must be maintained at a logic high level at all times, and they are preferably connected to each other.

Accordingly, as indicated by a dotted line in FIG. 4, the voltage at the node a, that is, the voltage at the first bit line BL-T1 also falls to a greater slope than in FIG. 2, The PMOS transistor 401 is also turned on earlier and the primary tracking signal TRKBL_N and the tracking signal TRKBL are generated more quickly.

According to the embodiment, the sense amplifier enable signal generation circuit includes a pass gate circuit portion 601 (hereinafter, referred to as &quot; pass gate circuit portion &quot;) for intermittently interrupting bit lines (bit line bars in accordance with an embodiment) , 603). The pass gate circuit portions 601 and 603 are controlled by separate control signals Opt 1 and Opt 2. For example, in FIG. 6, when the connection between the second bit line BL-T2 and the node a is cut off by the control signal Opt 2, the second bit line bar BLB- (Flotting) state, and the circuit of Fig. 6 operates in the same manner as the circuit of Fig.

The pass gate circuit units 601 and 603 applied when using a plurality of tracking cell columns can advance or delay the timing of generating the sense amplifier enable signal by controlling the number of tracking cell columns connected to the node a . Alternatively, some tracer cell columns may be reserved, in case some tracer cell columns are defective.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (10)

A sense amplifier enable signal generation circuit for a static random access memory (SRAM) having a cell array,
A first tracking cell column selected from the cell array and having a plurality of tracking cells individually accessed by a plurality of word lines for the cell array;
A first bit line pair disposed in the first tracking cell column and precharged;
Wherein the first bit line pair is connected to one bit line selected from the first bit line pair, and when one of the word lines is operated for a read operation, a voltage at a node connected to the selected bit line becomes less than a predetermined reference voltage, A tracking signal generator for generating a signal; And
And a control signal generator for generating a sense amplifier enable signal (SAE) using the tracking signal.
The method according to claim 1,
At least one other tracking cell column having a plurality of tracking cells selected from the cell array and accessed individually by the plurality of wordlines; And
Further comprising another bit line pair disposed and precharged in the other tracking cell column,
And one bit line selected from the other bit line pairs is also coupled to the node.
3. The method of claim 2,
Further comprising a pass gate circuit portion for interrupting the connection between the selected bit lines of the bit line pair and the node separately from the first bit line pair. Circuit.
The method according to claim 1,
Wherein the tracking cells are written with data to provide a discharge path for the selected bit line during a read operation.
The method according to claim 1,
Wherein the tracking signal generator comprises:
Wherein the reference voltage is a logic threshold voltage.
6. The method of claim 5,
Wherein the tracking signal generator comprises:
A pull-up PMOS transistor having the node connected to the gate terminal and turned on at the reference voltage; And
And an inverter for inverting the output of the drain terminal of the PMOS transistor and outputting the tracking signal.
A method of generating a sense amplifier enable signal for a static random access memory (SRAM)
Wherein when one word line of the plurality of word lines of the RAM is operated for a read operation of the cell, the plurality of trace cells of the first trace cell column included in the cell array of the RAM are mapped to the operated word line A first step of simultaneously accessing a tracking cell;
Generating a tracking signal at a time when a voltage of a selected bit line of the first bit line pair of the first tracking cell column becomes a predetermined reference voltage or less, Is recorded; And
And a third step of generating a sense amplifier enable signal (SAE) using the tracking signal.
8. The method of claim 7,
The first step is to access a tracking cell mapped to the operated word line among a plurality of tracking cells of at least one other tracking cell column included in the cell array of the RAM,
The second step generates the tracking signal at a time point when the voltage of the selected one of the first bit line pair and the common node of the selected bit line pair of the bit line pair of the other tracking cell column becomes equal to or lower than the reference voltage ,
Wherein data is written to the trace cells of the other trace cell columns to provide a discharge path for the selected bit line.
9. The method of claim 8,
Wherein the connection between the selected bit lines of the bit line pair and the common node is interrupted separately from the first bit line pair.
1. A static RAM having a cell array controlled by a plurality of word lines,
And a sense amplifier enable signal generating circuit for generating a sense amplifier enable signal for controlling the sense amplifier,
The sense amplifier enable signal generation circuit includes:
A first tracking cell column selected from the cell array and having a plurality of tracking cells that are individually accessed by the plurality of wordlines;
A first bit line pair disposed in the first tracking cell column and precharged;
Wherein the first bit line pair is connected to one bit line selected from the first bit line pair, and when one of the word lines is operated for a read operation, a voltage at a node connected to the selected bit line becomes less than a predetermined reference voltage, A tracking signal generator for generating a signal; And
And a control signal generator for generating the sense amplifier enable signal (SAE) using the tracking signal.

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