CN101764159B - 带有减小的击穿电压的金属氧化物半导体场效应管器件 - Google Patents

带有减小的击穿电压的金属氧化物半导体场效应管器件 Download PDF

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CN101764159B
CN101764159B CN200910260507XA CN200910260507A CN101764159B CN 101764159 B CN101764159 B CN 101764159B CN 200910260507X A CN200910260507X A CN 200910260507XA CN 200910260507 A CN200910260507 A CN 200910260507A CN 101764159 B CN101764159 B CN 101764159B
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semiconductor device
epitaxial loayer
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CN101764159A (zh
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潘继
安荷·叭剌
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明涉及一种半导体器件，其特征在于，包含一个漏极、一个覆盖在漏极上的外延层、一个有源区；上述有源区包含：一个沉积在外延层中的主体、一个嵌入主体内的源极、一个延伸进外延层的栅极沟道、一个沉积在栅极沟道中的栅极、一个沿源极和至少一部分主体延伸的接触沟道、一个沉积在接触沟道中的接触电极、一个沉积在接触沟道下面的外延增强部分；外延增强部分的载流子类型与外延层的一致。本发明通过一个沉积在器件的接触沟道下面的外延层增强部分，减小了金属氧化物半导体场效应管器件的击穿电压。

Description

带有减小的击穿电压的金属氧化物半导体场效应管器件
技术领域
本发明涉及一种半导体器件，特别涉及一种带有减小的击穿电压的金属氧化物半导体场效应管器件。
背景技术
当今的半导体器件，例如金属氧化物半导体场效应管，一般都是特征尺寸很小的高密度器件。比如，现在使用的某些金属氧化物半导体场效应管的壁-壁尺寸约为1到2微米。随着器件尺寸的减小，器件内栅极氧化物的厚度也随之减小，并且在使用过程中更易受到损坏。这种问题在经常传导大电流、消耗大功率的功率金属氧化物半导体场效应管器件中将变得更加显著。
发明内容
本发明的目的在于提供一种半导体器件，通过一个沉积在器件的接触沟道下面的外延层增强部分，减小了金属氧化物半导体场效应管器件的击穿电压。
为了达到上述目的，本发明的技术方案是提供一种半导体器件，其特征在于，包含一个漏极、一个覆盖在漏极上的外延层、一个有源区；
上述有源区包含：
一个沉积在外延层中的主体、
一个嵌入主体内的源极、
一个延伸进外延层的栅极沟道、
一个沉积在栅极沟道中的栅极、
一个沿源极和至少一部分主体延伸的接触沟道、
一个沉积在接触沟道中的接触电极、
一个沉积在接触沟道下面的外延增强部分；
上述外延增强部分的载流子类型与外延层的一致。
上述外延增强部分用于降低由接触电极和漏极形成的肖特基二极管的击穿电压。
上述外延增强部分的载流子浓度比外延层的载流子浓度要高。
上述有源区还包括一个沉积在接触沟道侧壁上的主体接触植入物。
上述有源区还包括一个沉积在接触沟道侧壁上的主体接触植入物，上述主体接触植入物的载流子类型与外延层相反。
上述有源区还包括一个沉积在接触沟道侧壁上的主体接触植入物和一个沿接触沟道底部沉积的二极管增强层，而且在上述二极管增强层下面沉积外延增强部分。
上述有源区还包括沉积在接触沟道下面和外延增强部分上面的香农植入物，上述香农植入物的载流子类型与外延层的相反。
上述半导体器件的壁-壁间距尺寸小于或等于1.4微米。
上述外延层和外延增强部分为N型。
上述外延层和外延增强部分为P型。
一种半导体器件的制作方法，其特征在于，包含以下步骤：
在外延层中制造一个栅极沟道，覆盖在半导体衬底上；
在栅极沟道内沉积栅极材料；
在外延层中制造一个主体；
制造一个源极嵌入主体；
制造一个沿源极和至少一部分主体延伸的接触沟道；
在接触沟道下面沉积一个外延增强部分，其中外延增强部分的载流子类型与外延层的一致；
在接触沟道中沉积一个接触电极。
上述外延增强部分用于降低由接触电极和漏极形成的肖特基二极管的击穿电压。
上述外延增强部分的载流子浓度要高于外延层的载流子浓度。
上述一种半导体器件的制作方法，还包括在接触沟道的侧壁上沉积一个主体接触植入物。
上述一种半导体器件的制作方法，还包括在接触沟道的侧壁上沉积一个主体接触植入物，上述主体接触植入物的载流子类型与外延层的相反。
上述一种半导体器件的制作方法，还包括在接触沟道的侧壁上沉积一个主体接触植入物，并沿接触沟道底部形成一个二极管增强层；上述外延增强部分沉积在二极管增强层之下。
上述一种半导体器件的制作方法，还包括在接触沟道下面和外延增强部分上面沉积香农植入物，上述香农植入物的载流子类型与外延层相反。
上述半导体器件的壁-壁间距尺寸小于或等于1.4微米。
上述主体的制作包括制作一个光致抗蚀主体块，并通过光致抗蚀主体块在未掩膜区内植入主体。
上述主体的制作包括制作一个主体层，并进行接触刻蚀。
本发明所述的带有减小的击穿电压的金属氧化物半导体场效应管器件，与现有技术相比，其优点在于：本发明通过一个沉积在器件的接触沟道下面的外延层增强部分，减小了金属氧化物半导体场效应管器件的击穿电压。
附图说明
图1A至1B是本发明所述带有减小的击穿电压的双扩散金属氧化物半导体器件实施例的横截面示意图；
图2是本发明制作一个双扩散金属氧化物半导体器件的实施例流程图；
图3A至3S是本发明所述金属氧化物半导体场效应管器件的一种制作过程横截面示意图；
图4K至4S是本发明所述金属氧化物半导体场效应管器件的另一种制作过程横截面示意图。
具体实施方式
本发明具有多种应用形式，包括用于加工过程、器件、系统、合成物质、嵌入计算机可读存储介质中的计算机程序产品，以及/或处理器，例如执行存储指令和/或由耦合到处理器上的内存配置的处理器。本说明书中，这些实施例，或本发明的其他任意应用形式，都可能会作为技术内容所提及。一般而言，所述的加工过程的顺序可能有所不同，但仍属本发明的范围。除非另加说明，用作其他用途的处理器或内存等元件，可以制作成通用元件，用于特定时间的临时加工任务或用作其他用途的特殊元件。此处提到的名词“处理器”涉及一种或多种器件、电路与/或处理核，用于处理计算机程序指令等数据。
以下将详细介绍本发明的一个或多个实施例，以及用于解释说明的附图。文中提出了本发明有关的多个实施例，但本发明并不局限于任一实施例。本发明的范围仅由权利要求书和本发明涵盖的各种变化、修改和等效的内容所决定。为了对本发明进行完整说明，以下还将详细介绍多个具体示例。这些示例仅用作举例说明，依据权利要求书，无需这些具体示例中的任何一个或全部示例，本发明仍可实施。
本发明提出了一种带有减小的击穿电压的半导体器件。在一些实例中，器件包括一个沉积在器件的接触沟道下面的外延层增强部分，以便减小器件的击穿电压。这个外延层增强部分具有和外延层相同的载流子类型。可选择包括体接触植入物或香农植入物。
图1A表示带有减小的击穿电压的双扩散金属氧化物半导体器件的一个实施例的横截面视图，该器件100包括一个在N+型半导体衬底103背面的漏极。漏极区域延伸进入N-型半导体的外延层104，与衬底103重叠。在外延层104中刻蚀出111、113、115等栅极沟道。在栅极沟道内形成栅极氧化层121。栅极131、133和135分别沉积在栅极沟道111、113和115中，并通过氧化层与外延层隔绝。栅极由多晶硅等导电材料构成，氧化层由热氧化物等绝缘材料构成。更确切地说，栅极沟道111位于终止区，并带有栅极引线131用于连接栅极的接触金属。正因如此，栅极引线沟道111可以比有源栅极沟道113和115更宽、更深。另外，栅极引线沟道111与它旁边的有源沟道113之间的距离，要比有源栅极沟道113和115之间的距离大。
源极区域150a到150d被分别埋入主体区140a到140d内。源极区域从主体上表面一直向下延伸到主体内。当主体区沿所有的栅极沟道的边缘植入时，源极区域仅仅在有源栅极沟道的邻近位置植入，而不是栅极引线沟道的附近。在所给出的实施例中，栅极，比如133，具有一个栅极顶面，这个顶面超出了带有源极嵌入的主体顶面。这种结构保证了栅极和源极重叠，使得源极区域比具有凹陷栅极器件的源极区域浅，增加了器件效率和性能。栅极多晶硅顶面延伸至源极-主体结上方的量，对于不同的实施例，可能有所不同。在某些实施例中，器件的栅极并没有延伸至源极-主体区域的顶面上方。
在制备过程中，漏极区域和主体区域都是一个二极管，称为体二极管。绝缘材料层160沉积在栅极上，使得栅极与源极-主体接触区绝缘。绝缘材料在栅极的顶部以及主体和源极区域的顶部，形成了类似于160a到160c的绝缘区。热氧化物、低温氧化物(LTO)、硼磷硅玻璃(BPSG)等都可作为这种绝缘材料。
在源极附近的有源栅极沟道和主体区域之间，形成了多个接触沟道112a到112b。由于这些沟道邻近器件源极和主体区形成的有源区，因此它们也被称为有源区接触沟道。例如，接触沟道112a延伸穿过源极和主体，在沟道附近形成了源极区域150a到150b和主体区域140a到140b。与之相反，在栅极引线131顶部形成的沟道117，并不邻近有源区，因此它就不是有源区接触沟道。又因为连接栅极信号的金属层172a沉积在沟道117内，因此沟道117被称为栅极接触沟道或栅极引线接触沟道。通过沟道111、113和115之间的三维互联(图中没有给出)，栅极信号被送往有源栅极133和135。金属层172a与金属层172b分离，172b通过接触沟道112a到112b将源极和主体区域连接起来，作为功率源极。在本例中，有源区接触沟道和栅极接触沟道的深度大致相同。
在本例中，主体内的和沿有源区接触沟道壁的区域，如170a到170d，都是重掺杂P型材料，形成P+型区域，也就是主体接触植入物。之所以引入主体接触植入物是为了保证在主体和源极金属之间形成欧姆接触，使得源极和主体之间的电势一致。
将导电材料沉积在接触沟道112a到112b和栅极接触沟道117中，以便形成接触电极。在有源区，接触电极和漏极区域形成与主体二极管并联的肖特基二极管。肖特基二极管降低了主体二极管的正向电压降，并使累计电荷最少，这就使得金属氧化物半导体二极管的效率更高。用于制备电极180a到180b的单一金属矿石，可以形成N-漏极的肖特基接触、同时对P+主体和N+源极有良好的欧姆接触。可以使用金属钛(Ti)、铂(Pt)、钯(Pd)、钨(W)等或其他合适的金属。在某些实施例中，使用金属铝(Al)或Ti/TiN/Al栈制备金属层172。
传统的功率金属氧化物半导体场效应管器件中，在接触电极和漏极之间形成的肖特基二极管的击穿电压一般与体二极管的击穿电压一样高。在击穿之前，在器件的栅极底部附近会形成一个很大的电场，对栅极氧化层造成损害。在器件100中，通过在接触沟道112a和112b下面，植入物和外延层具有相同载流子类型的掺杂剂，降低了器件的击穿电压。产生的外延层增强部分(也称为击穿电压降低植入物)182a和182b具有与外延层相同的载流子类型，但浓度更高。在本例中，外延层的载流子类型为N型(也就是说，电子为多数载流子，空穴为少数载流子)，外延层增强部分也为N型。在外延层载流子类型为P型(也就是说，电子为少数载流子，空穴为多数载流子)的实施例中，外延层增强部分也为P型。外延层增强植入物降低了在接触电极和漏极之间形成的肖特基二极管的击穿电压。由于肖特基二极管和体二极管并联，并且肖特基二极管的击穿电压更低，因此器件的总击穿电压将降低。如果建立起了大电场，肖特基二极管首先被击穿，通过传导电流消耗电荷，这就阻止了电场对栅极氧化层造成损害。下文将详细讨论外延层增强植入物的形成。外延层增强植入物的厚度和浓度由所需的击穿电压决定，外延层增强植入物的厚度越大、浓度越浓，相应的击穿电压会越低。本例中，包含外延层增强部分后，器件的击穿电压从38V降至22V。
图1B表示带有减小的击穿电压的双极金属氧化物半导体器件实施例的横截面视图，该器件102与器件100，除了P-材料185a和185b的薄层分别在接触沟道112a和112b下面直接形成之外，其他方面均类似。在接触沟道112a和112b的底面下方的体/漏结处形成低注入二极管，并不形成肖特基二极管。P-材料的上述薄层提高了低注入二极管的正向电压降(Vfd)，降低了漏电流，因此也称为二极管增强层。下文将详细介绍，在某些实施例中，二极管增强层的处理过程与体接触植入的处理过程相同。二极管增强层的掺杂浓度远低于体接触植入区170a到170d的掺杂浓度，因此当反向偏置时，二极管增强层完全耗尽，耗尽层相当高，使得当正向偏置时，二极管增强层没有耗尽。二极管增强层的厚度由所需的低注入二极管正向电压的变化量决定，层的厚度越大，正向电压降越大。
与器件100类似，器件102也植入了具有和外延层一样的载流子类型的掺杂物。它所产生的外延层增强部分(也就是击穿电压降低植入物)182a和182b形成于二极管增强层185a和185b下面，其载流子类型也与外延层相同，但浓度更高，以减小低注入二极管的击穿电压，这就阻止了电场对栅极氧化层造成损害。
上述实施例是将N型衬底(即在晶片上生成一层带有N-外延层的N+硅片)作为器件的漏极。在某些实施例中使用的是P型衬底，并且器件带有N型体接触植入物与P型外延层增强层。
图2表示制备一种双极金属氧化物半导体器件的处理过程实施例的流程图。在步骤202，在外延层中形成与半导体衬底重叠的栅极沟道。在步骤204，将栅极材料沉积在栅极沟道中。在步骤206，形成主体。在步骤208，形成源极。在步骤210，形成接触沟道。在步骤212，形成体接触植入物。在步骤214，形成外延层增强层。在步骤216，在接触沟道内沉积接触电极。工序200及其步骤只要稍作修改，就能用于制备上述的100和102等不同的金属氧化物半导体器件。
图3A至3S为器件的横截面示图，说明用于制备金属氧化物半导体场效应管器件的一种制作过程。图3A至3J表示栅极的形成。
在图3A中，在N型衬底300上，通过沉积或热氧化，形成了一个SiO2层302。根据不同的实施例中，二氧化硅层的厚度在到
Figure G200910260507XD00072
之间变化。也可以使用其他的厚度值，这取决于栅极所需的高度。在氧化层上面旋涂一个感光层304，并用沟道掩膜形成图案。
在图3B中，除去曝光区中的SiO2，剩余的SiO2硬膜310用于硅刻蚀。图3C中，异向刻蚀硅。栅极材料沉积在沟道中。然后在沟道内形成的栅极，栅极的边缘垂直于衬底顶面。图3D中，适量回蚀SiO2硬膜310，刻蚀后，使沟道壁与硬膜的边缘对齐。本实施例中，使用SiO2作为掩膜材料，是因为用SiO2硬膜刻蚀之后的沟道壁比较直，沟道壁与掩膜的边缘相互对齐。也可以选用其他合适的材料。通常使用的Si3N4等其他类型的材料用于硬膜刻蚀，必定会使刻蚀后的沟道壁产生弯曲，这对于接下来形成栅极不利。
图3E中，异向刻蚀衬底，使沟道的底部变得圆滑。在一些实施例中，沟道深约0.5到2.5μm、宽约0.2到1.5μm，也可选用其他尺寸。为了使表面平滑，便于生成栅极介电材料，要在沟道中生生成一个牺牲层SiO2330。然后通过湿法刻蚀除去该层。图3G中，SiO2层332作为介电材料，在沟道中热生成。
图3H中，沉积聚乙烯340填满沟道。在这种情况下，通过掺杂聚乙烯，获得合适的栅极阻抗。在一些实施例中，在(原位)沉积聚合物层时，开始掺杂。在另一些实施例中，沉积完聚合物后，开始掺杂聚乙烯。如图3I，回蚀SiO2顶部的聚乙烯层，形成类似于342的栅极。在这一点上，栅极的顶面344相对于SiO2的顶面348来说仍然是凹陷的；但是栅极的顶面344可能比硅的顶面346要高，这取决于硬膜层310的厚度。在一些实施例中，聚合物回蚀中并没有使用掩膜。另一些实施例中，是在聚合物回蚀中使用掩膜，以便在接下来的主体植入过程中不再使用额外的掩膜。如图3J，除去SiO2硬膜。在一些实施例中，使用干法刻蚀除去硬膜。遇到硅的顶面时，停止刻蚀，使聚合物栅极在衬底表面上延伸，源极和体掺杂物将被植入衬底中。在另一些实施例中，栅极在衬底表面上方延伸大概
Figure G200910260507XD00081
到
Figure G200910260507XD00082
之间，也可以选用其他值。由于SiO2硬膜以一种可控的方式，提供所需的在硅表面上的栅极延伸量，因此在这些实施例中都使用SiO2硬膜。然后屏蔽氧化层在晶片上生成。可以通过简化上述制备过程，制造带有减小的栅极聚合物的器件。例如在一些实施例中，可使用光致抗蚀剂掩模或非常薄的SiO2硬膜制备沟道，于是生成的栅极聚合物并不在硅表面上延伸。
图3K至3N表示源极和主体的形成。如图3K所示，光致抗蚀层350通过主体掩膜刻蚀在主体表面。由于光致抗蚀模块掺杂物从掩膜区中被植入，因此带图案的光致抗蚀层也称为主体模块。未掩膜的区域同主体掺杂物一起植入。植入的掺杂物包括硼离子等。如图3L所示，除去光致抗蚀层，加热晶片，以使植入的主体掺杂物热扩散，这个过程有时也叫做主体驱动。形成主体区域360a到360d。在一些实施例中，用于植入主体掺杂物的能量约为30到600KeV，剂量约为每平方厘米2e12到4e13个离子，最终生成的主体厚度约为0.3到2.4微米。可以通过改变植入能量、剂量以及扩散温度等参数，获得不同的主体厚度。在扩散过程中，形成了氧化层362。
如图3M所示，使用源极掩膜在光致抗蚀层364上形成图案。所给的实施例中，源极掩膜364并不阻塞有源沟道之间的任何区域。在一些实施例中，源极掩膜364阻塞了有源沟道之间的中心区域(图中没有给出)。未掩膜的区域366同源极掺杂物一起植入。在本例中，砷离子渗入硅中的未掩膜区，形成N+型源极。在另一些实施例中，用于植入源极掺杂物的能量约为10到100KeV，剂量约为每平方厘米1e15到1e16个离子，最终生成的主体厚度约为0.05到0.5微米。可以通过改变掺杂能量和剂量等参数进一步减薄厚度。也可以选用其他合适的植入工艺。如图3N所示，除去光致抗蚀层，加热晶片，通过源极驱动过程，使植入的源极掺杂物热扩散。源极驱动后，在器件的顶面上沉积一层介电(例如含有硼磷的硅玻璃)层365，在某些实施例中还可以选择性地增加介电层的密度。
图3O至3T表示接触沟道和各种植入物的形成。如图3O所示，光致抗蚀层372沉积在介电层上，使用接触掩膜形成图案。第一接触刻蚀用于形成沟道368和370。由于沟道370穿过源极植入物，并形成独立的源极区域371a和371b，因此沟道的深度至少部分取决于源极植入物的厚度。在一些实施例中，第一接触沟道的深度约为0.2到2.5微米。
如图3P所示，除去光致抗蚀层，用植入离子轰击沟道底部附近的区域，形成主体接触植入物373。一些实施例中，植入了大约每平方厘米1到5e15个离子的硼离子。相应的植入能量约为10到60keV。在另一些实施例中，使用大约每平方厘米1到5e15个离子、植入能量40到100keV的BF2离子。还有一些实施例中，植入BF2和硼，形成主体接触植入物。植入倾角约在0到45°之间。然后将植入物进行热扩散。
如图3Q所示，进行第二接触刻蚀。由于刻蚀过程并不影响介电层，第二接触刻蚀也就不需要额外的掩膜。第二刻蚀的深度取决于沟道底部主体接触植入物需要除去的量，这个量又进而取决于正向电压降的增加量以及相应的漏电流的减少量。在一些实施例中(如图1A所示的器件100)，沟道底部所有的主体接触植入物都被除去，仅剩余侧壁上的植入物。在另一些实施例中(如图1B所示的器件102和图3Q所示的器件)，仅除去沟道底部的一部分主体接触植入物，剩余二极管增强层374。二极管增强层越厚，导致肖特基正向电压降越大，漏电流却越小。在某些实施例中，接触沟道的深度增大了约0.2到0.5微米。
在一些实施例中，进行第二接触刻蚀时，接触沟道底面上所有的主体接触植入物都被除去。可以选择性地植入载流子类型和外延层相反的掺杂物，在接触沟道的底部区域，形成肖特基势垒控制层(也被认为是香农植入)。香农植入属于浅显、小剂量的植入，因此无论是否偏置，都完全耗尽。香农植入用于控制肖特基势垒高度，因此能够更好地控制漏电流，并增强肖特基二极管的反向恢复特性。因此，沉积香农植入的步骤是可选的，图表中并没有给出。
如图3R所示，植入一个外延层376。本例中，使用N型掺杂物。在载流子浓度为每立方厘米2e16个离子的N型外延层的实施例中，植入能级约为40keV、掺杂等级约为每平方厘米8e12个离子的磷离子。在1050℃下热扩散植入层30秒。生成的外延层厚度大约0.15到0.4微米，浓度约为每立方厘米5e16到3e17个离子。可以通过改变植入能量、剂量以及扩散温度等参数获得不同的厚度。外延增强层越厚或者其浓度越大，二极管击穿电压降低得越多。
也可选择省去第二次接触刻蚀。在一些实施例中，按照步骤3P进行接触植入后，外延增强植入可通过使用不同能量和计量组合的植入物形成。只要接触沟道侧壁内的主体接触植入物仍然不受影响，那么接触沟道底部的主体接触植入物就可以完全补偿肖特基二极管的形成，或部分补偿低注入二极管的形成，留下一个薄二极管增强层。在一个实施例中，首先植入200keV的磷离子植入浓度每平方厘米6e12个离子，随后第二次植入100keV的磷离子植入浓度每平方厘米2e12个离子，以补偿一部分主体接触植入物，并形成外延增强层。
如图3S，展示了一个完整的器件390。金属层378沉积、在适当的地方刻蚀，然后退火。沉积钝化层380后，制作钝化开口。还将进行晶片研磨、背垫金属沉积等制作过程。
图4K至4S为器件的横截面视图，详细介绍了另一种制造一个金属氧化物半导体场效应管器件的生产过程。此过程也经常用于制造小壁-壁间距尺寸的器件。本例中，图3A到3J所示的步骤已经用于形成栅极。如图4K所示，由于光致抗蚀主体块的间距尺寸(pitch)很小，因此如图3K中的350很难形成，图4K到4R所示的制作工艺中没有使用光致抗蚀主体块。
图4K中，植入一个没有光致抗蚀主体块的主体掺杂层。本例中器件的壁-壁间距尺寸(pitch)在1.4微米的数量级上，甚至更小。如图4L，热扩散主体掺杂物。如图4M所示，一层光致抗蚀剂形成源极阻块464。植入一层源极掺杂物466。如图4N所示，除去光致抗蚀剂，并热扩散源极掺杂物。源极驱动后，在器件的顶面上沉积一个介电(例如含有硼磷的硅玻璃)层465，在某些实施例中，在某些实施例中还可以选择性地增加介电层的密度。
图4O至4T表示接触沟道和各种植入物的形成。如图4O所示，在介电层上沉积一个光致抗蚀层472，并通过接触掩膜形成图案。通过第一次接触刻蚀形成沟道468和470。刻蚀穿透源极层，形成独立的源极区域。主体层的大部分也被除去。如图4P所示，除去光致抗蚀层，用植入离子轰击沟道底部附近的侧壁，以便形成主体接触植入物473。在一些实施例中，植入的是剂量约为每平方厘米1到5e15个离子的硼离子，植入能量约为10到60keV。在某些实施例中，也可使用剂量约为每平方厘米1到5e15个离子、植入能量约为40到100keV的BF2离子。在另一些实施例中，BF2和硼都植入，以便形成主体接触植入物。植入倾角约为0到45°。然后将植入物进行热扩散。
如图4Q所示，进行第二次接触刻蚀。根据二极管正向电压降和漏电流的变化情况，除去沟道底部部分或全部的主体接触植入物。如图4R所示，植入外延增强层476，并进行热扩散。对于载流子浓度为每立方厘米2e16个离子的N型外延层的实施例，需植入能级约为40keV、剂量等级约为每平方厘米8e12个离子的磷离子。在1050℃下热扩散植入层30秒。生成的外延增强层厚度约为0.15到0.4微米，浓度约为每立方厘米5e16到3e17个离子。可以通过改变植入能量、剂量以及扩散温度等参数获得不同的厚度。选择合适的沟道深度和外延增强植入物，以使主体区域477a和477b在主体区域底部分离。
也可以选择省去第二次接触刻蚀。在一些实施例中，按照步骤4P进行接触植入后，外延增强植入可通过使用不同能量和计量组合的植入物形成。只要接触沟道侧壁内的主体接触植入物仍然不受影响，那么接触沟道底部的主体接触植入物就可以完全补偿肖特基二极管的形成，或部分补偿低注入二极管的形成，留下一个薄二极管增强层。在一个实施例中，首先植入200keV的磷离子植入浓度每平方厘米6e12个离子，随后第二次植入100keV的磷离子植入浓度每平方厘米2e12个离子，以补偿一部分主体接触植入物，并形成外延增强层。
如图4S所示，展示了一个完整的器件490。金属层478沉积、在适当的地方刻蚀，然后退火。沉积钝化层480后，制作钝化开口。还将进行晶片研磨、背垫金属沉积等制作过程。
为了便于理解，上述实施例详细阐述了各项细节，但并不能将本发明的范围局限于此。本发明还有很多不同的实现方法。上述的实施例仅用作解释说明，并不具有限制性。

Claims (14)

1.一种半导体器件，其特征在于，包含一个漏极、一个覆盖在漏极上的外延层、一个有源区；
所述有源区包含：
一个沉积在外延层中的主体、
一个嵌入主体内的源极、
一个延伸进外延层的栅极沟道、
一个沉积在栅极沟道中的栅极、
一个沿源极和至少一部分主体延伸的接触沟道、
一个沉积在接触沟道中的接触电极、
一个沉积在接触沟道下面的外延增强部分；所述外延增强部分的载流子类型与外延层的一致；
一个沉积在接触沟道侧壁上的主体接触植入物；所述主体接触植入物的载流子类型与外延层相反；
一个沿接触沟道底部沉积的二极管增强层，而且在所述二极管增强层下面沉积所述外延增强部分。
2.如权利要求1所述的半导体器件，其特征在于，所述外延增强部分用于降低由接触电极和漏极形成的肖特基二极管的击穿电压。
3.如权利要求1所述的半导体器件，其特征在于，所述外延增强部分的载流子浓度比外延层的载流子浓度要高。
4.如权利要求1所述的半导体器件，其特征在于，所述有源区还包括沉积在接触沟道下面和外延增强部分上面的香农植入物，所述香农植入物的载流子类型与外延层的相反。
5.如权利要求1所述的半导体器件，其特征在于，所述半导体器件的壁-壁间距尺寸小于或等于1.4微米；所述半导体器件中包含若干个所述栅极沟道，每个所述栅极沟道具有相对布置的第一侧和第二侧的侧壁；所述壁-壁间距尺寸是其中任意一个栅极沟道的第一侧的侧壁，与相邻一个栅极沟道的第一侧的侧壁之间的距离。
6.如权利要求1所述的半导体器件，其特征在于，所述外延层和外延增强部分为N型。
7.如权利要求1所述的半导体器件，其特征在于，所述外延层和外延增强部分为P型。
8.一种半导体器件的制作方法，其特征在于，包含以下步骤：
在外延层中制造一个栅极沟道，覆盖在半导体衬底上；
在栅极沟道内沉积栅极材料；
在外延层中制造一个主体；
制造一个源极嵌入主体；
制造一个沿源极和至少一部分主体延伸的接触沟道；
在接触沟道下面沉积一个外延增强部分，其中外延增强部分的载流子类型与外延层的一致；
还在接触沟道的侧壁上沉积一个主体接触植入物，所述主体接触植入物的载流子类型与外延层的相反；
并沿接触沟道底部形成一个二极管增强层；所述外延增强部分沉积在二极管增强层之下；
在接触沟道中沉积一个接触电极。
9.如权利要求8所述的半导体器件的制作方法，其特征在于，所述外延增强部分用于降低由接触电极和漏极形成的肖特基二极管的击穿电压。
10.如权利要求8所述的半导体器件的制作方法，其特征在于，所述外延增强部分的载流子浓度要高于外延层的载流子浓度。
11.如权利要求8所述的半导体器件的制作方法，其特征在于，还包括在接触沟道下面和外延增强部分上面沉积香农植入物，所述香农植入物的载流子类型与外延层相反。
12.如权利要求8所述的半导体器件的制作方法，其特征在于，所述半导体器件的壁-壁间距尺寸小于或等于1.4微米；所述半导体器件中包含若干个所述栅极沟道，每个所述栅极沟道具有相对布置的第一侧和第二侧的侧壁；所述壁-壁间距尺寸是其中任意一个栅极沟道的第一侧的侧壁，与相邻一个栅极沟道的第一侧的侧壁之间的距离。
13.如权利要求8所述的半导体器件的制作方法，其特征在于，所述主体的制作包括制作一个光致抗蚀主体块，并通过光致抗蚀主体块在未掩膜区内植入主体。
14.如权利要求8所述的半导体器件的制作方法，其特征在于，所述主体的制作包括制作一个主体层，并进行接触刻蚀。
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