CN101740674A - Light-emitting element structure and manufacturing method thereof - Google Patents
Light-emitting element structure and manufacturing method thereof Download PDFInfo
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- CN101740674A CN101740674A CN200810177996A CN200810177996A CN101740674A CN 101740674 A CN101740674 A CN 101740674A CN 200810177996 A CN200810177996 A CN 200810177996A CN 200810177996 A CN200810177996 A CN 200810177996A CN 101740674 A CN101740674 A CN 101740674A
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Abstract
The invention discloses a photoelectric element structure with a stress balance layer and a manufacturing method thereof. The photoelectric element structure comprises a high heat conductivity substrate, the stress balance layer is positioned on the high heat conductivity substrate, a metal reflection layer is positioned on the stress balance layer, and an epitaxial structure is positioned on the metal reflection layer.
Description
Technical field
The present invention discloses has the photoelectric cell structure and the manufacture method thereof of stress equilibrium layer, particularly about a kind of high heat conductive LED structure and manufacture method thereof.
Background technology
The aluminium oxide of known carrying blue light-emitting diode (sapphire) substrate belongs to low heat conductivity material (coefficient of heat conduction is about 40W/mK), when under the high current situation, operating, can't transmit heat effectively, cause accumulation of heat and influence the reliability of light-emitting diode.
Full wafer high thermal conductivity metallic copper substrate (coefficient of heat conduction is about 400W/mK) is connected with light-emitting diode with plating or bonding method to be appearred in the market at present, can transmit heat effectively.Yet after removing the growth substrate, internal stress compression full wafer metallic copper substrate causes chip (wafer) warpage and influences the subsequent technique rate of finished products.
Summary of the invention
The invention provides a kind of photoelectric cell structure, substrate wherein is a high thermal conductive substrate, can be made up of copper, aluminium, molybdenum, silicon, germanium, metal-base composites, copper alloy, aluminium alloy or molybdenum alloy.
The invention provides a kind of photoelectric cell structure, substrate wherein is a high thermal conductive substrate, can be formed by electroless plating, plating or electroforming mode.
The invention provides a kind of photoelectric cell structure, stress equilibrium layer wherein can be made up of monolayer material or multilayer material.
The invention provides a kind of photoelectric cell structure, stress equilibrium layer wherein can be made up of nickel, tungsten, molybdenum, cobalt, platinum, gold or copper.
The invention provides a kind of photoelectric cell structure, stress equilibrium layer wherein can be formed by electroless plating, plating or electroforming mode.
The invention provides a kind of photoelectric cell structure, substrate wherein is a high thermal conductive substrate, and the thermal coefficient of expansion of its thermal coefficient of expansion and stress equilibrium layer differs and is not less than 5ppm/ ℃.
The invention provides a kind of photoelectric cell structure, wherein the thickness of stress equilibrium layer is not less than 0.01 times and be not more than 0.6 times high thermal conductive substrate thickness.
The invention provides a kind of photoelectric cell structure, stress equilibrium layer tool periodic patterns structure wherein.
The invention provides a kind of photoelectric cell structure, each patterning width of stress equilibrium layer of tool periodic patterns structure wherein is not less than the width of 0.01 times of photoelectric cell, and is not more than the width of 1 times of photoelectric cell.
The invention provides a kind of photoelectric cell structure, the stress equilibrium layer thickness of tool periodic patterns structure wherein is not less than 0.01 times and be not more than 1.5 times of high thermal conductive substrate thickness.
The invention provides a kind of photoelectric cell structure, stress equilibrium layer width wherein is greater than the width of high thermal conductive substrate.
The invention provides a kind of photoelectric cell structure, its material of epitaxial structure wherein comprises one or more material, is selected from the group that gallium, aluminium, indium, arsenic, phosphorus and nitrogen constitute.
Description of drawings
Fig. 1-the 5th shows that the photoelectric cell of the embodiment of the invention is made flow chart;
Fig. 6-the 9th shows that the photoelectric cell of another embodiment of the present invention is made flow chart;
Figure 10-the 12nd shows that the photoelectric cell of yet another embodiment of the invention is made flow chart.
Figure 13 is known luminous device structure schematic diagram.
The main element symbol description
21～growth substrate
22～epitaxial structure
23～the first electrical semiconductor layers
24～active layer
25～the second electrical semiconductor layers
26～the second electrical contact layers
27～reflector
28～stress equilibrium layer
29～high thermal conductive substrate
30～the first electrical contact layers
31～the first electrodes
32～Cutting Road
The stress equilibrium layer of 33～tool periodic patterns structure
34～photoresist
60～inferior carrier
62～scolder
64～electric connection structure
100,200,300～LED crystal particle
600～light-emitting device
602～circuit
A～stress equilibrium layer thickness
B～high thermal conductive substrate thickness
Each patterning width of the stress equilibrium layer of c～tool periodic patterns structure
D～photoelectric cell width
The stress equilibrium layer thickness of e～tool periodic patterns structure
F～stress equilibrium layer width
G～high thermal conductive substrate width
Embodiment
The present invention discloses a kind of photoelectric cell structure and manufacture method thereof with stress equilibrium layer.In order to make narration of the present invention more detailed and complete, can and cooperate that Fig. 1's to Figure 13 is graphic with reference to following description.
Embodiment one
Photoelectric cell structure of the present invention is example with the light-emitting diode, and its structure and manufacture method are shown in 1-5 figure.
Shown in Figure 1, comprise a growth substrate 21, its material can be GaAs, silicon, carborundum, sapphire, indium phosphide, gallium phosphide, aluminium nitride or gallium nitride etc.Then, on growth substrate 21, form epitaxial structure 22.Epitaxial structure 22 is to form by an epitaxy technique, for example organic metal vapour deposition epitaxy (MOCVD), liquid phase epitaxial method (LPE) or molecular beam epitaxy (MBE) homepitaxy technology.This extension structure 22 comprises one first electrical semiconductor layer 23 at least, for example is a n type AlGaInP (Al
xGa
1-x)
yIn
1-yA P layer or a n type aluminum indium gallium nitride (Al
xGa
1-x)
yIn
1-yThe N layer; One active layer 24 for example is AlGaInP (Al
xGa
1-x)
yIn
1-yP or aluminum indium gallium nitride (Al
xGa
1-x)
yIn
1-yThe formed multiple quantum trap structure of N; And one second electrical semiconductor layer 25, for example be a p type AlGaInP (Al
xGa
1-x)
yIn
1-yA P layer or a p type aluminum indium gallium nitride (Al
xGa
1-x)
yIn
1-yThe N layer.In addition, the active layer 24 of present embodiment can be piled up by for example homostyructure, single heterojunction structure, double-heterostructure or multiple quantum trap structure and be formed.
Then, on epitaxial structure 22, form one second an electrical contact layer 26 and a reflector 27.The material of the second electrical contact layer 26 can be tin indium oxide (Indium Tin Oxide), indium oxide (IndiumOxide), tin oxide (Tin Oxide), cadmium tin (Cadmium Tin Oxide), zinc oxide (ZincOxide), magnesium oxide (Magnesium Oxide) or titanium nitride (Titanium Nitride) etc.Reflector 27 can be metal material, and is for example silver-colored, aluminium, titanium, chromium, platinum, gold etc.
Then, the epitaxial structure that will have a reflector 27 with growth substrate 21 last, reflector 27 under mode insert and carry out electrochemical deposition method (electro chemical deposition) in the chemical tank, for example: electroplate electroforming; Or do not have electrochemical deposition method (electroless chemical deposition) technology, for example: electroless plating; With 27 the following formation one stress equilibrium layer 28 in the reflector, its material can be selected from nickel, tungsten, molybdenum, cobalt, platinum, gold or copper.Form structure shown in the 2nd figure.When stress equilibrium layer reflectivity is higher, can be used as the reflector, then reflector 27 can be omitted.
As shown in Figure 3, the structure that will have stress equilibrium layer 28 is again inserted and is carried out another time electrochemical deposition method (electro chemical deposition) in another chemical tank, for example: electroplate electroforming; Or do not have electrochemical deposition method (electroless chemical deposition) technology, for example: electroless plating; With in following formation one high thermal conductive substrate 29 of stress equilibrium layer 28, to become a wafer (wafer) structure.Wherein the high thermal conductive substrate material can be selected from copper, aluminium, molybdenum, silicon, germanium, tungsten, metal-base composites, copper alloy, aluminium alloy or molybdenum alloy etc.The material selection principle of high thermal conductive substrate is not less than 5ppm/ ℃ for the thermal coefficient of expansion of its thermal coefficient of expansion and epitaxial structure 22 differs.And stress equilibrium layer thickness a optimum condition is for being not less than 0.01 times and be not more than 0.6 times of high thermal conductive substrate thickness b, i.e. 0.01b≤a≤0.6b.
Then as shown in Figure 4, by modes such as laser lift-off technique, etch process or chemical mechanical milling tech part or after removing growth substrate 21 fully, expose the surface of the first electrical semiconductor layer 23 of epitaxial structure 22.Generally after removing the growth substrate, the internal stress between high thermal conductive substrate and the epitaxial structure can be compressed the full wafer high thermal conductive substrate, causes the chip architecture warpage and influences the subsequent technique rate of finished products.The formation of stress equilibrium layer can reduce the internal stress between high thermal conductive substrate and the epitaxial structure, suppresses the chip architecture warping phenomenon.Next, on the surface that the first electrical semiconductor layer 23 exposes, form the first electrical contact layer 30 again.The material of the first electrical contact layer 30 can be tin indium oxide (Indium Tin Oxide), indium oxide (Indium Oxide), tin oxide (Tin Oxide), cadmium tin (Cadmium Tin Oxide), zinc oxide (Zinc Oxide), magnesium oxide (Magnesium Oxide), titanium nitride (Titanium Nitride), germanium gold (Ge/Au), germanium gold nickel (Ge/Au/Ni) or the formed film of chromium aluminium (Cr/Al), and optionally forms specific pattern with etch process on film.Then, utilize hot evaporation (Thermal Evaporation), electron beam evaporation plating (E-beam) or ion beam sputtering deposition methods such as (Sputtering), between the specific pattern of the first electrical contact layer 30, form one first electrode 31.If the first electrical contact layer 30 does not form specific pattern for the continuous film layer, 31 at first electrode is formed directly on the first electrical contact layer 30, and its material can be gold-tin alloy or golden indium alloy.In this embodiment, high thermal conductive substrate 29 can be used as second electrode.Then etching multiple tracks Cutting Road 32 cuts into the LED crystal particle 100 with high thermal conductive substrate along Cutting Road with light-emitting diode, as shown in Figure 5 again.
Embodiment two
The formed photoelectric cell structure of another embodiment of the present invention is example with the light-emitting diode, and structure and manufacture method are then shown in Fig. 1 and Fig. 6-9.Wherein epitaxial structure is identical with embodiment one, as shown in Figure 1.As shown in Figure 6, the epitaxial structure that will have a reflector 27 with growth substrate 21 last, reflector 27 under mode insert and carry out electrochemical deposition method (electro chemical deposition) in the chemical tank, for example: electroplate electroforming; Or do not have electrochemical deposition method (electroless chemical deposition) technology, for example: electroless plating; With in the following formation one stress equilibrium layer 33 in reflector, utilize gold-tinted again, technologies such as etching make the stress equilibrium layer form the structure of a tool periodic patterns.Its material can be selected from nickel, tungsten, molybdenum, cobalt, platinum, gold or copper.When stress equilibrium layer reflectivity is higher, can be used as the reflector, then reflector 27 can be omitted.
As shown in Figure 7, the structure of the stress equilibrium layer 33 of tool periodic patterns structure is inserted carried out another time electrochemical deposition method (electro chemical deposition) in another chemical tank again, for example: electroplate electroforming; Or do not have electrochemical deposition method (electroless chemical deposition) technology, for example: electroless plating; Make the interval and the below of stress equilibrium layer of tool periodic patterns structure form a high thermal conductive substrate 29, to become a wafer (wafer) structure.Wherein the high thermal conductive substrate material can be selected from copper, aluminium, molybdenum, silicon, germanium, tungsten, metal-base composites, copper alloy, aluminium alloy, molybdenum alloy etc.Each the patterning width c of stress equilibrium layer of periodic patterns structure of wherein having is not less than 0.01 times high heat conduction photoelectric cell width d, and is not more than the width of 1 times high heat conduction photoelectric cell, i.e. 0.01d≤c≤d.The stress equilibrium layer thickness e optimum condition of periodic patterns structure is the high thermal conductive substrate layer thickness b that is not less than 0.01 times and is not more than 1.5 times, i.e. 0.01b≤e≤1.5b.
Then, as shown in Figure 8, utilize modes such as laser lift-off technique, etch process or chemical mechanical milling tech partly or remove growth substrate 21 fully.After growth substrate 21 removes, expose the surface of the first electrical semiconductor layer 23 of epitaxial structure 22, form the first electrical contact layer 30 more thereon.The material of the first electrical contact layer 30 can be tin indium oxide (Indium Tin Oxide), indium oxide (IndiumOxide), tin oxide (Tin Oxide), cadmium tin (Cadmium Tin Oxide), zinc oxide (ZincOxide), magnesium oxide (Magnesium Oxide), titanium nitride (Titanium Nitride), germanium gold (Ge/Au), germanium gold nickel (Ge/Au/Ni) or the formed film of chromium aluminium (Cr/Al), and optionally forms specific pattern with etch process on film.Form one first electrode 31 respectively at first electrical contact layer 30 upper surfaces again, in this embodiment, high thermal conductive substrate 29 can be used as second electrode.Wherein the material of first electrode can be gold-tin alloy or golden indium alloy.In this embodiment, also can form a matsurface in first electrical contact layer 30 upper surfaces and/or lower surface.Then etching multiple tracks Cutting Road 32 cuts into the LED crystal particle 200 with high thermal conductive substrate along Cutting Road with light-emitting diode, as shown in Figure 9 again.
Embodiment three
The formed photoelectric cell structure of an embodiment more of the present invention is example with the light-emitting diode, and structure and manufacture method are then shown in Fig. 1-2 and Figure 10-12.Wherein epitaxial structure is identical with embodiment one with manufacture method, shown in Fig. 1-2.Again as shown in figure 10, forming the multiple tracks spacing distance in stress equilibrium layer 28 below is the photoresist 34 of g, again this structure is inserted and carried out another time electrochemical deposition method (electro chemical deposition) in another chemical tank, for example: electroplate electroforming; Or do not have electrochemical deposition method (electroless chemical deposition) technology, for example: electroless plating to form a high thermal conductive substrate 29 between the following multiple tracks photoresist of stress equilibrium layer 28, becomes a wafer (wafer) structure at last.Wherein the high thermal conductive substrate material can be selected from copper, aluminium, molybdenum, silicon, germanium, tungsten, metal-base composites, copper alloy, aluminium alloy or molybdenum alloy etc.Then as shown in figure 11, by modes such as laser lift-off technique, etch process or chemical mechanical milling tech part or after removing growth substrate 21 fully, expose the surface of the first electrical semiconductor layer 23 of epitaxial structure 22, form the first electrical contact layer 30 more thereon.The material of the first electrical contact layer 30 can be tin indium oxide (Indium Tin Oxide), indium oxide (IndiumOxide), tin oxide (Tin Oxide), cadmium tin (Cadmium Tin Oxide), zinc oxide (ZincOxide), magnesium oxide (Magnesium Oxide), titanium nitride (Titanium Nitride), germanium gold (Ge/Au), germanium gold nickel (Ge/Au/Ni) or the formed film of chromium aluminium (Cr/Al), and optionally forms specific pattern with etch process on film.Then, utilize hot evaporation (Thermal Evaporation), electron beam evaporation plating (E-beam) or ion beam sputtering deposition methods such as (Sputtering), between the specific pattern of the first electrical contact layer 30, form one first electrode 31.If the first electrical contact layer 30 does not form specific pattern for the continuous film layer, 31 at first electrode is formed directly on the first electrical contact layer 30, and its material can be gold-tin alloy or golden indium alloy.In this embodiment, high thermal conductive substrate 29 can be used as second electrode.Then etching multiple tracks Cutting Road 32 cuts into the LED crystal particle 300 with high thermal conductive substrate along Cutting Road with light-emitting diode, as shown in figure 12 again.The width g that is in high thermal conductive substrate layer 29 that present embodiment is different with other embodiment is less than stress equilibrium layer 28 width f, i.e. g＜f.The high thermal conductive substrate width is wideer, and the internal stress of its expanded by heating is just bigger, but must transmit heat in allowing width range, so design makes the width g of high thermal conductive substrate layer less than stress equilibrium layer width f.
In addition, the above embodiments one to three LED crystal particle 100-300 that is disclosed more can be connected with other elements combination to form a light-emitting device (light-emitting apparatus) further.The 13rd figure is known luminous device structure schematic diagram, and as shown in figure 13, a light-emitting device 600 comprises an inferior carrier (sub-mount) 60 with at least one circuit 602; At least one scolder 62 (solder) is positioned on above-mentioned carrier 60, by this scolder 62 above-mentioned LED crystal particle 100 is cohered and is fixed on time carrier 60 and the substrate 29 of LED crystal particle 100 is electrically connected with circuit 602 formation on time carrier 60; And an electric connection structure 64 is with the electrode 31 of electric connection LED crystal particle 100 and the circuit 602 on time carrier 60; Wherein, above-mentioned inferior carrier 60 can be that lead frame (leadframe) or large scale are inlayed substrate (mounting substrate), with the circuit planning that makes things convenient for light-emitting device 600 and improve its radiating effect.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (10)
1. a photoelectric cell, its manufacture method comprises:
The growth substrate is provided, and it has first plane and second plane;
Form epitaxial structure on first plane of this growth substrate, it has n type semiconductor layer, luminescent layer and p type semiconductor layer at least;
Form metallic reflector on this epitaxial structure;
With electrochemical deposition method or do not have electrochemical deposition method and form the stress equilibrium layer in this metallic reflector side relative with this epitaxial structure;
With electrochemical deposition method or do not have electrochemical deposition method and form high thermal conductive substrate in this stress equilibrium layer side relative with this epitaxial structure, wherein this stress equilibrium layer can reduce the internal stress between this high thermal conductive substrate and this epitaxial structure, and the thermal coefficient of expansion of this high thermal conductive substrate and this epitaxial structure differs and is not less than 5ppm/ ℃;
Remove this growth substrate, to expose a surface of this epitaxial structure;
Form electrode on this surface that this epitaxial structure exposes, wherein this electrode and this epitaxial structure form electrical ties;
Be etched to this high thermal conductive substrate from this epitaxial structure from top to bottom, to form the multiple tracks Cutting Road; And
Cut to form this photoelectric cell along this Cutting Road.
2. photoelectric cell manufacture method as claimed in claim 1, the electrochemical deposition method that wherein forms this stress equilibrium layer and this high thermal conductive substrate can be to be electroplated or electroforming.
3. photoelectric cell manufacture method as claimed in claim 1, the no electrochemical deposition method that wherein forms this stress equilibrium layer and this high thermal conductive substrate can be electroless plating.
4. photoelectric cell manufacture method as claimed in claim 1, the method that wherein forms this multiple tracks Cutting Road also comprises gold-tinted or developing process.
5. a photoelectric cell, its manufacture method comprises:
The growth substrate is provided, and it has first plane and second plane;
Form epitaxial structure on first plane of this growth substrate, it has n type semiconductor layer, luminescent layer and p type semiconductor layer at least;
Form metallic reflector on this epitaxial structure;
With electrochemical deposition method or do not have electrochemical deposition method and form the stress equilibrium layer in this metallic reflector side relative with this epitaxial structure;
Utilize etch process to make this stress equilibrium layer form the structure of tool periodic patterns, wherein each patterning width of the stress equilibrium layer of this tool periodic patterns structure is not less than the width of 0.01 times of this photoelectric cell, and is not more than the width of 1 times of this photoelectric cell;
With electrochemical deposition method or do not have electrochemical deposition method and form high thermal conductive substrate in the stress equilibrium layer of this a tool periodic patterns structure side relative with this epitaxial structure, wherein the stress equilibrium layer of this tool periodic patterns structure can reduce the internal stress between this high thermal conductive substrate and this epitaxial structure;
Remove this growth substrate, to expose a surface of this epitaxial structure;
Form electrode on this surface that this epitaxial structure exposes, wherein this electrode and this epitaxial structure form electrical ties;
Be etched to this high thermal conductive substrate from this epitaxial structure from top to bottom, to form the multiple tracks Cutting Road; And
Form this photoelectric cell along this Cutting Road cutting.
6. photoelectric cell manufacture method as claimed in claim 5 wherein forms the stress equilibrium layer of this tool periodic patterns structure and the electrochemical deposition method of this high thermal conductive substrate and can be plating or electroforming.
7. photoelectric cell manufacture method as claimed in claim 5 wherein forms the stress equilibrium layer of this tool periodic patterns structure and the no electrochemical deposition method of this high thermal conductive substrate and can be electroless plating.
8. a photoelectric cell, its manufacture method comprises:
The growth substrate is provided, and it has first plane and second plane;
Form epitaxial structure on first plane of this growth substrate, it has n type semiconductor layer, luminescent layer and p type semiconductor layer at least;
Form metallic reflector on this epitaxial structure;
With electrochemical deposition method or do not have electrochemical deposition method and form the stress equilibrium layer in this metallic reflector side relative with this epitaxial structure;
Form the multiple tracks photoresist in the below of this stress equilibrium layer;
With electrochemical deposition method or do not have electrochemical deposition method and form high thermal conductive substrate in the below of this stress equilibrium layer and there is not the zone that this photoresist covers, make the width of this high thermal conductive substrate less than the width of this stress equilibrium layer, and this stress equilibrium layer can reduce the internal stress between this high thermal conductive substrate and this epitaxial structure;
Remove in the below of this stress equilibrium layer multiple tracks photoresist;
Remove this growth substrate, to expose a surface of this epitaxial structure;
Form electrode on this surface that this epitaxial structure exposes, wherein this electrode and this epitaxial structure form electrical ties;
Be etched to this high thermal conductive substrate from this epitaxial structure from top to bottom, to form the multiple tracks Cutting Road; And
Form this photoelectric cell along this Cutting Road cutting.
9. photoelectric cell manufacture method as claimed in claim 8, the electrochemistry sedimentation that wherein forms this stress equilibrium layer and this high thermal conductive substrate can be electroplates or electroforming.
10. photoelectric cell manufacture method as claimed in claim 8, the no electrochemistry sedimentation that wherein forms this stress equilibrium layer and this high thermal conductive substrate can be electroless plating.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681980A (en) * | 2012-09-25 | 2014-03-26 | 上海蓝光科技有限公司 | A method for cutting light emitting diodes with back-plated reflecting layers |
| CN105047804A (en) * | 2015-06-01 | 2015-11-11 | 聚灿光电科技股份有限公司 | Packaging-free LED chip and preparation method thereof |
| CN106058000A (en) * | 2011-09-16 | 2016-10-26 | 首尔伟傲世有限公司 | Light emitting diode and method of manufacturing same |
| CN106449912A (en) * | 2016-11-28 | 2017-02-22 | 东莞市中镓半导体科技有限公司 | GaN-based composite substrate with stress balance structural layer and method for preparing GaN-based composite substrate |
| CN110071210A (en) * | 2019-04-15 | 2019-07-30 | 深圳先进技术研究院 | Infrared LED device and preparation method thereof |
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| CN100477301C (en) * | 2004-12-21 | 2009-04-08 | 晶元光电股份有限公司 | Method for fabricating light emitting diode |
| CN100573937C (en) * | 2006-12-29 | 2009-12-23 | 晶元光电股份有限公司 | Light-emitting diode and manufacture method thereof |
| CN101276863B (en) * | 2007-03-29 | 2011-02-09 | 晶元光电股份有限公司 | LED and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106058000A (en) * | 2011-09-16 | 2016-10-26 | 首尔伟傲世有限公司 | Light emitting diode and method of manufacturing same |
| CN106058000B (en) * | 2011-09-16 | 2019-04-23 | 首尔伟傲世有限公司 | Light emitting diode and the method for manufacturing the light emitting diode |
| CN103681980A (en) * | 2012-09-25 | 2014-03-26 | 上海蓝光科技有限公司 | A method for cutting light emitting diodes with back-plated reflecting layers |
| CN105047804A (en) * | 2015-06-01 | 2015-11-11 | 聚灿光电科技股份有限公司 | Packaging-free LED chip and preparation method thereof |
| CN106449912A (en) * | 2016-11-28 | 2017-02-22 | 东莞市中镓半导体科技有限公司 | GaN-based composite substrate with stress balance structural layer and method for preparing GaN-based composite substrate |
| CN110071210A (en) * | 2019-04-15 | 2019-07-30 | 深圳先进技术研究院 | Infrared LED device and preparation method thereof |
| CN110071210B (en) * | 2019-04-15 | 2020-10-23 | 深圳先进技术研究院 | Infrared LED device and preparation method thereof |
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|---|---|
| CN101740674B (en) | 2011-08-31 |
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