CN112652689B - Light emitting diode and manufacturing method thereof - Google Patents
Light emitting diode and manufacturing method thereof Download PDFInfo
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- CN112652689B CN112652689B CN202011615686.7A CN202011615686A CN112652689B CN 112652689 B CN112652689 B CN 112652689B CN 202011615686 A CN202011615686 A CN 202011615686A CN 112652689 B CN112652689 B CN 112652689B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/387—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
Abstract
The application relates to the field of light emitting diodes, and particularly discloses a light emitting diode and a manufacturing method thereof, wherein the light emitting diode comprises: a substrate; the light-emitting epitaxial layer comprises a first semiconductor layer, an active light-emitting layer and a second semiconductor layer which are sequentially stacked and arranged on one side of the substrate; the ohmic contact patterns are arranged on one side of the first semiconductor layer or the second semiconductor layer, which is far away from the active light emitting layer, at intervals in a lattice mode; and the reflecting mirror layer is positioned on one side of the ohmic contact patterns, which is deviated from the active light-emitting layer, and covers the ohmic contact patterns and the first semiconductor layer or the second semiconductor layer among the ohmic contact patterns. By the mode, the current distribution can be effectively improved, the current distribution uniformity is improved, the efficiency dip effect under large current is inhibited, and the reflectivity of the reflector is improved.
Description
Technical Field
The present disclosure relates to the field of light emitting diodes, and more particularly, to a light emitting diode and a method for manufacturing the same.
Background
A Light Emitting Diode (LED) is a semiconductor element that converts an electric current into Light in a specific wavelength range. The light emitting diode has the advantages of high brightness, low working voltage, low power consumption, easy matching with an integrated circuit, simple driving, long service life and the like, thereby being widely applied to the field of illumination as a light source.
An LED generally includes a first semiconductor layer, a light emitting epitaxial layer, and a second semiconductor layer. When a voltage is applied across the LED, holes and electrons recombine in the light-emitting epitaxial layer, radiating photons. One problem faced by LEDs during their application is their light extraction efficiency. Because photons can be generated only when current passes through the light-emitting epitaxial layer, the light-emitting efficiency of the LED has a great relationship with the distribution uniformity of the current on the surface of the LED device. For an LED chip with a flip-chip structure, Ag can be generally used as a p-type ohmic contact and a reflector, but a high-temperature annealing process needs to be introduced when the Ag and the p-type gallium nitride form ohmic contact, and the annealing process can reduce the reflectivity of Ag, so that the light emitting efficiency of the LED is reduced. The ohmic contact and the reflector process can be separated by adopting a method of plating a layer of Ag reflector on the ITO after the good ohmic contact is formed between the Europe conductive ITO material and the p-type gallium nitride, but the light-emitting efficiency of the LED is also reduced because the ITO material can absorb light.
Disclosure of Invention
The application provides a light-emitting diode and a manufacturing method thereof, which can effectively improve current distribution, improve current distribution uniformity, inhibit efficiency dip effect under large current, and improve reflectivity of a reflector, thereby improving light-emitting efficiency of an LED chip.
In one aspect, the present application provides a light emitting diode, including: a substrate; the light-emitting epitaxial layer comprises a first semiconductor layer, an active light-emitting layer and a second semiconductor layer which are sequentially stacked and arranged on one side of the substrate; the ohmic contact patterns are arranged on one side of the first semiconductor layer or the second semiconductor layer, which is far away from the active light emitting layer, at intervals in a lattice mode; and the reflecting mirror layer is positioned on one side of the ohmic contact patterns, which is far away from the active light-emitting layer, and covers the ohmic contact patterns and the first semiconductor layer or the second semiconductor layer between the ohmic contact patterns.
In another aspect, the present application provides a method of manufacturing a light emitting diode, the method including: providing a substrate; forming a light-emitting epitaxial layer on one side of the substrate, wherein the light-emitting epitaxial layer comprises a first semiconductor layer, an active light-emitting layer and a second semiconductor layer which are sequentially stacked; forming a plurality of ohmic contact patterns on one side of the second semiconductor layer, which is far away from the active light-emitting layer, wherein the ohmic contact patterns are arranged at intervals in a lattice mode; and forming a reflecting mirror layer on one side of the ohmic contact patterns, which is far away from the active light-emitting layer, wherein the reflecting mirror layer covers the ohmic contact patterns and the second semiconductor layer between the ohmic contact patterns.
The beneficial effect of this application is: different from the prior art, the ohmic contact patterns are arranged on one side of the first semiconductor layer or the second semiconductor layer, which is far away from the active light-emitting layer, at intervals in a lattice manner; the reflector layer is positioned on one side of the ohmic contact patterns, which is far away from the active light-emitting layer, and covers the ohmic contact patterns and the first semiconductor layer or the second semiconductor layer between the ohmic contact patterns. After the second electrode evaporation is completed, the light emitting diode of the present application forms a dot-shaped electrode-reflector layer structure, which can effectively improve current distribution, improve current distribution uniformity, and inhibit efficiency drop (efficiency drop) effect under a large current. Meanwhile, the reflectivity of the reflector can be improved, so that the light emitting efficiency of the LED chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
fig. 1 is a schematic structural diagram of a light emitting diode according to a first embodiment of the present application;
fig. 2 is a flip-chip type light emitting diode according to a second embodiment of the present application;
fig. 3 is a flip-chip type light emitting diode according to a third embodiment of the present application;
fig. 4 is a schematic flow chart of a method of manufacturing a flip-chip type light emitting diode according to a first embodiment of the present application;
fig. 5 is another schematic flow chart of a method of manufacturing a flip-chip type light emitting diode according to the first embodiment of the present application;
fig. 6 is a schematic structural diagram of a vertical light emitting diode according to a fourth embodiment of the present application;
fig. 7 is another schematic structural diagram of a vertical light emitting diode according to a fourth embodiment of the present application;
fig. 8 is a schematic flow chart of a method for manufacturing a vertical light emitting diode according to a fourth embodiment of the present application;
FIG. 9 is a schematic view of the vertical light emitting diode structure at various stages of the process of FIG. 8;
fig. 10 is a schematic top view of a vertical light emitting diode according to a fifth embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For a vertical or flip-chip light emitting diode, in the prior art, an Ag layer is generally used as a reflector, and annealing treatment is performed on the Ag layer, so that the Ag layer has functions of both the reflector and an ohmic contact pattern. After the P-side metal electrode evaporation is completed, a planar electrode-mirror structure will be formed, and this region will become a surface current injection region. The current density of the structure gradually decreases from the electrode pad area to the outside, and the uniformity of the current density distribution under large current is poor. After annealing, the reflectivity of the Ag layer is reduced to about 90%, which results in increased light absorption and reduced light-emitting efficiency of the led.
As shown in fig. 1, the light emitting diode according to the first embodiment of the present application is a flip chip type light emitting diode 10 including: a substrate 11, a light emitting epitaxial layer 12, a plurality of ohmic contact patterns 13, and a mirror layer 14. In the present embodiment, the substrate 11 may be sapphire, SiC, Si, GaN, ZnO, GaAs, GaP, LiAl 2 O 3 Any one of BN, AlN and the like is not limited thereto.
The light-emitting epitaxial layer 12 further includes a first semiconductor layer 121, an active light-emitting layer 122, and a second semiconductor layer 123, which are sequentially stacked and disposed on one main surface of the substrate 11. The first semiconductor layer 121 may be an n-type semiconductor layer, such as an n-type GaN semiconductor layer, and specifically may be a GaN layer doped with at least one of Si, Ge, and Sn. The second semiconductor layer 123 may Be a p-type semiconductor layer, and specifically may Be a GaN layer doped with at least one of Mg, Zn, Be, Ca, Sr, and Ba.
In other embodiments, the first semiconductor layer 121 and the second semiconductor layer 123 may be a single layer or a multi-layer structure of any other suitable material having different conductivity types.
Further, as shown in fig. 1, a plurality of ohmic contact patterns 13 are arranged at intervals in a lattice manner on a side of the second semiconductor layer 123 facing away from the active light emitting layer 122. The mirror layer 14 is positioned at a side of the plurality of ohmic contact patterns 13 facing away from the active light emitting layer 122. Further, the plurality of ohmic contact patterns 13 and the second semiconductor layer 123 are covered. After the evaporation of the second electrode (not shown in the figure) is finished, a dot-shaped electrode-reflector layer structure is formed, so that the current distribution is effectively improved, the current distribution uniformity is improved, and the efficiency dip (effect drop) effect under large current is inhibited. Meanwhile, the reflectivity of the reflector can be improved, so that the light emitting efficiency of the LED chip is improved.
In a specific implementation process, the thicknesses and materials of the mirror layer 14 and the ohmic contact patterns 13 may be adjusted accordingly according to actual conditions. In this embodiment, the thickness of the mirror layer 14 may be 0.01 to 1 micrometer, and the thickness of the plurality of ohmic contact patterns 13 may be 0.01 to 1 micrometer. The material of the mirror layer 14 may be gold, aluminum, silver (Ag), platinum, chromium, nickel, or other suitable metal. The material of the ohmic contact pattern 13 may be a transparent conductive material or other suitable metal, wherein the transparent conductive material may be indium oxide, tin oxide, zinc oxide, Indium Tin Oxide (ITO), cadmium tin oxide, copper aluminum oxide, copper gallium oxide, or strontium copper oxide. In the present embodiment, the material of the plurality of ohmic contact patterns 13 is preferably ITO or silver, and the material of the mirror layer 14 is preferably silver.
In the present embodiment, the reflectivity of the mirror layer 14 is greater than the plurality of ohmic contact patterns 13. Wherein, the reflectivity of the reflector layer 14 in the visible light band is greater than 97%, and the reflectivity of the plurality of ohmic contact patterns 13 in the visible light band is greater than 90%.
Further, in order to make the reflectivity of the mirror layer 14 greater than that of the plurality of ohmic contact patterns 13, the annealing process is performed on the plurality of ohmic contact patterns 13, but the annealing process is not performed on the mirror layer 14. The ITO pattern or the Ag pattern is brought into good ohmic contact with the second semiconductor layer 123 by annealing the ITO pattern or the Ag pattern, wherein the annealing temperature is between 350 ℃ and 550 ℃ and the annealing time is between 3 and 20 minutes.
Since the mirror layer 14 does not need to be annealed, the reflectivity of the mirror layer 14 is not affected and the high reflectivity thereof can still be maintained, as shown in fig. 3, only the area of the second electrode 17 corresponding to the ohmic contact patterns 13 has light absorption loss, and the other areas can still obtain the maximum reflectivity of the mirror layer 14, so that the light absorption loss caused by the ohmic contact patterns 13 can be partially eliminated, and the light extraction efficiency of the light emitting diode 10 is improved.
As shown in fig. 2, the flip-chip type light emitting diode 10 according to the second embodiment of the present application further includes a transparent dielectric layer 15 disposed in the spaced area between the plurality of ohmic contact patterns 13. The mirror layer 14 is in direct contact with the transparent medium layer 15, and it should be noted that the transparent medium layer 15 does not affect the reflectivity of the mirror layer 14.
Through the mode, the whole flatness of the light emitting diode can be well controlled.
The flip-chip type light emitting diode 10 according to the third embodiment of the present application, further includes: an electrode layer (i.e., the second electrode 17 shown in fig. 3) disposed on a side of the mirror layer 14 facing away from the ohmic contact patterns 13, and a pad electrically connected to the electrode layer.
Wherein the electrode layer and the pad on the side of the mirror layer 14 facing away from the plurality of ohmic contact patterns 13 may be respectively formed by printing, evaporation, magnetron sputtering or electroplating techniques, wherein the pad is electrically connected to the electrode layer by directly contacting the electrode layer. Specifically, the shape of the electrode layer is not limited and can be selected according to actual needs. The electrode layer is made of conductive materials, the materials of the electrode layer are aluminum, copper, tungsten, molybdenum, gold, titanium, silver, nickel, palladium or any combination of the aluminum, the copper, the tungsten, the molybdenum, the gold, the titanium, the silver, the nickel and the palladium, and the electrode layer is at least of one layer structure.
As shown in fig. 10, the area of the plurality of ohmic contact patterns 13 is gradually increased in a direction away from the pad 30, so that current is more uniformly diffused compared to the same area, thereby making current injection, light emission, heat dissipation, and wavelength more uniform. Compared with the prior art, the embodiment can achieve the effects of improving current dispersion and improving the luminous efficiency of the light-emitting diode on the premise of not increasing the area of the light-tight electrode.
Further, as shown in fig. 3, grooves 18 are disposed on the second semiconductor layer 123 and the active light emitting layer 122, and the grooves 18 divide the second semiconductor layer 123 and the active light emitting layer 122 into a plurality of mesas 19 arranged in an array spaced apart from each other and expose a portion of the first semiconductor layer 121. The first electrode 16 is disposed in the trench 18 on both sides of the mesa structure 19. The first electrode 16 is disposed on the first semiconductor layer 121 and electrically connected to the first semiconductor layer 121, for example, in the present embodiment, the first electrode 16 is electrically connected to the first semiconductor layer 121 by directly contacting. When the first semiconductor layer 121 is an n-type semiconductor layer, the corresponding first electrode 16 is also referred to as an n-type electrode.
The flip-chip type light emitting diode 10 further includes a buffer layer (not shown) disposed between the first semiconductor layer 121 and the substrate 11. When the first semiconductor layer 121 is an n-type semiconductor layer, the buffer layer may be an n-type GaN buffer layer, and the buffer layer may specifically be a GaN layer doped with at least one of Si, Ge, and Sn; when the first semiconductor layer 121 is a p-type semiconductor layer, the buffer layer may Be a p-type GaN buffer layer, and the buffer layer may Be a GaN layer doped with at least one of Mg, Zn, Be, Ca, Sr, and Ba.
The flip-chip type light emitting diode 10 further includes: a protective metal layer (not shown) disposed on a side of the mirror layer 14 away from the ohmic contact patterns 13, wherein the protective metal layer is made of aluminum, silver, titanium, nickel, gold, platinum, chromium, tin, tungsten, or an alloy of any two or more of the above metals.
As shown in fig. 4, the present application also proposes a method of manufacturing a light emitting diode, which is used to manufacture the flip-chip type light emitting diode 10 in the above-described embodiment. The method comprises the following steps:
s101: a substrate 11 is provided.
The material of the substrate 11 mentioned above is not particularly limited, but any known material that can be patterned and used as the nitride LED substrate 11 can be used. In general, the material may be sapphire, SiC, Si, GaN, ZnO, GaAs, GaP, LiAl, or the like, which can grow nitride semiconductor material 2 O 3 Any one of BN and AlN, but not limited thereto.
S102: a light emitting epitaxial layer 12 is formed on one side of the substrate 11.
The light emitting epitaxial layer 12 is attached to the substrate 11, the light emitting epitaxial layer 12 may be a multilayer structure, and specifically, the first semiconductor layer 121, the active light emitting layer 122, and the second semiconductor layer 123 may be sequentially grown on one side of the substrate 11 by using an MOCVD method. The first semiconductor layer 121, the active light emitting layer 122, and the second semiconductor layer 123 may be sequentially formed by a Metal-organic Chemical Vapor Deposition (MOCVD), a Molecular Beam Epitaxy (MBE), or other growth methods.
Specifically, on the substrate 11 side, a first semiconductor layer 121 is grown at 1000 to 1200 ℃. The first semiconductor layer 121 may be an n-type GaN layer, for example, a GaN layer doped with at least one of Si, Ge, and Sn. Then, the temperature is reduced to 700-900 ℃, and an active light emitting layer 122 is grown on the first semiconductor layer 121, wherein the active light emitting layer 122 may have any one of the following structures: single layer quantum wells (SQW) and Multilayer Quantum Wells (MQW). And then raising the temperature to 800-1000 ℃ to grow a second semiconductor layer 123 on the active light emitting layer 122. The second semiconductor layer 123 is a p-type GaN layer, for example, a GaN layer doped with at least one of Mg, Zn, Be, Ca, Sr, and Ba.
S103: a plurality of ohmic contact patterns 13 are formed on a side of the second semiconductor layer 123 facing away from the active light emitting layer 122.
Specifically, an ITO film or an Ag layer is deposited on a side of the second semiconductor layer 123 away from the active light emitting layer 122, and the deposition method of the ITO film or the Ag layer may be implemented by means of electron beam, sputtering, vacuum evaporation, or electroplating. And etching the ITO film or the Ag layer by adopting a mask to realize the patterning of the ITO film or the Ag layer, wherein the remained ITO film or the Ag layer is used as an ohmic contact pattern 13, and the ohmic contact patterns 13 are arranged at intervals in a lattice mode.
S104: a mirror layer 14 is formed on a side of the plurality of ohmic contact patterns 13 facing away from the active light emitting layer 122.
Specifically, the mirror layer 14 is deposited on the ITO thin film or Ag layer, the material of the mirror layer 14 may be gold, aluminum, silver, platinum, chromium, nickel or other suitable metals, and the deposition method of the mirror layer 14 may be implemented by means of electron beam, sputtering, vacuum evaporation or electroplating.
Further, step S103 specifically includes: the plurality of ohmic contact patterns 13 are subjected to an annealing process.
Specifically, the plurality of ohmic contact patterns 13 are subjected to a rapid annealing process in an annealing furnace in a nitrogen atmosphere to form ohmic contacts of the plurality of ohmic contact patterns 13 with the second semiconductor layer. Wherein the annealing temperature is generally 350 ℃ to 550 ℃, the annealing time is generally 3 minutes to 20 minutes, and the flow rates of nitrogen and oxygen are 0.1L/min to 10L/min.
In this embodiment, the annealing process is performed on the plurality of ohmic contact patterns 13, so that the interface reaction between the ohmic contact patterns 13 and the second semiconductor layer 123 is enhanced, the contact barrier is reduced, the ohmic contact area is increased, and the ohmic contact resistance is reduced.
Step S104 specifically includes: the annealing process is not performed on the mirror layer 14 so that the reflectivity of the mirror layer 14 is greater than the plurality of ohmic contact patterns 13.
As shown in fig. 5, before step S102, the method further includes:
s105: a buffer layer is formed on one main surface of the substrate 11.
In this step, a buffer layer may be grown on one main surface of the substrate 11 by a conventional MOCVD process or by means of, for example, physical vapor deposition, sputtering, hydrogen vapor deposition or atomic layer deposition process.
Further, step S102 includes:
s21: a light-emitting epitaxial layer 12 is formed on the side of the buffer layer facing away from the substrate 11.
Wherein: when the first semiconductor layer 121 is an n-type semiconductor layer, the buffer layer may be an n-type GaN buffer layer, and the buffer layer may specifically be a GaN layer doped with at least one of Si, Ge, and Sn; when the first semiconductor layer 121 is a p-type semiconductor layer, the buffer layer may Be a p-type GaN buffer layer, and the buffer layer may Be a GaN layer doped with at least one of Mg, Zn, Be, Ca, Sr, and Ba.
It should be noted that the above-mentioned design concept based on the flip-chip type led 10 is also applicable to the vertical type led.
As shown in fig. 6 to 7, a vertical type light emitting diode 20 according to a fourth embodiment of the present application includes: a transfer substrate 21, a mirror layer 22, a plurality of ohmic contact patterns 23, and a light emitting epitaxial layer 24. The light emitting epitaxial layer 24 includes a second semiconductor layer 243, an active light emitting layer 242, and a first semiconductor layer 241, which are sequentially stacked on one side of the transfer substrate 21.
It is to be understood that the transfer substrate 21 in the present embodiment corresponds to the substrate 11 in the above-described embodiment.
The ohmic contact patterns 23 are arranged at intervals in a lattice manner on a side of the second semiconductor layer 243 away from the active light emitting layer 242, and the mirror layer 22 is located on a side of the ohmic contact patterns 23 away from the active light emitting layer 242, that is, the mirror layer 22 is disposed between the transfer substrate 21 and the active light emitting layer 242. Meanwhile, the mirror layer 22 covers the plurality of ohmic contact patterns 23 and the second semiconductor layer 243 between the plurality of ohmic contact patterns 23.
Wherein the mirror layer 22 is in direct contact with the second semiconductor layer 243 between the plurality of ohmic contact patterns 23, or the mirror layer 22 between the plurality of ohmic contact patterns 23 is in direct contact with the second semiconductor layer 243.
The first electrode 25 is disposed on a side of the first semiconductor layer 241 far from the active light emitting layer 242, and the first electrode 25 is electrically connected to the first semiconductor layer 241, for example, in this embodiment, the first electrode 25 is electrically connected to the first semiconductor layer 241 by direct contact. When the first semiconductor layer 241 is an n-type semiconductor layer, for example, an n-type GaN semiconductor layer, the corresponding first electrode 25 is also referred to as an n-type electrode.
In this embodiment, the transfer substrate 21 may be made of a conductive material such as Si, Ge, Cu, CuW, etc., and is not limited herein. The second electrode 26 is disposed on the side of the transfer substrate 21 remote from the mirror layer 22, and the second electrode 26 is electrically connected to the second semiconductor layer 243 through the transfer substrate 21. When the second semiconductor layer 243 is a p-type semiconductor layer, for example, a p-type GaN semiconductor layer, the corresponding second electrode 26 is also referred to as a p-type electrode.
The vertical type light emitting diode 20 further includes: and a metal bonding layer 29, wherein the metal bonding layer 29 is arranged between the reflector layer 22 and the transfer substrate 21 so as to improve the adhesion strength of the reflector layer 22. The material of the metal bonding layer 29 may be at least one of In, Cu, Au, Ni, Ti, and Sn, or an alloy thereof, which is not limited herein.
As shown in fig. 8 and 9, the present application also proposes a method of manufacturing a light emitting diode, which is used to manufacture the vertical type light emitting diode 20 in the above-described embodiment. The method comprises the following steps:
s201: a substrate 27 is provided.
S202: a buffer layer 28 is formed on one main surface of the substrate 27.
The specific process of step S202 can refer to step S105 in the above embodiment, which is not described herein.
S203: a light-emitting epitaxial layer 24 is formed on the side of the buffer layer 28 facing away from the substrate 27.
The light-emitting epitaxial layer 24 is attached to the buffer layer 28, and the light-emitting epitaxial layer 24 may have a multilayer structure, and specifically, a first semiconductor layer 241, an active light-emitting layer 242, and a second semiconductor layer 243 may be sequentially grown on one side of the substrate 27 by using an MOCVD method. The first semiconductor layer 241, the active light emitting layer 242, and the second semiconductor layer 243 may be sequentially formed by a growth method such as Metal-organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE).
S204: a plurality of ohmic contact patterns 23 are formed on a side of the second semiconductor layer 243 facing away from the active light emitting layer 242. Wherein the plurality of ohmic contact patterns 23 are spaced apart in a lattice manner.
The specific process of step S204 can refer to S103 in the above embodiment, which is not described herein.
S205: the mirror layer 22 is formed at a side of the plurality of ohmic contact patterns 23 facing away from the active light emitting layer 242.
The specific process of step S205 can refer to S104 in the above embodiment, which is not described herein.
Wherein the mirror layer 22 covers the plurality of ohmic contact patterns 23 and the second semiconductor layer 243 between the plurality of ohmic contact patterns 23.
Further, the method further comprises:
s206: the transfer substrate 21 is bonded on the side of the mirror layer 22 facing away from the active light emitting layer 242.
Specifically, the transfer substrate 21 may employ a conductive material such as Si, Ge, Cu, CuW, or the like. The first metal bonding layer 291 is formed on the mirror layer 22 by thermal evaporation, electron beam evaporation, magnetron sputtering evaporation, or the like. A second metal bonding layer 292 is further formed on one main surface of the transfer substrate 21 by a method such as thermal evaporation, electron beam evaporation, magnetron sputtering evaporation, or the like. Finally, the first and second metal bonding layers 291 and 292 are bonded through a bonding process. The material of the first metal bonding layer 291 and the second metal bonding layer 292 may be at least one of In, Cu, Au, Ni, Ti, and Sn, or an alloy thereof, which is not limited herein. The first and second metal bonding layers 291 and 292 constitute a metal bonding layer 29.
S207: the buffer layer 28 is removed to peel off the substrate 27 from the contact surface between the buffer layer 28 and the substrate 27, with the buffer layer 28 being a peeling sacrificial layer.
Since the first electrode 25 is disposed on the side of the first semiconductor layer 241 remote from the active light emitting layer 242 and the second electrode 26 is disposed on the side of the transfer substrate 21 remote from the mirror layer 22 in the vertical type light emitting diode 20 and is electrically connected to the first semiconductor layer 241 and the second semiconductor layer 243, respectively, it is necessary to peel off the substrate 27. In this step, the buffer layer 28 may be removed by dry etching, wet etching, or a combination thereof, thereby peeling the substrate 27.
The above are only embodiments of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent processes performed by the present application and the contents of the attached drawings, which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (8)
1. A light emitting diode, comprising:
a substrate;
the light-emitting epitaxial layer comprises a first semiconductor layer, an active light-emitting layer and a second semiconductor layer which are sequentially stacked and arranged on one side of the substrate;
a plurality of ohmic contact patterns which are arranged at intervals in a lattice mode on one side of the second semiconductor layer, which is far away from the active light-emitting layer;
the reflecting mirror layer is positioned on one side of the ohmic contact patterns, which is far away from the active light-emitting layer, and covers the ohmic contact patterns and the second semiconductor layer between the ohmic contact patterns;
the light emitting diode further comprises a transparent dielectric layer arranged in the spacing area between the ohmic contact patterns, and the reflector layer is in direct contact with the transparent dielectric layer;
the electrode layer is arranged on one side, away from the ohmic contact patterns, of the reflector layer, and the bonding pad is electrically connected with the electrode layer, wherein the areas of the ohmic contact patterns are gradually increased in the direction away from the bonding pad.
2. The led of claim 1, wherein said mirror layer has a reflectivity greater than said plurality of ohmic contact patterns.
3. The led of claim 2, wherein the plurality of ohmic contact patterns are treated with an annealing process and the reflector layer is not treated with the annealing process.
4. The led of claim 2, wherein the plurality of ohmic contact patterns are ITO patterns or Ag patterns, and the mirror layer is an Ag layer.
5. The led of claim 1, wherein the thickness of the mirror layer is 0.01-1 μm, and the thickness of the plurality of ohmic contact patterns is 0.01-1 μm.
6. A method of manufacturing a light emitting diode, the method comprising:
providing a substrate;
forming a light-emitting epitaxial layer on one side of the substrate, wherein the light-emitting epitaxial layer comprises a first semiconductor layer, an active light-emitting layer and a second semiconductor layer which are sequentially stacked;
forming a plurality of ohmic contact patterns on one side of the second semiconductor layer, which is far away from the active light-emitting layer, wherein the ohmic contact patterns are arranged at intervals in a lattice manner;
forming a mirror layer on a side of the ohmic contact patterns facing away from the active light emitting layer, wherein the mirror layer covers the ohmic contact patterns and the second semiconductor layer between the ohmic contact patterns;
arranging a transparent dielectric layer in the interval area between the ohmic contact patterns, wherein the reflector layer is in direct contact with the transparent dielectric layer;
the electrode layer is arranged on one side, away from the ohmic contact patterns, of the reflector layer, and the bonding pad is electrically connected with the electrode layer, wherein the areas of the ohmic contact patterns are gradually increased in the direction away from the bonding pad.
7. The method of claim 6, wherein the step of forming a plurality of ohmic contact patterns on a side of the second semiconductor layer facing away from the active light emitting layer comprises: carrying out annealing process treatment on the plurality of ohmic contact patterns;
the step of forming a mirror layer on a side of the ohmic contact patterns facing away from the active light emitting layer includes: and not performing an annealing process on the mirror layer so that the reflectivity of the mirror layer is greater than the plurality of ohmic contact patterns.
8. The method of claim 6, wherein the step of forming a light emitting epitaxial layer on one side of the substrate comprises:
forming a buffer layer on one main surface of the substrate;
forming the light-emitting epitaxial layer on one side of the buffer layer, which is far away from the substrate;
the method further comprises the following steps:
bonding a transfer substrate on the side of the reflector layer, which is far away from the active light-emitting layer;
and taking the buffer layer as a stripping sacrificial layer, and removing the buffer layer so as to strip the substrate from the contact surface of the buffer layer and the substrate.
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