CN108461586B - Vertical structure LED chip based on NiO nano-dot reflector and preparation method thereof - Google Patents
Vertical structure LED chip based on NiO nano-dot reflector and preparation method thereof Download PDFInfo
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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Abstract
The invention discloses a vertical structure LED chip based on a NiO nano-dot reflector and a preparation method thereof. The array NiO nanodots prepared by the ultraviolet nanoimprint technology replace the traditional Ni layer and are used as the ohmic contact layer of the Ag reflector, so that the light absorption problem of the Ni layer is reduced, and the Schottky barrier between NiO and p-GaN is greatly reduced because NiO is a p-type semiconductor, and the reflection efficiency of the reflector is improved. The NiO array nano-dot has quantum size effect and three-dimensional grating effect on the nano scale, and can further improve the light emitting efficiency of the LED chip with the vertical structure. The double-layer adhesive process adopted by the invention greatly optimizes the precision of lift-off NiO, thereby modifying the morphology of NiO nanodots.
Description
Technical Field
The invention relates to the field of LED manufacturing, in particular to a vertical structure LED chip based on a NiO nano-dot reflector and a preparation method thereof.
Background
With the gradual application of LEDs in the field of illumination, the market is no longer satisfied with the horizontal structure LEDs and vertical structure LEDs of small current driven sapphire substrates. Compared with the LED with the horizontal structure, the LED with the vertical structure has the characteristics of vertical conduction of current and electric conduction of a substrate by virtue of the two sides of the P, N electrode array, and can perfectly solve the problems of poor heat conductivity, current crowding effect and electrode light absorption effect of the horizontal structure, so that the LED can bear high-current overdrive. The introduction of the reflector enables the single face of the LED with the vertical structure to emit light, so that the external quantum efficiency of the LED chip with the vertical structure is greatly improved compared with that of the LED chip with the horizontal structure, the effect of reducing the luminous efficiency generated by the increase of current is also solved, and the stability of the LED chip with the vertical structure is greatly enhanced. And the vertical structure generally adopts a silicon substrate which is low in cost and easy to prepare to replace expensive sapphire, so that the manufacturing cost is greatly reduced. Therefore, gaN-based vertical structure LEDs are the market place oriented and are a necessary trend for the development of semiconductor illumination.
At present, a vertical structure LED chip mostly adopts a Ni/Ag-based laminated reflecting mirror, and the specific process flow is that an electron beam evaporation machine is used for growing Ni/Ag layer metal on p-GaN, then alloying treatment is carried out in a rapid annealing furnace, ohmic contact can be formed although annealing is carried out, the problem of poor adhesion of an Ag layer can be solved by the Ni layer, meanwhile, the work function of the Ni layer reaches 5.15eV which is far higher than 4.25eV of the Ag layer, ohmic contact can be better formed in the annealing heat treatment process, and the Schottky barrier is reduced. However, the Ni layer is an opaque metal, and has a strong light absorption problem, light emitted by the quantum well is absorbed, ni is oxidized in pure oxygen atmosphere to obtain NiO, which is a p-type transparent semiconductor, and the forbidden bandwidth of NiO is larger than that of Ni, so that the work function of NiO is increased, the schottky barrier of NiO and p-GaN is remarkably reduced compared with that of Ni and p-GaN, and NiO has high light transmittance. Thus NiO can be used as a contact layer for Ag-based ohmic mirrors instead of Ni layers. And when the particle size is reduced to a certain value, the electron energy level near the fermi level is determined by quasi-continuous
Continuously becomes a discrete energy level or a phenomenon that the energy gap becomes wider. As the particle size decreases to the nano-dot quantum dot size, quantum size effects and grating effects are exhibited, thereby enhancing the reflection efficiency of the Ag mirror. The nano imprinting technology can achieve the aim, and nano points with array arrangement and different patterns can be manufactured, so that NiO can be completely manufactured into NiO nano points by adopting a nano imprinting method, a nano grating is formed, and the reflectivity of the Ag-based reflector is enhanced.
Disclosure of Invention
In order to overcome the defects and shortcomings of the prior art, the invention aims to provide the vertical structure LED chip based on the NiO nano-dot reflector and the preparation method thereof, wherein p-type semitransparent NiO nano-dots are manufactured by means of nano-imprinting to form a semitransparent nano-grating, an opaque metal film Ni is replaced, and the reflection efficiency of the Ag reflector is enhanced, so that the light output power and the external quantum efficiency of the vertical structure LED chip are improved.
The aim of the invention is achieved by the following technical scheme.
A preparation method of a vertical structure LED chip based on a NiO nano-dot reflector comprises the following steps:
(1) Cleaning an LED epitaxial wafer: carrying out material feeding cleaning on the silicon substrate LED epitaxial wafer; the silicon substrate LED epitaxial wafer comprises a silicon substrate, an n-GaN layer on the silicon substrate, an InGaN/GaN multi-quantum well layer on the n-GaN layer, and a p-GaN layer on the InGaN/GaN multi-quantum well layer;
(2) Spin-coating a first NOA61, namely spin-coating the first NOA61 on the surface of the p-GaN layer of the cleaned silicon substrate epitaxial wafer, and baking the spin-coated first NOA 61;
(3) Spin-coating a second NOA61, namely spin-coating the second NOA61 on the surface of the first NOA61, wherein baking is not performed after spin-coating;
(4) Nanoimprinting: imprinting is carried out by adopting a nano imprinting template, and the patterns on the imprinting template are transferred to a first layer NOA61 and a second layer NOA 61; after imprinting, using an ultraviolet light source to irradiate the imprinting template to solidify the first layer NOA61, the second layer NOA61 and the transfer pattern; the imprinting pressure of the imprinting is 300-800 mbar, the imprinting temperature is normal temperature, and the imprinting time is 2-5 min; the irradiation is carried out at 365nm wavelength and 16.4mW/cm light source intensity 2 Irradiating the substrate for 4-8 min by an ultraviolet light source;
(5) Residual glue etching: etching the residual glue on the p-GaN layer at the stamping pattern obtained in the step (4) by adopting an inductive coupling plasma technology, and modifying the angle of the obtained NOA 61;
(6) Sputtering a NiO layer: sputtering a NiO layer on the surface of the NOA61 by adopting a magnetron sputtering process; the Ni/O mole ratio of the NiO source used for sputtering NiO is 1:1, a step of; the thickness of the NiO layer is 1-20 nm; the DC sputtering power in the sputtering process is 0.3-1.5 kW, and the sputtering air pressure is 2-8 multiplied by 10 -3 mbar；
(7) Lift-off: removing the first and second NOA61 layers and NiO on the first and second NOA61 layers by adopting a lift-off process of tearing the NOA61 by using a blue film, leaving array NiO nano-dots, and then cleaning residual glue on the surface of the p-GaN layer;
(8) Annealing of NiO: annealing the LED epitaxial wafer containing the array NiO nano-dots obtained in the step (7);
(9) Sputtering an Ag/Z layer, namely sputtering the Ag/Z layer on the surface of the array NiO nano-dots by adopting a magnetron sputtering process, wherein the Ag/Z layer comprises an Ag layer and a Z layer; no annealing is required after sputtering the Ag/Z layer;
(10) Bonding and substrate transfer: evaporating Cr/Pt protective layers on the Ag/Z layers by using electron beam evaporation, evaporating Au/Sn bonding layers, evaporating the same Au/Sn bonding layers on the polished surfaces of the conductive Si (100) substrates, and bonding the prepared LED epitaxial wafer containing the reflector, the Cr/Pt protective layers and the Au/Sn bonding layers with the conductive Si (100) substrate by using a metal high-temperature bonding mode, wherein the bonding surfaces are the Au/Sn bonding layers of the LED epitaxial wafer and the Au/Sn bonding layers on the Si (100) substrate; then, evaporating a Pt layer on the bonded Si (100) substrate to serve as a Si (100) substrate protective layer, and stripping the original epitaxial Si substrate by using a chemical etching method;
(11) Preparing a PA layer and an n electrode: deposition of SiO by PECVD 2 And sequentially preparing an LED chip n electrode pattern by adopting a photoresist homogenizing, photoetching and developing standard photoetching process, sequentially depositing a Pd/Al/Pt n electrode layer on the upper surface of the epitaxial wafer n-GaN layer, and removing redundant electrode metal by adopting a blue film pasting and stripping mode to prepare the LED chip with the vertical structure.
Preferably, the solution for cleaning in the step (1) is a mixed solution of sulfuric acid, hydrogen peroxide and water, and the volume ratio of sulfuric acid to hydrogen peroxide to water is 1:1: 1-5: 1:1, the sulfuric acid is concentrated sulfuric acid with mass fraction more than 70%.
Preferably, the rotating speed of the spin coating in the step (2) is 1000-3000 rpm, and the time is 30-50 seconds; the baking temperature is 90-150 ℃ and the baking time is 90-180 seconds.
Preferably, the rotation speed of the spin coating in the step (3) is 1000-3000 rpm, and the time is 30-50 seconds.
Preferably, the etching gas used for etching the residual photoresist and modifying the photoresist angle in the step (5) is O 2 The etching rate is 3-10A/s, the etching time is 600-2000 s, and the etching is powered downThe pole power is 80-100W.
Preferably, the annealing atmosphere in the step (8) is N 2 /O 2 Mixture gas, N in the mixture gas 2 ：O 2 The flow ratio of (2) is 1: 1-5: 1, a step of; the annealing temperature is 150-500 ℃ and the annealing time is 10-300 seconds.
Preferably, the thickness of the Ag layer in the step (9) is 200-500 nm, the DC sputtering power in the sputtering process is 3-7 kW, and the sputtering air pressure is (15-25) multiplied by 10 -3 mbar; the material used for sputtering the Z layer is more than one of Ti, mg, W, ni and Al, the DC sputtering power is 0.5-2.5 kW, and the sputtering air pressure is (2-7) multiplied by 10 -3 mbar; the thickness of the Z layer is 50-200 nm.
Preferably, the thickness of Cr in the Cr/Pt protective layer in the step (10) is 10-30 nm, and the thickness of Pt is 100-300 nm; the thickness of Sn in the Au/Sn bonding layer is 1-3 mu m, and the thickness of Au is 10-200 nm; the bonding temperature is 200-500 ℃, and the bonding time is 10-20 minutes; the thickness of the Pt layer is 200-300 nm; the volume ratio of the solution used for corrosion is 1: 1-1:4 of hydrofluoric acid and nitric acid.
Preferably, the photoresist is negative photoresist, and the photoresist homogenizing time is 40-200 seconds; the photoetching time is 3-30 seconds, the developing solution adopts negative photoresist developing solution, and the developing time is 20-300 seconds; the Pd thickness in the Pd/Al/Pt n electrode layer is 10-100 nm, the Al thickness is 0.5-2 um, and the Pt thickness is 10-200 nm.
The vertical structure LED chip based on the NiO nano-dot reflector, which is manufactured by the manufacturing method, sequentially comprises a Si (100) substrate 1, an Au/Sn bonding layer 2, a Cr/Pt protective layer 3, an array NiO nano-dot/Ag/Z reflector 4, a p-GaN layer 5, an InGaN/GaN multi-quantum well layer 6, an n-GaN layer 7 and Pd/Al/Pt n electrode layers 8 which are respectively arranged on two sides of the upper surface of the n-GaN layer 7 from bottom to top; the array NiO nano-dot/Ag/Z reflecting mirror 4 sequentially comprises an array NiO nano-dot layer 401, an Ag layer 402 and an anti-oxidation Z layer 403; the array NiO nanodots are deposited layer by layer on the p-GaN layer.
The invention firstly obtains a silicon substrate LED epitaxial wafer, and the structure of the epitaxial wafer comprises a silicon substrate, an n-GaN layer on the silicon substrate, an InGaN/GaN multi-quantum well layer on the n-GaN layer and a p-GaN layer on the InGaN/GaN multi-quantum well layer. Then, preparing a NiO array nano-dot/Ag reflecting mirror on the surface of the LED epitaxial wafer by adopting means of photoetching combined with nano-imprinting, inductively coupled plasma etching standard photoetching, sputtering and the like, and preparing a reflecting mirror protecting layer, a bonding layer and the like on the reflecting mirror protecting layer; transferring the LED epitaxial layer onto a highly doped conductive Si (100) substrate by using a bonding machine, and stripping an old growth substrate by combining a thinning machine and a chemical corrosion method; then preparing an MESA channel and a PA layer by utilizing equipment such as PECVD, ICP and the like; and then preparing an n-electrode pattern by a standard photoetching process, preparing an n-electrode by using an electron beam evaporation method, removing redundant electrode metal by using a Lift-off mode, and finally forming the preparation of the complete LED chip with the vertical structure.
The preparation process of the NiO array nano dot/Ag reflecting mirror comprises the following parts:
the first step: on the p-GaN surface of the silicon substrate LED epitaxial wafer, a double-layer ultraviolet imprinting photoresist NOA61 is prepared by adopting a double-layer glue process and a baking process (Norland Optical Adhesive).
And a second step of: then carrying out imprinting and ultraviolet curing treatment by a nano imprinting machine to form patterned PMMA, and removing residual glue in the imprinted pattern by combining an inductively coupled plasma etching process (ICP);
and a third step of: and preparing the NiO ohmic contact layer by adopting a magnetron sputtering process, stripping off the glued area by adopting a lift-off process, and leaving array NiO nano-dots.
Fourth step: and preparing an Ag/Z reflecting mirror layer by adopting a magnetron sputtering process, and annealing in a rapid annealing furnace.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) According to the LED chip with the vertical structure based on the NiO nano-dot reflector, the array NiO nano-dots are prepared by using an ultraviolet nano-imprinting technology to replace a traditional Ni layer and serve as an ohmic contact layer of an Ag reflector, so that the light absorption problem of the Ni layer is reduced, and meanwhile, due to the fact that NiO is a p-type semiconductor, the Schottky barrier between NiO and p-GaN is greatly reduced, and the reflection efficiency of the reflector is improved.
(2) The NiO array nano-dot has quantum size effect and three-dimensional grating effect on the nano scale, and can further improve the light emitting efficiency of the LED chip with the vertical structure.
(3) The double-layer adhesive process adopted by the invention greatly optimizes the precision of lift-off NiO, thereby modifying the morphology of NiO nanodots.
Drawings
Fig. 1 is a schematic structural diagram of an LED chip with a vertical structure according to the present invention.
Fig. 2 is a schematic structural diagram of NiO nanodot/Ag/Z mirrors in a vertical structure LED chip of the invention.
FIG. 3 is a flow chart of the double layer glue-lift-off process for preparing array NiO nanodots.
FIG. 4a is an AFM image of a Ni layer in a conventional Ni/Ag mirror;
FIG. 4b is a two-dimensional AFM image of NiO array nanodots in a NiO nanodot/Ag/Z mirror according to example 1 of the present invention;
FIG. 4c is a three-dimensional AFM image of NiO array nanodots in a NiO nanodot/Ag/Z mirror according to example 1 of the present invention;
FIG. 5a is a LOP-mapping diagram of a conventional Ni/Ag mirror vertical structure LED chip;
FIG. 5b is a schematic diagram of a conventional Ni/Ag mirror vertical structure LED chip Vf 2-mapping;
FIG. 6a is a LOP-mapping diagram of an LED chip with a vertical structure of NiO nanodots/Ag/Z mirrors according to example 1 of the present invention;
FIG. 6b is a schematic diagram of a vertical structure LED chip Vf2-mapping of the NiO nanodot/Ag/Z mirror according to example 1 of the present invention;
FIG. 7a is a LOP-mapping diagram of an LED chip with a vertical structure of NiO nanodots/Ag/Z mirrors according to example 2 of the present invention;
fig. 7b is a view showing the structure of the NiO nanodot/Ag/Z mirror vertical structure LED chip Vf2-mapping in example 2 of the invention.
Detailed Description
The following describes the embodiments of the present invention in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
The structural schematic diagram of the LED chip with the vertical structure is shown in fig. 1, and the LED chip with the vertical structure sequentially comprises a Si (100) substrate 1, an Au/Sn bonding layer 2, a Cr/Pt protective layer 3, an array NiO nano-dot/Ag/Z reflector 4, a p-GaN layer 5, an InGaN/GaN multi-quantum well layer 6, an n-GaN layer 7 and Pd/Al/Pt n electrode layers 8 which are respectively arranged on two sides of the upper surface of the n-GaN layer 7 from bottom to top; the schematic structural diagram of the array NiO nano-dot/Ag/Z mirror 4 is shown in fig. 2, and the array NiO nano-dot/Ag/Z mirror sequentially includes an array NiO nano-dot layer 401, an Ag layer 402, and an anti-oxidation Z layer 403; the array NiO nanodot layer 401 is deposited on the p-GaN layer 5. .
Example 1
(1) And cleaning the epitaxial wafer, namely carrying out material feeding cleaning on the obtained silicon substrate LED epitaxial wafer, wherein the silicon substrate LED epitaxial wafer comprises a silicon substrate, an n-GaN layer on the silicon substrate, an InGaN/GaN multi-quantum well layer on the n-GaN layer and a p-GaN layer on the InGaN/GaN multi-quantum well layer. The cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide and water (the volume ratio is 3:1:1). The sulfuric acid is concentrated sulfuric acid (sulfuric acid aqueous solution with mass fraction more than 70%). The silicon substrate has a (111) plane as an epitaxial plane. The thickness of the n-GaN layer is 3um, and the doping concentration is 5x10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The InGaN/GaN multiple quantum well is 10 cycles of InGaN well layer/GaN barrier layer, wherein the thickness of the InGaN well layer is 10nm, the thickness of the GaN barrier layer is 5nm, the thickness of the p-GaN layer is 300nm, and the doping concentration is 5x10 17 cm -3 。
(2) Spin-coating a first layer NOA61, namely spin-coating the first layer NOA61 on the surface of the p-GaN layer of the cleaned silicon substrate epitaxial wafer by using a spin-coating spin coater, wherein the spin-coating rotating speed is 3000 r/s, the spin-coating time is 30 seconds, baking the spin-coated first layer NOA61, and the baking temperature is 120 ℃ and the baking time is 100 seconds;
(3) Spin coating the second layer of NOA 61. Spin coating the second layer of NOA61 on the surface of the first layer of NOA61 by using a spin-coating spin coater, wherein the spin coating speed is 3000 rpm, the spin coating time is 30 seconds, and baking is not performed.
(4) Nanoimprinting: the prepared nano-imprint template is adopted to carry out imprinting on NOA61, the imprinting pressure is 500mbar,the imprinting time was 2min, the imprinting temperature was ambient, and the pattern on the imprint template was transferred to NOA 61. After imprinting, 365nm wave band is used, and the light source intensity is 16.4mW/cm 2 The ultraviolet light source of (a) irradiates the imprint template to cure the NOA61 and the transferred pattern. The ultraviolet irradiation time is 6min.
(5) Residual glue etching: etching residual glue on p-GaN at the imprinting pattern by adopting inductive coupling plasma technology, wherein etching gas is O 2 The etching rate is 10A/s, the etching time is 600s, and the power of the etched lower electrode is 80W.
(6) Sputtering NiO, namely sputtering Ni/O on the surface of NOA61 by adopting a magnetron sputtering process, wherein the mole ratio of Ni/O is 1:1, the thickness of the NiO layer is 3nm, the DC sputtering power is 1kW, and the sputtering air pressure is 3.5X10 -3 mbar, sputtering time was 10 seconds.
(7) Lift-off: and removing the first layer NOA61, the second layer NOA61 and the NiO on the surface by adopting a lift-off process of tearing the NOA61 by using a blue film, leaving array NiO nanodots, and cleaning residual glue on the p-GaN surface by adopting a special glue removal solution RCL-LE10, wherein the preparation flow is shown in a figure 3.
(8) Annealing of NiO: carrying out low-temperature annealing on the LED epitaxial wafer containing the array NiO nano-dots obtained in the step (7) in a rapid annealing furnace, wherein the annealing atmosphere is N 2 /O 2 The flow ratio of the mixed gas and the atmosphere is N 2 ：O 2 =4: 1 at 400℃for 60 seconds.
(9) Sputtering Ag/Z layer: sputtering Ag/Z layer on the surface of NiO layer by magnetron sputtering process, wherein the thickness of Ag layer is 200nm, the DC sputtering power is 3.5kW, and the sputtering air pressure is 20×10 -3 mbar, sputtering time is 1000 seconds; the Z oxidation-resistant layer is Mg, the thickness is 75nm, the DC sputtering power is 1.5kW, and the sputtering air pressure is 5 multiplied by 10 -3 mbar, sputtering time 375 seconds, no annealing after said Ag/Mg; the AFM image of the Ni layer in the conventional Ni/Ag mirror is shown in fig. 4a, and the two-dimensional AFM image and the three-dimensional AFM image of the NiO array nanodots in the NiO nanodot/Ag/Z mirror obtained in this embodiment are shown in fig. 4b and fig. 4c, so that the particle diameter of the NiO nanodot obtained in this embodiment is about 125nm.
(10) Bonding and substrate transfer: evaporating Cr/Pt protective layer metal on the nano Ag reflector by using an electron beam, wherein the thickness of Cr is 10nm, and the thickness of Pt is 200nm; and evaporating an Au/Sn bonding layer, wherein the thickness of Sn is 3 mu m, and the thickness of Au is 200nm. And then the same Au/Sn bonding layer is also evaporated on the polished surface of the conductive Si (100) substrate, and the prepared LED epitaxial wafer containing the reflector, the Cr/Pt protective layer and the Au/Sn bonding metal is bonded with the conductive Si (100) substrate by using a metal high-temperature bonding mode, wherein the bonding surface is the Au/Sn bonding layer of the LED epitaxial wafer and the Au/Sn bonding layer on the Si (100) substrate, and the bonding temperature is 300 ℃ and the bonding time is 20 minutes. Next, pt was vapor deposited as a protective layer of Si (100) substrate on the bonded Si (100) substrate, and the thickness thereof was 300nm. The original epitaxial Si substrate is stripped by using a chemical etching method, wherein an etching solution is mixed solution of hydrofluoric acid and nitric acid, and the volume ratio is 1:2.
(11) Preparing a PA layer and an n electrode: subsequently, siO is deposited by PECVD 2 The passivation layer sequentially prepares n electrode patterns of the LED chip by adopting standard photoetching processes such as photoresist homogenizing, photoetching, developing and the like, wherein the photoresist homogenizing adopts negative photoresist, and the photoresist homogenizing time is 55 seconds; the photolithography time was 5 seconds, and the development time was 55 seconds using a negative photoresist developer. And sequentially depositing Pd/Al/Pt n electrode metal on the upper surface (n-GaN layer) of the epitaxial wafer by using an electron beam evaporation device, wherein the Pd thickness is 15 nm, the Al thickness is 1um, and the Pt thickness is 200nm. And removing redundant electrode metal by adopting a blue film pasting and stripping mode to prepare the LED chip with the vertical structure. And testing by a point measuring machine to obtain the photoelectric performance parameters of the LED.
FIGS. 5a and 5b are vertical structure LED chips LOP and VF of a conventional Ni/Ag mirror 2 Can be seen from the mapping graph of (1) in LOP and VF 2 Is 405 mW and 3.2V. FIGS. 6a and 6b are graphs showing LED chips LOP and VF of the vertical structure based on the array NiO nanodots/Ag/Mg mirrors according to the present embodiment 2 The average of LOP and Vf2 was found to be 483mW and 2.93V. In contrast, the photoelectric performance of the vertical junction LED chip of the array NiO nanodot/Ag/Mg mirror obtained in this embodiment is greatly improved, where the LOP value is improved by 19.2% and the voltage value is reduced by 8.43%.
Example 2
(1) And cleaning the epitaxial wafer, namely carrying out material feeding cleaning on the obtained silicon substrate LED epitaxial wafer, wherein the silicon substrate LED epitaxial wafer structure comprises a silicon substrate, n-GaN on the silicon substrate, an InGaN/GaN multi-quantum well layer on the n-GaN layer and a p-GaN layer on the InGaN/GaN multi-quantum well layer. The cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide and water, and the proportion range is 3:1:1. the sulfuric acid is concentrated sulfuric acid (sulfuric acid aqueous solution with mass fraction more than 70%). The silicon substrate has a (111) plane as an epitaxial plane. The thickness of the n-GaN layer is 3um, and the doping concentration is 5x10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The InGaN/GaN multiple quantum well is 10 cycles of InGaN well layer/GaN barrier layer, wherein the thickness of the InGaN well layer is 10nm, the thickness of the GaN barrier layer is 5nm, the thickness of the p-GaN layer is 300nm, and the doping concentration is 5x10 17 cm -3 。
(2) Spin-coating a first layer NOA61, namely spin-coating the first layer NOA61 on the p-GaN surface of the cleaned silicon substrate epitaxial wafer by a spin-coating spin coater, wherein the spin-coating speed is 2000 rpm, the spin-coating time is 40 seconds, baking the spin-coated first layer NOA61, and the baking temperature is 100 ℃ and the baking time is 120 seconds;
(3) Spin coating the second layer of NOA 61. Spin coating the second layer of NOA61 on the surface of the first layer of NOA61 by using a spin-coating spin coater, wherein the spin coating speed is 2000 rpm, the spin coating time is 45 seconds, and baking is not performed.
(4) Nanoimprinting: and (3) imprinting is carried out by adopting the prepared nano imprinting template, the imprinting pressure is between 400mbar, the imprinting time is 3min, the imprinting temperature is normal temperature, and the pattern on the imprinting template is transferred to the NOA 61. After imprinting, 365nm wave band is used, and the light source intensity is 16.4mW/cm 2 The ultraviolet light source of (a) irradiates the imprint template to cure the NOA61 and the transferred pattern. The ultraviolet irradiation time is 6min.
(5) Residual glue etching: etching residual glue on p-GaN at the imprinting pattern by adopting inductive coupling plasma technology, wherein etching gas is O 2 The etching rate is 6A/s, the etching time is 1000s, and the power of the etched lower electrode is 90W;
(6) Sputtering NiO: by usingSputtering Ni/O ratio of 1 on the surface of the photoresist by a magnetron sputtering process: 1, the thickness of the NiO layer is 5nm, the DC sputtering power is 1.5kW, and the sputtering air pressure is 3 multiplied by 10 -3 mbar, sputtering time was 20 seconds.
(7) Lift-off: and removing the first layer NOA61, the second layer NOA61 and the NiO on the surface by adopting a lift-off process of tearing the NOA61 by using a blue film, leaving array NiO nano points, and cleaning residual glue on the p-GaN surface by adopting a special glue removing solution RCL-LE 10.
(8) Annealing of NiO: carrying out low-temperature annealing on the LED epitaxial wafer containing the array NiO nano-dots obtained in the step (7) in a rapid annealing furnace, wherein the annealing atmosphere is N 2 /O 2 Mixed gas with atmosphere proportion of N 2 ：O 2 =4: 1 at 430℃for 25 seconds.
(9) Sputtering Ag/Z layer on NiO surface by magnetron sputtering process, wherein the thickness of Ag layer is 300nm, DC sputtering power is 4kW, and sputtering air pressure is 22×10 -3 mbar, sputtering time is 1500 seconds; the Z oxidation-resistant layer material is W, the thickness is 150nm, the DC sputtering power is 2.5kW, and the sputtering air pressure is 7 multiplied by 10 -3 mbar, sputtering time 750 seconds, no annealing after said Ag/W;
(10) Bonding and substrate transfer: evaporating Cr/Pt protective layer metal on the annealed nano Ag reflector by using an electron beam, wherein the thickness of Cr is 30nm, and the thickness of Pt is 300nm; and evaporating an Au/Sn bonding layer, wherein the thickness of Sn is 3 mu m, and the thickness of Au is 200nm. And then the same Au/Sn bonding layer is also evaporated on the polished surface of the conductive Si (100) substrate, and the prepared LED epitaxial wafer containing the reflector, the Cr/Pt protective layer and the Au/Sn bonding metal is bonded with the conductive Si (100) substrate by using a metal high-temperature bonding mode, wherein the bonding surface is the Au/Sn bonding layer of the LED epitaxial wafer and the Au/Sn bonding layer on the Si (100) substrate, and the bonding temperature is 500 ℃ and the bonding time is 15 minutes. Next, pt was vapor deposited on the bonded Si (100) substrate as a Si (100) substrate protective layer, and the thickness thereof was 250 nm. The original epitaxial Si substrate is stripped by using a chemical etching method, wherein an etching solution is mixed solution of hydrofluoric acid and nitric acid, and the volume ratio is 1:2.
(11) Preparing a PA layer and an n electrode: subsequently, siO is deposited by PECVD 2 The passivation layer adopts standard photoetching processes such as photoresist homogenizing, photoetching, developing and the like to sequentially prepare n-electrode patterns of the LED chip, wherein the photoresist homogenizing adopts negative photoresist, and the photoresist homogenizing time is 66 seconds; the photolithography time was 15 seconds, and the development time was 66 seconds using a negative photoresist developer. And sequentially depositing n-electrode metals such as Pd/Al/Pt and the like on the upper surface (n-GaN layer) of the epitaxial wafer by using an electron beam evaporation device, wherein the Pd thickness is 25nm, the Al thickness is 1.5um, and the Pt thickness is 150nm. And removing redundant electrode metal by adopting a blue film pasting and stripping mode to prepare the LED chip with the vertical structure. And testing by a point measuring machine to obtain the photoelectric performance parameters of the LED.
FIGS. 5a and 5b are vertical structure LED chips LOP and VF of a conventional Ni/Ag mirror 2 Can be seen from the mapping graph of (1) in LOP and VF 2 Is 405 mW and 3.2V. FIGS. 7a and 7b are graphs showing LED chips LOP and VF of the vertical structure based on the array NiO nanodots/Ag/Mg mirrors according to the present embodiment 2 The average of LOP and Vf2 was found to be 475mW and 2.87V. In contrast, the photoelectric performance of the vertical junction LED chip of the array NiO nanodot/Ag/Mg mirror obtained in this embodiment is greatly improved, where the LOP value is improved by 17.3% and the voltage value is reduced by 10.3%.
The embodiments described above are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the embodiments described above, and any other changes, modifications, substitutions, combinations, and simplifications that do not depart from the spirit and principles of the present invention should be made in the equivalent manner, and are included in the scope of the present invention.
Claims (10)
1. The preparation method of the vertical structure LED chip based on the NiO nano-dot reflector is characterized by comprising the following steps of:
(1) The LED epitaxial wafer is cleaned, namely the LED epitaxial wafer with the silicon substrate is subjected to material feeding cleaning; the silicon substrate LED epitaxial wafer comprises a silicon substrate, an n-GaN layer on the silicon substrate, an InGaN/GaN multi-quantum well layer on the n-GaN layer, and a p-GaN layer on the InGaN/GaN multi-quantum well layer;
(2) Spin-coating a first NOA61, namely spin-coating the first NOA61 on the surface of the p-GaN layer of the cleaned silicon substrate epitaxial wafer, and baking the spin-coated first NOA 61;
(3) Spin-coating a second NOA61, namely spin-coating the second NOA61 on the surface of the first NOA61, wherein baking is not performed after spin-coating;
(4) Nanoimprinting: imprinting is carried out by adopting a nano imprinting template, and the patterns on the imprinting template are transferred to a first layer NOA61 and a second layer NOA 61; after imprinting, using an ultraviolet light source to irradiate the imprinting template to solidify the first layer NOA61, the second layer NOA61 and the transfer pattern; the imprinting pressure of the imprinting is 300-800 mbar, the imprinting temperature is normal temperature, and the imprinting time is 2-5 min; the irradiation was performed using a light source having an intensity of 16.4mW/cm 2 Irradiating the substrate for 4-8 min by an ultraviolet light source;
(5) Residual glue etching: etching the residual glue on the p-GaN layer at the stamping pattern obtained in the step (4) by adopting an inductive coupling plasma technology, and modifying the angle of the obtained NOA 61;
(6) Sputtering a NiO layer: sputtering a NiO layer on the surface of the NOA61 by adopting a magnetron sputtering process; the thickness of the NiO layer is 1-20 nm; the DC sputtering power in the sputtering process is 0.3-1.5 kW, and the sputtering air pressure is 2-8 multiplied by 10 -3 mbar；
(7) Lift-off: removing NOA61 and NiO on the NOA61 by adopting a lift-off process of tearing the NOA61 by a blue film, leaving array NiO nano points, and cleaning residual glue on the surface of the p-GaN layer;
(8) Annealing of NiO: annealing the LED epitaxial wafer containing the array NiO nano-dots obtained in the step (7);
(9) Sputtering an Ag/Z layer, namely sputtering the Ag/Z layer on the surface of the array NiO nano-dots by adopting a magnetron sputtering process, wherein the Ag/Z layer comprises an Ag layer and an anti-oxidation Z layer; no annealing is required after sputtering the Ag/Z layer;
(10) Bonding and substrate transfer: evaporating Cr/Pt protective layers on the Ag/Z layers by using electron beam evaporation, evaporating Au/Sn bonding layers, evaporating the same Au/Sn bonding layers on the polished surfaces of the conductive Si (100) substrates, and bonding the prepared LED epitaxial wafer containing the reflector, the Cr/Pt protective layers and the Au/Sn bonding layers with the conductive Si (100) substrate by using a metal high-temperature bonding mode, wherein the bonding surfaces are the Au/Sn bonding layers of the LED epitaxial wafer and the Au/Sn bonding layers on the Si (100) substrate; then, evaporating a Pt layer on the bonded Si (100) substrate to serve as a Si (100) substrate protective layer, and stripping the original epitaxial Si substrate by using a chemical etching method;
(11) Preparing a PA layer and an n electrode: deposition of SiO by PECVD 2 And sequentially preparing an LED chip n electrode pattern by adopting a photoresist homogenizing, photoetching and developing standard photoetching process, sequentially depositing a Pd/Al/Pt n electrode layer on the upper surface of the epitaxial wafer n-GaN layer, and removing redundant electrode metal by adopting a blue film pasting and stripping mode to prepare the LED chip with the vertical structure.
2. The preparation method of claim 1, wherein the solution for cleaning in the step (1) is a mixed solution of sulfuric acid, hydrogen peroxide and water, and the volume ratio of sulfuric acid, hydrogen peroxide and water is 1:1: 1-5: 1:1, the sulfuric acid is concentrated sulfuric acid with mass fraction more than 70%.
3. The method according to claim 1, wherein the spin-coating in step (2) is performed at a rotational speed of 1000 to 3000 rpm for 30 to 50 seconds; the baking temperature is 90-150 ℃ and the baking time is 90-180 seconds.
4. The method according to claim 1, wherein the spin-coating in step (3) is performed at a rotation speed of 1000 to 3000 rpm for 30 to 50 seconds.
5. The method of claim 1, wherein the etching gas used in the step (5) for etching the resist residue and for modifying the angle of the resist is O 2 The etching rate is 3-10A/s, the etching time is 600-2000 s, and the power of the etched lower electrode is 80-100W.
6. The method according to claim 1, wherein the annealing atmosphere in the step (8) is N 2 /O 2 Mixture gas, N in the mixture gas 2 ：O 2 The flow ratio of (2) is 1: 1-5: 1, a step of; the annealing temperature is 150-500 ℃ and the annealing time is 10-300 seconds.
7. The method according to claim 1, wherein the Ag layer in step (9) has a thickness of 200 to 500nm, a DC sputtering power of 3 to 7kW during sputtering, and a sputtering air pressure of (15 to 25). Times.10 -3 mbar; the material used for sputtering the Z layer is more than one of Ti, mg, W, ni and Al, the DC sputtering power is 0.5-2.5 kW, and the sputtering air pressure is (2-7) multiplied by 10 -3 mbar; the thickness of the Z layer is 50-200 nm.
8. The method according to claim 1, wherein the Cr in the Cr/Pt protective layer in step (10) has a thickness of 10 to 30nm and Pt has a thickness of 100 to 300nm; the thickness of Sn in the Au/Sn bonding layer is 1-3 mu m, and the thickness of Au is 10-200 nm; the bonding temperature is 200-500 ℃, and the bonding time is 10-20 minutes; the thickness of the Pt layer is 200-300 nm; the volume ratio of the solution used for corrosion is 1: 1-1:4 of hydrofluoric acid and nitric acid.
9. The preparation method of claim 1, wherein the spin coating in the step (11) is negative photoresist, and the spin coating time is 40-200 seconds; the photoetching time is 3-30 seconds, the developing solution adopts negative photoresist developing solution, and the developing time is 20-300 seconds; the Pd thickness of the Pd/Al/Pt n electrode layer is 10-100 nm, the Al thickness is 0.5-2 um, and the Pt thickness is 10-200 nm.
10. A vertical structure LED chip based on NiO nanodot mirrors produced by the production method according to any one of claims 1-9, characterized by comprising, in order from bottom to top, a Si (100) substrate (1), an Au/Sn bonding layer (2), a Cr/Pt protective layer (3), an array NiO nanodot/Ag/Z mirror (4), a p-GaN layer (5), an InGaN/GaN multiple quantum well layer (6), an n-GaN layer (7) and Pd/Al/Pt n electrode layers (8) separated on both sides of the upper surface of the n-GaN layer (7); the array NiO nano-dot/Ag/Z reflecting mirror (4) sequentially comprises an array NiO nano-dot layer (401), an Ag layer (402) and an anti-oxidation Z layer (403); the array NiO nano-dot layer (401) is deposited on the p-GaN layer (5).
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