JP5471485B2 - Nitride semiconductor device and pad electrode manufacturing method for nitride semiconductor device - Google Patents

Description

  The present invention relates to a technique of an electrode structure of a nitride semiconductor device, particularly a nitride semiconductor device such as a light emitting device.

  Nitride semiconductors are generally used in light emitting elements such as light emitting diodes (LEDs) and laser diodes (LD), light receiving elements such as solar cells and optical sensors, and electronic devices such as transistors and power devices. In particular, light emitting diodes using nitride semiconductors are widely used in various light sources used for backlights, lighting, traffic lights, large displays, and the like.

  In a nitride semiconductor device using a nitride semiconductor, an n-type nitride semiconductor layer and a p-type nitride semiconductor layer are basically stacked on a substrate, and the n-type and p-type nitride semiconductor layers are electrically connected to each other. In this structure, an n-side electrode and a p-side electrode to be connected are formed. When both electrodes are formed on the upper surface side, a part of the upper p-type nitride semiconductor layer is removed to form an n-side electrode in a region where the n-type nitride semiconductor layer is exposed, and on the p-type nitride semiconductor layer. A p-side electrode is formed. Here, particularly for a nitride semiconductor element having a light extraction / capture surface on the upper surface and a light receiving element, a translucent electrode is formed on the entire surface of the p-type nitride semiconductor layer on the upper surface. Furthermore, a structure is known in which a pad electrode made of a metal such as Au is formed in a part of the upper region to form a p-side electrode.

In the p-side electrode, the translucent electrode supplies the current from the pad electrode to the entire p-type nitride semiconductor layer and transmits light. Can be taken inside. As a translucent electrode, generally conductive oxide such as indium tin oxide (ITO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), etc. Things are used. On the other hand, the n-side electrode does not need to transmit light because the connection area to the n-type nitride semiconductor layer may be small, and therefore, the pad electrode directly on a part of the region on the n-type nitride semiconductor layer. Is formed.

  The n-side electrode (pad electrode) is composed of an ohmic contact layer made of Al, W, Cr, Ti or the like in good ohmic contact with the n-type nitride semiconductor, and a bonding layer of Au or the like having good adhesion to the wire. Generally, a layer structure or a three-layer structure in which a barrier layer such as Pt is further provided between the two layers (for example, Patent Documents 1 and 2). On the other hand, since the pad electrode on the p side is formed on the translucent electrode, it has good adhesion to an oxide such as ITO, and further, ohmic contact with the p-type nitride semiconductor can be achieved through this oxide. In general, it is formed by laminating a bonding layer such as Au on the lowermost layer. That is, the pad electrode needs to have different structures on the n side and the p side. However, if there is a pad electrode structure that can be connected to both the n-type nitride semiconductor and the translucent electrode on the p-type nitride semiconductor, the n-side and p-side pad electrodes can have a common structure. Therefore, the entire structure of the nitride semiconductor device can be simplified and the manufacturing cost can be reduced. Thus, pad electrode structures for both n-side and p-side have been developed.

  For example, Patent Document 3 discloses that Ti that is in good ohmic contact with an n-type nitride semiconductor is formed with a film thickness that is thinner than the surface roughness of the conductive oxide in the p-side electrode, thereby being in close contact with the conductive oxide. P-side applicable to the n-side electrode in which the non-oxide film forming portion of inferior Ti is not made continuous, and the conductive oxide and Rh have good adhesion, and Au is further laminated as a bonding layer. A pad electrode is disclosed. Further, Patent Document 4 discloses that first metals such as Rh and Pt having good adhesion with a conductive oxide are scattered in an island shape, and Al, Ti, and the like that are in ohmic contact with an n-type nitride semiconductor. Disclosed is a pad electrode including an ohmic contact layer in which a first metal and a second metal are in contact with each of a p-side conductive oxide and an n-type nitride semiconductor by laminating a second metal as a film. Has been.

Japanese Patent No. 4099989 US Pat. No. 7,335,519 JP 2006-324511 A JP 2008-41866 A

  However, these pad electrodes according to the prior art have room for improvement particularly in terms of adhesion to the conductive oxide as the p-side pad electrode.

  The present invention has been made in view of the above-mentioned problems, and ohmic contact is possible in both the translucent electrode on the p-type nitride semiconductor layer and the n-type nitride semiconductor layer, and the adhesion is improved. Another object of the present invention is to provide a nitride semiconductor device having an excellent pad electrode.

That is, the nitride semiconductor device according to the present invention is formed on an n-type nitride semiconductor layer, a p-type nitride semiconductor layer stacked on the n-type nitride semiconductor layer, and the p-type nitride semiconductor layer. A translucent electrode made of a conductive oxide, a p-side pad electrode formed in a part of the translucent electrode, and an n-side pad electrode connected to the n-type nitride semiconductor layer. It is a structure with. Then, p-side pad electrode or the n-side pad electrode and the p-side pad electrodes, in turn from the side in contact with the respective n-type nitride semiconductor layer and the translucent electrode, Cr layer of less than a thickness of 1 nm 9 nm,, characterized in that it comprises by stacking Pt layer having a thickness of more than the thickness of the pre-Symbol Cr layer.

  As described above, Cr having excellent ohmic contact with the n-type nitride semiconductor is extremely thin and the thickness is limited to the first layer (lowermost layer), and p-type nitridation via the conductive oxide is further formed thereon. By laminating Pt capable of ohmic contact with a physical semiconductor, ohmic contact can be obtained even if the first layer is Cr which does not make ohmic contact with a p-type nitride semiconductor. That is, a low-resistance pad electrode can be obtained regardless of whether it is applied to either the n-side pad electrode or the p-side pad electrode. In particular, by setting the Pt layer to be equal to or greater than the thickness of the Cr layer, the Cr layer is easily affected by the Pt layer, and the above effect can be obtained.

  Further, at least one of the n-side pad electrode and the p-side pad electrode having such a structure is preferably the following structure. That is, it is preferable that a part of the Pt layer on the Cr layer is diffused and a layer containing Cr and Pt is formed between the Cr layer and the Pt layer. In this way, since the Cr layer, which is a thin film, is provided with strong adhesion to the conductive oxide by being in close contact with the Pt layer so that a Cr—Pt alloy layer is formed at the interface, the p side is particularly preferred. It can be excellent as a pad electrode.

  Preferably, a Ru layer or an Ir layer is laminated on the Pt layer, and an Au layer is further laminated thereon to form the outermost surface of at least one of the n-side pad electrode and the p-side pad electrode. More preferably, the Ru layer or Ir layer has a thickness of 50 nm or more.

  As described above, when an Au layer with good bonding property is provided on the outermost surface, by disposing the Ru layer or Ir layer between the Pt layer and the Au layer, diffusion from the Pt layer is suppressed and bonding property is improved. It can be prevented from decreasing. In particular, when the Ru layer or Ir layer has a thickness of 50 nm or more, the above effect can be obtained.

  In the nitride semiconductor device according to the present invention, the translucent electrode of the p-side electrode is preferably indium-tin oxide (ITO). Among conductive oxides, ITO has a high light transmittance and is a material having a relatively high conductivity, so that the light emission efficiency of the nitride semiconductor element can be increased.

  In the nitride semiconductor device according to the present invention, the n-side pad electrode is stacked on the n-type nitride semiconductor layer, and is formed in a region different from the p-type nitride semiconductor layer in a plane. The side pad electrode and the p-side pad electrode can have the same stacked structure. That is, in a nitride semiconductor device, an n-side pad electrode and a p-side pad electrode are stacked on the same side, and the n-side pad electrode and the p-side pad electrode are simultaneously formed by forming the same stacked structure. It becomes possible.

  A method for manufacturing a pad electrode of a nitride semiconductor device according to the present invention is a method for manufacturing an n-side pad electrode and a p-side pad electrode of the nitride semiconductor device, wherein the pad electrode is formed on the n-type nitride semiconductor layer and on the transparent substrate. A step of laminating a Cr layer and a Pt layer in order on each of the photoelectrodes, a Ru layer or an Ir layer on the Pt layer, and further laminating an Au layer thereon, and the laminated metal layer And a step of heating. By performing such a method, the p-side and n-side pad electrodes can be simultaneously formed, and Pt can be diffused into the Cr layer by heating the stacked metal layers.

  According to the nitride semiconductor device of the present invention, it is possible to provide a pad electrode with good ohmic contact and adhesiveness for any of the p-type and n-type nitride semiconductor layers, and the p-side, The structure of the nitride semiconductor device can be simplified by using the n-side pad electrode as a common structure. And according to the manufacturing method of the pad electrode of the nitride semiconductor device concerning the present invention, the above-mentioned pad electrode can be simultaneously formed in each of the p side and the n side, and productivity is good.

It is a schematic diagram explaining the structure of the nitride semiconductor element which concerns on embodiment of this invention, (a) is a top view, (b) is sectional drawing. FIG. 2 is an enlarged cross-sectional view schematically showing a pad electrode structure in the nitride semiconductor device shown in FIG. 1. 3 is a flowchart illustrating a method for manufacturing a nitride semiconductor device according to an embodiment of the present invention. It is a graph explaining the thickness dependence of the adhesiveness of a pad electrode and contact property in the Example which concerns on this invention, and Cr layer, (a) shows a peeling rate, (b) shows contact resistance and a forward voltage. It is a graph which shows the thickness direction distribution of the detection intensity by the GDS analysis of the pad electrode in the Example which concerns on this invention, (a), (b), (c) is the thickness of Cr layer 1nm, 2nm, 3nm, respectively. It is. It is a graph explaining the heat processing dependence of the adhesiveness of a pad electrode and contact property in the Example which concerns on this invention, (a) shows a peeling rate, (b) shows contact resistance. It is a graph which shows the thickness direction distribution of the detected intensity by the GDS analysis of the pad electrode in the Example which concerns on this invention, (a) is before heat processing, (b) is after heat processing. It is a figure explaining formation of the Cr-Pt alloy layer of Cr layer-Pt layer of the pad electrode in the Example which concerns on this invention, (a) is the translucent electrode (ITO) of a nitride semiconductor element, and p side pad The STEM image photograph of the cross section of the interface vicinity of an electrode, (b) is a graph which shows the composition ratio of Pt, Cr, In according to depth region. It is a graph which shows the thickness direction distribution of the detection intensity by the GDS analysis of the pad electrode in the Example which concerns on this invention, (a) is an Example whose barrier layer is an Ir layer, (b) is implementation of the Ru layer as a barrier layer. Example (c) is a comparative example without a barrier layer. It is a graph which compares the wire shear strength of the pad electrode in the Example which concerns on this invention.

  Hereinafter, a nitride semiconductor device according to the present invention and a method for manufacturing a pad electrode of the nitride semiconductor device will be described.

[Nitride semiconductor devices]
The structure of the nitride semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. A nitride semiconductor device 10 according to an embodiment of the present invention is a light emitting device. As shown in FIG. 1B, an n-type nitride semiconductor layer 2, an active layer 3, and a p-type nitride are formed on a substrate 1. A physical semiconductor layer 4 is stacked. Further, the nitride semiconductor element 10 includes an n-side electrode (n-side pad electrode) 7 n electrically connected to the n-type nitride semiconductor layer 2 and a p-side electrode 5 electrically connected to the p-type nitride semiconductor layer 4. Are provided on the upper surface side, and an insulating protective film 9 is provided on the surface. The n-side electrode 7n is a pad electrode, and is formed directly on the surface of the n-type nitride semiconductor layer 2 exposed by removing a part of the p-type nitride semiconductor layer 4 and the active layer 3. On the other hand, the p-side electrode 5 includes a translucent electrode 6 formed on almost the entire surface of the p-type nitride semiconductor layer 4 and a pad electrode (in a partial region on the translucent electrode 6). p-side pad electrode) 7p. Protective film 9 covers the entire surface of nitride semiconductor element 10 except for the upper surfaces of n-side electrode 7n and p-side pad electrode 7p. Note that “upper” in this specification refers to the side provided with the nitride semiconductor layer with respect to the substrate, and is the upward direction in FIG.

(substrate)
The substrate 1 may be any substrate material capable of epitaxially growing a nitride semiconductor, and the size and thickness are not particularly limited. As such a substrate material, an insulating substrate such as sapphire or spinel (MgA1 ₂ O ₄ ) whose main surface is any one of C-plane, R-plane, and A-plane, silicon carbide (SiC), silicon, ZnS ZnO, Si, GaAs, diamond, and oxide substrates such as lithium niobate and neodymium gallate that are lattice-bonded to nitride semiconductors. Since the nitride semiconductor device 10 according to the present embodiment includes the n-side electrode 7n and the p-side electrode 5 on the same surface side (upper surface side), an insulating substrate can be provided as the substrate 1, but the conductive substrate is used. It may be used as the substrate 1.

(N-type nitride semiconductor layer, active layer, p-type nitride semiconductor layer)
The n-type nitride semiconductor layer 2, the active layer 3, and the p-type nitride semiconductor layer 4 are not particularly limited. For example, In _x Al _Y Ga _1-XY N (0 ≦ X, 0 ≦ Y A gallium nitride compound semiconductor such as X + Y <1) is preferably used. Each of n-type nitride semiconductor layer 2, active layer 3, and p-type nitride semiconductor layer 4 (collectively referred to as nitride semiconductor layers 2, 3, and 4) may each have a single-layer structure. A laminated structure of different layers, a superlattice structure, or the like may be used. In particular, the active layer 3 that is a light emitting layer preferably has a single quantum well or multiple quantum well structure in which thin films that produce quantum effects are stacked, and the well layer is preferably a nitride semiconductor containing In. Note that the n-type nitride semiconductor layer 2 may be formed on the substrate 1 through an underlayer (not shown) such as a buffer layer for arbitrarily relaxing the lattice constant mismatch with the substrate 1. .

  Usually, such a nitride semiconductor layer may be configured as a homostructure, a heterostructure, or a double heterostructure each having a MIS junction, a PIN junction, or a PN junction, and the film thickness is particularly It is not limited and can be configured with various film thicknesses. As a laminated structure of the nitride semiconductor layer, for example, a buffer layer made of AlGaN, an undoped GaN layer, an n-side contact layer made of Si-doped n-type GaN, a superlattice layer in which GaN layers and InGaN layers are alternately laminated, An active layer having a multiple quantum well structure in which GaN layers and InGaN layers are alternately stacked, a superlattice layer in which Mg-doped AlGaN layers and Mg-doped InGaN layers are alternately stacked, a p-side contact layer made of Mg-doped GaN, Etc.

  In the present invention, the method for forming the nitride semiconductor layer is not particularly limited, but MOVPE (metal organic chemical vapor deposition), MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE. A known method such as (molecular beam epitaxy) can be suitably used as a method for growing a nitride semiconductor. In particular, MOCVD is preferable because it can be grown with good crystallinity. The nitride semiconductor layers 2, 3, and 4 are preferably grown by appropriately selecting various nitride semiconductor growth methods according to the purpose of use.

(N-side electrode, p-side electrode)
The n-side electrode 7n is electrically connected to the n-type nitride semiconductor layer 2, and the p-side electrode 5 is electrically connected to the p-type nitride semiconductor layer 4 to supply current from the outside. Here, a suitable gallium nitride compound semiconductor among nitride semiconductors is unlikely to be p-type, that is, the p-type nitride semiconductor layer 4 tends to have a relatively high resistance. Therefore, when the electrodes are connected only in a part of the region on the p-type nitride semiconductor layer 4, the current supplied to the nitride semiconductor element 10 hardly spreads in the p-type nitride semiconductor layer 4, and light emission is in-plane. It becomes uneven. Therefore, the p-side electrode 5 needs to be connected on a larger area on the p-type nitride semiconductor layer 4 so that the current flows uniformly throughout the surface of the p-type nitride semiconductor layer 4. However, since the upper surface is the light extraction surface of the nitride semiconductor element 10, the p-side electrode 5 is directly connected to the p-type nitride semiconductor layer 4 so that the light extraction efficiency is not reduced by the p-side electrode 5. A translucent electrode 6 is provided on the entire surface or a region having an area close to it (substantially the entire surface). The p-side electrode 5 is further provided with a pad electrode (p-side pad electrode) 7p having Au or the like having a good bonding property on the surface for connection to an external circuit by wire bonding or the like on the translucent electrode 6. . The p-side pad electrode 7p has a planar view shape and area necessary for bonding so as not to block much light, and is smaller than the planar view shape of the translucent electrode 6, so that it is contained, that is, translucent. It is formed in a partial region on the electrode 6.

  On the other hand, in the low resistance n-type nitride semiconductor layer 2, since the n-side electrode 7n may have a small connection area, the n-side electrode 7n can be composed of only a pad electrode (n-side pad electrode) that does not transmit light. It is formed directly on the type nitride semiconductor layer 2. In addition, since the nitride semiconductor device 10 according to the present embodiment includes the n-side pad electrode 7n on the upper surface side, the active layer in the region for connecting the n-side pad electrode 7n on the n-type nitride semiconductor layer 2 is used. 3 and the p-type nitride semiconductor layer 4 are removed (see FIG. 1B), that is, this region does not emit light. Therefore, the n-side electrode (n-side pad electrode) 7n is necessary for bonding in the same manner as the p-side pad electrode 7p so as not to greatly reduce the amount of light emission, and is electrically connected to the n-type nitride semiconductor layer 2. It is formed in a planar view shape and area required for the above. The respective positions of the n-side pad electrode 7n and the p-side pad electrode 7p in the plan view of the nitride semiconductor element 10 are not particularly limited, but the amount of light blocked by the pad electrodes 7n and 7p themselves or wires connected from an external circuit is more increased. What is necessary is just to design based on what can be suppressed and workability | operativity of bonding.

(Translucent electrode)
The translucent electrode 6 in the p-side electrode 5 is made of a conductive oxide. Although a metal thin film can be used as the light-transmitting electrode, since the conductive oxide is more light-transmitting than the metal thin film, the nitride semiconductor element 10 can be a light-emitting element with high light emission efficiency. Examples of the conductive oxide include oxides containing at least one selected from the group consisting of Zn, In, Sn, and Mg, specifically ZnO, In ₂ O ₃ , SnO ₂ , and ITO. In particular, ITO can be suitably used because it has a high light transmittance in visible light (visible region) and is a material having a relatively high electrical conductivity. As described above, in order to uniformly supply current to the entire region of the p-type nitride semiconductor layer 4 having a relatively high resistance, the translucent electrode 6 has a larger area on the p-type nitride semiconductor layer 4, that is, It is preferable to form almost the entire surface. The film thickness of the translucent electrode 6 is not particularly limited, but is preferably 5000 nm or less, and more preferably about 100 to 1000 nm so that the sheet resistance is not excessive.

  The translucent electrode 6 made of a conductive oxide can be formed by a known method. For example, sputtering method, reactive sputtering method, vacuum deposition method, ion beam assisted deposition method, ion plating method, laser ablation method, CVD method, spray method, spin coating method, dipping method, or a combination of these methods and heat treatment Various methods can be used. In addition, as described above, the translucent electrode 6 is preferably formed almost entirely on the p-type nitride semiconductor layer 4 in terms of conductivity, but the shape in plan view is not particularly limited, and photolithography The film can be formed into a desired shape by etching or the like. The translucent electrode 6 may have a shape corresponding to the planar shape of the p-type nitride semiconductor layer 4 such as an integral rectangle. For example, the translucent electrode 6 is patterned in a lattice shape, a mesh shape, a dot shape, a stripe shape, a mesh shape, or the like. By forming the light, the light extraction efficiency may be improved. The stripe shape or the like is formed in a branch shape branched from a single body into a plurality of shapes so that the conductive oxide film is not completely separated by the pattern.

(Pad electrode)
In the nitride semiconductor device 10 according to the present embodiment, the n-side pad electrode 7n and the p-side pad electrode 7p have the same stacked structure, and are collectively referred to as a pad electrode 7 as appropriate. As shown in FIG. 2, the pad electrode 7 has a configuration in which a bonding layer (Au layer) 73 for connecting a wire from the outside is provided on the uppermost layer (uppermost surface) as in a general case. In the present embodiment, the pad electrode 7 includes an ohmic contact layer (Cr / Pt layer) 71 in which a Cr layer 71a and a Pt layer 71b are sequentially laminated on the lowermost layer, and further, that is, a bonding layer (Au layer) 73. And a barrier layer (Ru layer or Ir layer) 72. These metal layers 71a, 71b, 72 and 73 can be formed by a known method such as a vapor deposition method or a sputtering method, and are preferably formed continuously and laminated. Further, the planar view shape of the pad electrode 7 (7n, 7p) is not particularly limited, and the pad electrode 7 (7n, 7p) is formed into a desired shape (for example, see FIG. 1A) by a lift-off method, etching using photolithography, or the like. Can do.

  The ohmic contact layer 71 is composed of two layers (referred to as a Cr / Pt layer as appropriate) of a Cr layer 71a and a Pt layer 71b. The Cr layer 71a is a layer that contacts the n-type nitride semiconductor layer 2 in the n-side pad electrode 7n and the translucent electrode 6 in the p-side pad electrode 7p. Cr has good adhesion to the n-type nitride semiconductor layer 2 and the translucent electrode 6 that is a conductive oxide, and forms a film capable of ohmic contact with the n-type nitride semiconductor layer 2. However, Cr does not have ohmic contact with the p-type nitride semiconductor layer 4 through the conductive oxide. Specifically, Cr loses ohmic contact with the p-type nitride semiconductor layer 4 when heated. Since the nitride semiconductor element 10 is generally subjected to a heat treatment at about 300 ° C. in a process of being mounted on a package as a light emitting device, for example, it is necessary that the characteristics are not deteriorated by such heat. However, the Cr layer 71a is improved in ohmic contact with the p-type nitride semiconductor layer 4 by the effect of the Pt layer 71b laminated thereon, in particular, Pt is diffused by heat as described later. To do. That is, in the pad electrode 7, the two layers of the Cr layer 71a and the Pt layer 71b laminated thereon constitute an ohmic contact layer 71 common to the n side and the p side.

  The Cr layer 71a has a thickness of 1 nm or more and preferably 1.5 nm or more in order to maintain ohmic contact with the n-type nitride semiconductor layer 2. Further, in order to prevent the diffusion of Pt from the Pt layer 71b from increasing toward the upper bonding layer 73, the thickness of the Cr layer 71a is preferably 2 nm or more. On the other hand, when the Cr layer 71a is thick, it becomes difficult to be affected by the Pt layer 71b up to the contact surface with the translucent electrode 6, and the ohmic contact with the p-type nitride semiconductor layer 4 is lowered. Further, the Cr layer 71a is in close contact with the Pt layer 71b to form a Cr / Pt layer (ohmic contact layer) 71, thereby improving the adhesion to the translucent electrode 6 as will be described later. However, when the thickness is increased, the integrity with the Pt layer 71b becomes insufficient, and the adhesion to the translucent electrode 6 decreases. Accordingly, the Cr layer 71a has a thickness of less than 9 nm, preferably 6 nm or less, and more preferably 4.5 nm or less. Considering thickness variation in manufacturing, it is particularly preferable that the Cr layer 71a has a thickness target of 3.0 nm.

  The Pt layer 71b is preferably formed so as not to be thinner than the Cr layer 71a in order to sufficiently diffuse Pt into the Cr layer 71a. That is, the thickness of the Pt layer 71b is preferably 1 or more times that of the Cr layer 71a, more preferably 5 times or more, and specifically 10 nm or more is preferable because it is easy to control in manufacturing. On the other hand, even if the Pt layer 71b is thicker than 100 nm, the further improvement of the effect is saturated and the productivity is lowered. In addition, Pt diffuses also to the bonding layer 73 side and the bonding property may be lowered. Therefore, the thickness is preferably 100 nm or less, and more preferably 50 nm or less.

  As Pt diffuses from the Pt layer 71b to the Cr layer 71a, a Cr—Pt alloy layer (not shown in FIG. 2) is provided near the interface between the Cr layer 71a and the Pt layer 71b (between the Cr layer 71a and the Pt layer 71b). Preferably it is formed. Inherently, Cr alone has good adhesion, but in the present invention, the Cr layer 71a is extremely thin, so that the adhesion is weak and is insufficient particularly for the conductive oxide film. Therefore, the Cr layer 71a and the Pt layer 71b having good adhesion to the conductive oxide film are in close contact with each other so that a Cr—Pt alloy layer is formed at the interface to form an integral Cr / Pt layer 71. Thereby, the adhesiveness to the translucent electrode 6 improves. Moreover, as Pt sufficiently diffuses in the Cr layer 71a, ohmic contact with the p-type nitride semiconductor layer 4 is improved as described above. In order to diffuse Pt from the Pt layer 71b to the Cr layer 71a, the pad electrode 7 is subjected to heat treatment as will be described later in the manufacturing method after the Cr layer 71a, the Pt layer 71b, and other metal layers are formed. Is preferably applied.

  The barrier layer 72 is laminated between the Pt layer 71 b and the bonding layer (Au layer) 73. In the present embodiment, since the bonding layer 73 is made of Au, when directly laminated on the Pt layer 71b, Pt is diffused and the bonding property of Au is lowered. That is, the barrier layer 72 is provided to suppress the diffusion of Pt into the bonding layer 73. In particular, in the heat treatment for diffusing Pt from the Pt layer 71b to the Cr layer 71a, Pt diffuses into the bonding layer 73. This is suppressed, and the bonding property is prevented from deteriorating. In order to obtain such an effect, Ru and Ir that are difficult to thermally diffuse into Au of the bonding layer 73 are applied to the barrier layer 72. In this embodiment, a Ru layer is applied to the barrier layer 72 (see FIG. 2). In addition, although Mo is also mentioned as a metal which is hard to thermally diffuse in Au, Mo may be dissolved by hydroozone.

  The barrier layer 72 preferably has a thickness of 50 nm or more, although it depends on the thicknesses of the Pt layer 71b and the bonding layer 73 and the heat treatment conditions described later. With this thickness, when heat treatment is performed to diffuse Pt to the Cr layer 71a side, even if Pt diffuses to the barrier layer 72 side, it reaches the bonding layer 73 and diffuses further. Can be suppressed. A more preferable thickness is 60 nm or more. On the other hand, even if the barrier layer 72 is thicker than 90 nm, further improvement in the effect is saturated and the productivity is lowered. Therefore, the thickness is preferably 90 nm or less.

  The bonding layer 73 is provided to connect wires and bumps from the outside and constitutes the surface (uppermost surface) of the pad electrode 7. The bonding layer 73 is excellent in adhesion to a wire or the like, that is, bonding properties, and can be applied to metals such as Al (including Al alloy), Cu, Au, etc., which are generally applied, but particularly to corrosion resistance and the like. It is preferable to apply excellent Au. The bonding layer 73 preferably has a thickness of 100 nm or more and more preferably 200 nm or more in order to maintain bonding properties. On the other hand, in terms of productivity, the thickness of the bonding layer 73 is preferably 1000 nm or less, more preferably 800 nm or less, and particularly preferably 500 nm or less.

(Protective film)
The protective film 9 covers the exposed surfaces (upper surface and side walls) of the nitride semiconductor layers 2, 3, 4 in the nitride semiconductor element 10, the surface of the translucent electrode 6, and the like to protect the nitride semiconductor element 10. A film and an antistatic film are used. Specifically, the region excluding the peripheral portion on the upper surface of the pad electrodes 7n and 7p is used as a bonding region (pad portion), and the protective film 9 is formed on the entire surface excluding the pad portion region. The protective film 9 is made of an oxide such as Si, Ti, Ta, which is a light-transmitting insulating film, and can be formed by a known method such as a vapor deposition method or a sputtering method, and its film thickness is particularly limited. Although it is not, it is preferable to set it as 100-1000 nm.

  Here, Au in the bonding layer 73 constituting the uppermost surfaces of the pad electrodes 7n and 7p is inferior in adhesion to the protective film 9 made of oxide, and thus the protective film 9 may be peeled off from the end of the pad portion. . In order to prevent this, it is preferable to form a film of Ni or the like as the adhesion layer 82 on the peripheral edge portion of the upper surface of the bonding layer 73 (a region immediately below the protective film 9). Further, in the case where the adhesion layer 82 is formed of Ni, if Ni diffuses from the adhesion layer 82 to Au of the bonding layer 73, the bonding property is deteriorated. Therefore, in order to prevent this, the barrier layer 81 is provided under the adhesion layer 82. It is preferable to form. The barrier layer 81 can be formed of W, Ru, Ir, or the like, but it is particularly preferable to apply Ru or Ir as in the case of the barrier layer 72 of the pad electrode 7. The thicknesses of the barrier layer 81 and the adhesion layer 82 are not particularly limited. However, in order to work appropriately, the barrier layer 81 is preferably 20 to 50 nm and the adhesion layer 82 is preferably 1 to 20 nm. In addition, the two layers (for example, Ru / Ni layer) of the barrier layer 81 and the adhesion layer 82 are appropriately referred to as the underlayer 8. Similarly to the metal film (Cr / Pt layer 71 to Au layer 73) constituting the pad electrodes 7n and 7p, the base layer 8 can also be formed by a known method such as a vapor deposition method or a sputtering method. It is preferable to form a film continuously from the (Au layer) 73, that is, continuously from the Cr layer 71a.

  The nitride semiconductor device according to the embodiment of the present invention having the above configuration has ohmic contact and adhesion to both the n-type nitride semiconductor layer and the p-type nitride semiconductor layer on which the translucent electrode is formed. A pad electrode with good characteristics is provided. For this reason, the nitride semiconductor device according to the embodiment of the present invention is a light-emitting device that has a low forward voltage Vf, a high light-emitting efficiency, and has few contact failures due to deterioration over time, and has excellent reliability.

[Method of manufacturing pad electrode of nitride semiconductor element]
An example of the method for manufacturing a pad electrode of a nitride semiconductor device according to the present invention will be described with reference to FIG. 3, including the manufacture of the nitride semiconductor device according to the embodiment.

(Formation of nitride semiconductor layer: S10)
Using the sapphire substrate as the substrate 1, each nitride semiconductor constituting the n-type nitride semiconductor layer 2, the active layer 3, and the p-type nitride semiconductor layer 4 is grown on the substrate 1 using a MOVPE reactor. (S11 in FIG. 3, the same applies hereinafter). Specifically, the first buffer layer, the second buffer layer, the n-side contact layer, the third buffer layer, and the n-side multilayer film constituting the n-type nitride semiconductor layer 2 on the substrate 1. After the active layer 3 is grown on the n-side multilayer film layer, the p-side multilayer film layer and the p-side contact layer that form the p-type nitride semiconductor layer 4 are sequentially formed. Grow. The substrate 1 on which each nitride semiconductor layer is grown (hereinafter referred to as a wafer) is annealed at about 600 to 700 ° C. in a nitrogen atmosphere in the processing chamber of the apparatus to reduce the resistance of the p-type nitride semiconductor layer 4. (S12).

(Formation of contact region for n-side electrode: S20)
A part of n-type nitride semiconductor layer 2 is exposed as a contact region for connecting n-side electrode (n-side pad electrode) 7n. A mask having a predetermined shape is formed on the annealed wafer with a photoresist (S21), and p-type nitride semiconductor layer 4 and active layer 3, and n-type nitride are formed by reactive ion etching (RIE). The n-side multilayer film layer and the third buffer layer of the semiconductor layer 2 are removed, and the n-side contact layer is exposed on the surface (S22). After the etching, the resist is removed (S23). The peripheral portion (scribe region) of the nitride semiconductor element 10 (chip) may be etched simultaneously with the contact region (see FIG. 1B).

(Formation of translucent electrode: S30)
An ITO film is formed as a translucent electrode 6 on the entire surface of the wafer by a sputtering apparatus (S31). Then, a mask having a shape corresponding to the plan view shape of the p-type nitride semiconductor layer 4 below (see FIG. 1A) is formed on the ITO film with a photoresist (S32) and etched (S32). S33), the translucent electrode 6 is formed on the p-type nitride semiconductor layer 4. After the etching, the resist is removed (S34). Next, annealing is performed at about 500 ° C. in a nitrogen atmosphere, the ohmic contact between the translucent electrode 6 (ITO film) and the p-type nitride semiconductor layer 4, and the exposed n-type nitride of the contact region. The ohmic contact property of the semiconductor layer 2 to the n-side pad electrode 7n is improved (S35).

(Formation of pad electrode: S40)
A mask is formed on the exposed n-type nitride semiconductor layer 2 and a predetermined region in each of the translucent electrodes 6 with a photoresist (S41), and a pad is formed on the mask using a sputtering apparatus. A total of six metal films of Cr, Pt, Ru, Au constituting the electrodes 7n, 7p and Ru, Ni constituting the underlayer 8 are successively formed in a predetermined thickness (S42). Thereafter, when the resist is removed together with the metal film thereon (S43), an n-side pad electrode 7n and a p-side pad electrode 7p are formed in the predetermined region (lift-off method), and the same planar view shape is formed thereon. Thus, two layers of Ru and Ni are laminated.

(Heat treatment: S44)
In a nitrogen atmosphere, the wafer is heat-treated (annealed) to diffuse Pt from the Pt layer 71b to the Cr layer 71a in the pad electrodes 7n and 7p. Although depending on the respective thicknesses of the Cr layer 71a and the Pt layer 71b, the temperature of the heat treatment is preferably 280 ° C. or higher in order to diffuse Pt. On the other hand, if the temperature is too high, the nitride semiconductor layers 2, 3, and 4 are deteriorated by heat, and the ohmic contact properties of the n-type nitride semiconductor layer 2 and the p-type nitride semiconductor layer 4 are reduced. Since the light emission intensity of the nitride semiconductor element 10 may be reduced, the heat treatment temperature is preferably 500 ° C. or lower. Moreover, although processing time is set according to temperature and thickness, such as Cr layer 71a, about 10 to 20 minutes are preferable.

(Formation of protective film: S50)
A SiO ₂ film is formed as a protective film 9 on the entire surface of the wafer by a sputtering apparatus (S51). As a pad portion, a mask having a predetermined area on the Ru, Ni film on the pad electrodes 7n, 7p is formed with a photoresist (S52), and the SiO ₂ film is etched (S53), and then the resist is removed (S53). S54). Ni and Ru are etched using the remaining SiO ₂ film (protective film 9) as a mask to expose the bonding layer (Au layer) 73 in the pad portion (S55).

  The wafer is separated by scribing, dicing, or the like to form one nitride semiconductor element 10 (chip). Further, before separation into chips, the substrate 1 may be ground (back grind) from the back surface of the wafer and thinned to a desired thickness.

  Since the nitride semiconductor device pad electrode manufacturing method according to the present invention according to the above-described steps can be formed simultaneously on the p-side and the n-side of the nitride semiconductor device according to the above-described embodiment. , Improve productivity.

  The pad electrode of the nitride semiconductor device according to the present invention is applied only to one of the p-side and n-side pad electrodes, and at this time, the other pad electrode has a conventionally known structure (for example, n-side: Cr / Pt). / Au, p side: Rh / W / Au). Further, the pad electrode of the nitride semiconductor device according to the present invention is not limited to the nitride semiconductor device according to the embodiment (see FIG. 1), and for example, an n-side electrode is provided on the back surface (lower surface) side of the conductive substrate. It can also be applied to a nitride semiconductor device (not shown).

  As described above, the nitride semiconductor device and the pad electrode manufacturing method of the nitride semiconductor device according to the present invention have been described in the mode for carrying out the present invention. However, the present invention is not limited to the above embodiment. Needless to say, various changes and modifications based on these descriptions are also included in the spirit of the present invention.

  An example in which a nitride semiconductor device is fabricated and the effect of the present invention is confirmed with respect to the structure of the pad electrode will be specifically described in comparison with a comparative example that does not satisfy the requirements of the present invention. In addition, this invention is not limited to this Example.

[Production of nitride semiconductor devices]
A nitride semiconductor device 10 having the structure shown in FIG. 1 was produced. The shape in plan view (see FIG. 1A) is that the entire nitride semiconductor device 10 is X (horizontal) 420 μm × Y (vertical) 240 μm, of which the region of the p-type nitride semiconductor layer 4 (the contact region for the n-side electrode) The approximate shape included) was X: 370 μm × Y: 190 μm, and the pad electrodes 7 n and 7 p on the n side and the p side had a diameter of 90 μm (pad part diameter 80 μm). The center positions of the pad electrodes 7n and 7p are aligned with the center of the full width in the Y direction. In the X direction, the n-side pad electrode 7n is 50 μm from the end in the region of the p-type nitride semiconductor layer 4, and the p-side pad electrode 7p is the same. The distance from the end (opposite side) was 60 μm, and the distance between the centers of both pad electrodes 7 n and 7 p was 260 μm.

(Formation of nitride semiconductor layer)
As shown in Table 1, on a substrate 1 made of 3 inch φ sapphire (C-plane), the temperature and gas type are switched as shown in Table 1, and the buffer layer, the n-type nitride semiconductor layer 2, the active layer 3. Each nitride semiconductor composing the p-type nitride semiconductor layer 4 was grown sequentially. A substrate 1 (hereinafter referred to as a wafer) on which each layer of nitride semiconductor was grown was annealed at 600 ° C. in a nitrogen atmosphere in a processing chamber of a MOVPE reactor.

(Formation of contact region for n-side electrode)
The wafer is taken out of the processing chamber, a resist mask having a predetermined shape is formed on the p-type nitride semiconductor layer 4, and the p-type nitride is formed with an RIE (reactive ion etching) apparatus as shown in FIG. Etching was performed until the n-side contact layer of the semiconductor layer 4 and the active layer 3 and the n-type nitride semiconductor layer 2 were exposed, and the resist was removed.

(Formation of translucent electrode)
The wafer was immersed in buffered hydrofluoric acid (BHF, hydrofluoric acid / ammonium fluoride aqueous solution) at room temperature, and then a 170 nm-thick ITO film was formed using a sputtering apparatus. Specifically, an oxide target made of a sintered body of In ₂ O ₃ and SnO ₂ was used, and discharge was performed in an Ar atmosphere to form an ITO film on the wafer. Then, a resist mask was formed and etched so that the ITO film remained on almost the entire surface of the p-type nitride semiconductor layer 4, and the resist was removed. And in order to improve the ohmic contact property of ITO film | membrane, annealing at 500 degreeC was performed in nitrogen atmosphere, and it was set as the translucent electrode 6. FIG.

(Pad electrode formation)
Resist masks are formed on the n-type nitride semiconductor layer 2 (n-side contact layer) in the n-side electrode contact region and on the translucent electrode 6 to form predetermined resist masks. On top, Cr, Pt, Ru, Au for the pad electrode 7 (7n, 7p), and Ru, Ni as the underlayer 8 of the protective film 9 were successively formed. Then, the resist was removed (lift-off), and a six-layer film having a plan view shape (see FIG. 1A) of the n-side and p-side pad electrodes 7n and 7p was formed. The thickness of each layer of the pad electrode 7 is as shown in Table 2. Sample No. No. 1 has no Cr layer (thickness 0 nm). 3 was formed by changing the thickness of the Cr layer to other than 3 nm shown in Table 2. On the other hand, the Ru layer of the underlayer 8 was 30 nm thick and the Ni layer was 6 nm thick. However, sample no. 7 has a configuration in which the underlayer 8 is not provided.

(Formation of pad electrode of reference example)
As a reference example of a conventional pad electrode structure common to the n-side and p-side, a sample No. 1 of pad electrode having a laminated structure of Ti / Rh / W / Au in which a W layer is provided as a barrier layer on the pad electrode of Patent Document 3. 12 was prepared, and the underlayer 8 was provided with a W layer in place of the Ru layer (see Table 2).

(Pad electrode heat treatment)
Thereafter, the wafer was annealed at a temperature and time shown in Table 2 in a nitrogen atmosphere in an annealing furnace. Sample No. 3 (Cr layer thickness 3 nm), No. 3 For 4, 5 and 12, the annealing temperature was changed in addition to the temperatures shown in Table 2, and specifications were also made without annealing. However, sample no. 3, the specification in which the thickness of the Cr layer was changed was annealed at 400 ° C. for 10 minutes as shown in Table 2, and the specification in which the annealing was not performed was set as Sample No. 2 is shown in Table 2. In addition, annealing was performed in units of 10 minutes, and when performed for 20 minutes, it was performed twice. An electric furnace was used for annealing at 280 ° C.

(Formation of protective film)
A 200 nm thick SiO ₂ film was formed as a protective film 9 on the entire surface of the wafer. A resist mask was formed with a region to be a pad portion on the pad electrodes 7n and 7p, the SiO ₂ film was etched, and the resist was removed. Further, Ni and Ru of the underlayer 8 were etched to expose the Au layer 73 of the pad electrodes 7n and 7p, whereby the nitride semiconductor device 10 was obtained. In addition, the substrate was ground from the back surface of the wafer by back grinding to a total thickness of 85 μm.

[Evaluation of Cr layer thickness dependence]
Sample No. 1 and 3 (annealing temperature 400 ° C.), and sample no. 6, the thickness dependence of the Cr layer 71a of the pad electrode was evaluated as follows.

(Adhesion evaluation method)
Wire bonding acceleration test to evaluate the adhesion between the ohmic contact layer 71 (71a) of the pad electrode and each of the n-type nitride semiconductor layer 2 (n-type GaN contact layer) and the translucent electrode 6 (ITO film) The peeling rate was measured at Specifically, using a wire bonding apparatus (FB-150DGII, manufactured by Kaijo Corporation), a 30 μm Au wire was bonded to the pad electrode, and at that time, the pad electrode was peeled off from the base (n-type GaN contact layer, ITO film) The number of samples was measured.

(Ohmic contact evaluation method)
In order to evaluate the ohmic contact of the ohmic contact layer 71 of the pad electrode to the n-type nitride semiconductor layer 2 (n-type GaN contact layer) and the translucent electrode 6 (ITO film), contact measurement is performed on the wafer. The sample (chip) was mounted on a φ5 type bullet-type lamp, and the forward voltage Vf was measured by integrating sphere measurement.

(Metal composition distribution of pad electrode)
The elemental composition analysis from the surface of the pad electrode (including the protective film and the underlayer) to the lowest layer was performed with a glow discharge emission spectroscopy (GDS) apparatus. The detected intensity of each obtained element was evaluated by a graph of distribution in the thickness direction.

  Sample No. For FIGS. 1 and 3, the peel rate is shown in FIG. 4A, the contact resistance and the forward voltage Vf are shown in FIG. Further, Table 2 shows the peeling rate and contact resistance when the Cr layer has a thickness of 0 nm and 3 nm (sample Nos. 1 and 3). In addition, graphs of thickness distribution in the detected intensity for Cr layer thicknesses of 1 nm, 2 nm, and 3 nm (sample No. 6) are shown in FIGS. 5 (a), 5 (b), and 5 (c), respectively.

〔Evaluation results〕
(Cr layer thickness dependence)
As shown in FIG. 4 (a), Cr has good adhesion to the n-type nitride semiconductor layer even when the layer thickness is very thin of 0.5 nm. Adhesiveness to the sample is also obtained, and both the n-side and p-side have sample No. 12 (see Table 2). However, when the thickness was 9 nm, the adhesion to the ITO film was lowered.

  As shown in FIG. 4B, Cr has good ohmic contact with the n-type nitride semiconductor layer, has low n-side contact resistance, and improved particularly when the thickness is about 2 nm or more. On the other hand, on the p side, by laminating Pt on the Cr layer, the Cr layer can obtain ohmic contact with the p-type nitride semiconductor layer via the ITO film, and the contact resistance is lowered. The voltage Vf was also lowered. Further, when the Cr layer has a thickness of 9 nm, the influence from the Pt layer is reduced, so that the ohmic contact with the p-type nitride semiconductor layer is reduced and the contact resistance is slightly increased. The comparison was good and there were no problems. Thus, by providing a Cr layer having a thickness within the range of the present invention in the lowermost layer, good adhesion and ohmic contact were obtained for both the n-side and p-side pad electrodes.

  As shown in FIG. 5, Pt diffuses to the vicinity of the lowermost surface of the Cr layer (right direction in FIG. 5), so that not only an n-type nitride semiconductor layer but also a p-type nitride semiconductor layer has a good ohmic contact. Sex was obtained. In addition, in the thickness of 1 nm of Cr layer shown to Fig.5 (a), Pt diffused also to the Au layer side because Cr layer was thin. Thus, by providing a Cr layer having a thickness within the range of the present invention in the lowermost layer, good adhesion and ohmic contact were obtained for both the n-side and p-side pad electrodes.

[Evaluation of heat treatment]
The effect of annealing on the pad electrode and the temperature dependence were evaluated by the measurement of the peeling rate (Sample No. 2 and 3) and the contact measurement (Sample No. 2 to 5). Sample No. 3 is the thickness of the Cr layer of 3 nm. The results are shown in FIG. 6A and FIG. 6B as graphs showing the annealing temperature dependence, and part of the results are shown in Table 2. Sample No. 7 was subjected to GDS analysis before and after annealing, and graphs of the distribution of detected intensity in the thickness direction are shown in FIGS. 7 (a) and 7 (b). Furthermore, sample no. 3 (annealing temperature 400 ° C.), the cross section near the interface between the ITO film and the pad electrode (p side) was observed using a scanning transmission electron microscope (STEM) at an acceleration voltage of 200 kv. A STEM image photograph at 600k magnification is shown in FIG. 8A, and the composition ratio of In as a component of Pt, Cr and ITO film analyzed by an energy dispersive X-ray spectrometer (EDS) is shown in FIG. 8B. .

(Effect of heat treatment)
As shown in FIG. 6A, adhesion of the Cr layer to the ITO film was obtained by performing heat treatment (annealing). On the other hand, as shown in FIG. 6 (b), the contact resistance tends to increase as the heat treatment temperature is increased. In particular, although the increase in the p-side pad electrode is large, it is the same as or higher than that in the n-side pad electrode. It was a change to low resistance. For the p-side pad electrode, the contact resistance is lower in the heat treatment up to about 300 ° C. than in the heat treatment (no heat treatment), and this suppresses the decrease in ohmic contact due to the thermal deterioration of the p-type nitride semiconductor layer. It is presumed that the effect of improving ohmic contact due to the diffusion of Pt into the Cr layer appeared. In addition, Sample No. whose Cr layer greatly exceeds the scope of the present invention. No. 5 has a small increase in the contact resistance of the p-side pad electrode due to the annealing temperature because the effect of Pt diffusion is small and the ohmic contact of the p-type nitride semiconductor layer of the Cr layer itself is lost due to heat. The temperature greatly exceeded the n-side pad electrode at 350 ° C. or higher.

  From the changes in FIGS. 7A and 7B, a region in which Cr and Pt are mixed (the white arrow in FIG. 7B) is generated in the Cr / Pt layer by the heat treatment. ) And (b), it was confirmed that a Cr—Pt alloy layer was formed. That is, it can be said that the diffusion of the mutual components proceeded between the Cr layer and the Pt layer by the heat treatment, and as a result, effects such as improved adhesion were obtained.

(Pt layer thickness dependence)
As shown in Table 2 and FIG. 6B, by laminating a sufficiently thick Pt layer on the Cr layer (sample No. 3, Cr layer thickness 3 nm), the n-side pad electrode of the Cr layer As a p-side pad electrode, adhesion to the ITO film and ohmic contact to the p-type nitride semiconductor layer were imparted while maintaining good adhesion and ohmic contact. Furthermore, even if the Pt layer is thinned to the same thickness of 3 nm as the Cr layer (Sample No. 4), sufficient adhesion and ohmic contact as the p-side pad electrode can be obtained, and the effects of the present invention can be confirmed. It was.

[Production of nitride semiconductor devices]
In Example 2, a nitride semiconductor device was produced in the same manner as in Example 1, and the effect of the barrier layer was evaluated. The nitride semiconductor layer has the same specifications as shown in Table 1, and the pad electrode structure is shown in Table 3. As shown in Table 3, the barrier layer examples of different materials (sample Nos. 9 and 10) and the comparison without the barrier layer An example (sample No. 8) was produced. In addition, sample No. 1 was obtained by changing the thickness of the Ru layer as a barrier layer from 40 nm to 90 nm in increments of 10 nm. For No. 11, the Pt layer was made as thick as 120 nm, while the Cr layer was made as thin as 2 nm in order to make it easy to understand the effect of suppressing the Pt diffusion by the barrier layer (Ru layer). Furthermore, in order to diffuse more Pt in these samples, annealing was performed twice at 500 ° C. for 10 minutes × 2 times (20 minutes in total).

[Evaluation of barrier layer]
GDS analysis was performed in the same manner as in Example 1, and the degree of diffusion of Pt into the Au layer was observed with a graph of the distribution of detected intensity in the thickness direction. Sample No. The graphs 9, 10, and 8 are shown in FIGS. 9A, 9B, and 9C, respectively. In addition, sample Nos. With different Ru layer thicknesses. In No. 11, GDS analysis was performed before annealing, and the amount of Pt diffused (detected intensity) in the Au layer was compared before and after annealing, and the presence or absence of an increase in Pt due to heat treatment was observed.

(Evaluation method for bonding properties)
Sample No. 8 to 10 and sample Nos. With respect to 12 nitride semiconductor elements 10 × 2 lots (20 in total), the wire shear strength at the pad electrodes on the n side and the p side was measured. Specifically, using the same wire bonding apparatus as that for measuring the peeling rate, an Au wire having a diameter of 23 μm was bonded to the pad electrode, and the adhesion between the wire and the pad electrode was measured. The results are shown in FIG. An average of 20 wire share strengths is 20 gf or more.

〔Evaluation results〕
As shown in FIGS. 9A and 9B, the effect of suppressing the diffusion of Pt due to heat treatment as a barrier layer can be obtained by applying any of the Ir layer and the Ru layer. As a result, as shown in FIG. Thus, the bonding property equivalent to the conventional pad electrode (reference example) could be maintained. On the other hand, sample No. of the comparative example which did not provide the barrier layer. In FIG. 8, Pt diffused into the Au layer as shown in FIG. 9 (c), and as a result, the bondability deteriorated as shown in FIG. Also, regarding the thickness of the barrier layer (Ru layer), Pt diffused into the Au layer by heat treatment at 40 nm and a sufficient suppression effect was not obtained, but Pt diffusion was small at 50 nm, which was sufficient as a barrier layer. An effect was observed, and when the thickness was 60 nm or more, Pt hardly diffused into the Au layer, and a preferable effect was obtained.

DESCRIPTION OF SYMBOLS 10 Nitride semiconductor element 1 Substrate 2 N type nitride semiconductor layer 3 Active layer 4 P type nitride semiconductor layer 5 P side electrode 6 Translucent electrode 7p P side pad electrode 7n N side electrode (n side pad electrode)
7 Pad electrode 71 Ohmic contact layer, Cr / Pt layer 71a Cr layer 71b Pt layer 72 Barrier layer (Ru layer or Ir layer)
73 Bonding layer (Au layer)
9 Protective film

Claims (8)

an n-type nitride semiconductor layer, a p-type nitride semiconductor layer stacked on the n-type nitride semiconductor layer, and a translucent electrode made of a conductive oxide formed on the p-type nitride semiconductor layer; A nitride semiconductor device comprising a p-side pad electrode formed in a partial region on the translucent electrode, and an n-side pad electrode connected to the n-type nitride semiconductor layer,
The p-side pad electrode and the p-side pad electrodes and the n-side pad electrode, from the side in contact with each of the n-type nitride semiconductor layer and the translucent electrode in sequence, of a thickness less than 1nm or more 9nm Cr layer, a nitride semiconductor device, characterized in that it comprises by stacking Pt layer having a thickness of more than the thickness of the pre-Symbol Cr layer. The Cr layer, the part of the Pt layer is diffused, a nitride semiconductor according to claim 1, wherein the layer containing Cr and Pt is formed between the Pt layer element. A Ru layer or an Ir layer is laminated on the Pt layer, and an Au layer is further laminated thereon to form the outermost surface of at least one of the n-side pad electrode and the p-side pad electrode. The nitride semiconductor device according to claim 1 or 2 . The nitride semiconductor device according to claim 3 , wherein the Ru layer or the Ir layer has a thickness of 50 nm or more. The translucent electrode is indium - nitride semiconductor device according to any one of claims 1 to 4, characterized in that it comprises a tin oxide. The n-side pad electrode, said laminated on n-type nitride semiconductor layer, wherein any one of the p-type nitride semiconductor layer and the claims 1 to 5 are formed in mutually different regions in the plane The nitride semiconductor device described in 1. The p-side pad electrode and the n-side pad electrode, a nitride semiconductor device according to any one of claims 1 to 6, characterized in that it consists of the same multilayer structure. An n-type nitride semiconductor layer, an n-side pad electrode and a p-type nitride semiconductor layer that are stacked on the n-type nitride semiconductor layer and formed in different regions on a plane, and the p-type nitride semiconductor layer An n-side pad electrode of a nitride semiconductor device comprising: a translucent electrode made of a conductive oxide formed; and a p-side pad electrode formed in a partial region on the translucent electrode; A method of manufacturing a pad electrode of a nitride semiconductor device for manufacturing the p-side pad electrode,
On each of the n-type nitride semiconductor layer and the translucent electrode, a Cr layer having a thickness of 1 nm or more and less than 9 nm and a Pt layer having a thickness not less than the thickness of the Cr layer are sequentially stacked, and the Pt layer Manufacturing of pad electrode of nitride semiconductor device, comprising: stacking Ru layer or Ir layer thereon, further stacking Au layer thereon, and heating the stacked metal layer Method.