CN101740533B - 集成电路 - Google Patents

集成电路 Download PDF

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CN101740533B
CN101740533B CN2009101300680A CN200910130068A CN101740533B CN 101740533 B CN101740533 B CN 101740533B CN 2009101300680 A CN2009101300680 A CN 2009101300680A CN 200910130068 A CN200910130068 A CN 200910130068A CN 101740533 B CN101740533 B CN 101740533B
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integrated circuit
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CN101740533A (zh
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萧全成
李洪松
林奕成
饶哲源
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MediaTek Inc
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Abstract

本发明提供一种集成电路，包含衬底及位于衬底上的连接垫阵列，所述连接垫阵列包含内部连接垫列、多个第一内部金属层、外部连接垫列以及多个第一外部金属层。其中每一内部连接垫的位置都与多个内部连接垫开窗相关；多个第一内部金属层分别耦接至内部连接垫列的多个内部连接垫；每一外部连接垫的位置都与多个外部连接垫开窗相关，且外部连接垫列与内部连接垫列相互交错；以及多个第一外部金属层分别耦接至外部连接垫列的多个外部连接垫，其中至少一个内部连接垫与相邻的第一外部金属层重叠。所述的集成电路能够减小集成电路芯片连接垫间距，并保持良好电迁移特性。

Description

集成电路
技术领域
本发明有关于一种复合集成电路(complex integrated circuit)的连接垫阵列(bond pad array)，且特别有关于一种具有小连接垫间距(pitch)及良好电迁移(electro-migration)特性的连接垫阵列。
背景技术
集成电路(Integrated Circuit，以下简称为IC)芯片是利用金属连接垫从其它电路接收信号，以及将信号提供给其它电路。所述连接垫是由多个金属层构成，其通常为矩形，而所述金属层中的某些金属层也可用于在连接垫及IC芯片的其它电路间传送信号。由一个或多个金属层形成的导线(conductive line)将连接垫连接至电路。
对于芯片来说，连接垫尺寸相对较大，因此连接垫的排列(arrangement)限制了电路的剩余空间。连接垫通常排列在IC芯片边缘周围。为了更有效地利用空间，复合IC芯片包含由连接垫构成的两个或更多同心环，其位置交错排列。连接垫的交错排列可使外部连接垫列的导线位于内部连接垫列的连接垫之间。
请参考图1。图1是现有技术中复合IC芯片100一部分的结构的示意图。如图所示，复合IC芯片100包含5个连接垫112、114、116、122及124，其中连接垫112、114、116、122形成复合IC芯片100的外部连接垫列，连接垫122、124形成复合IC芯片100的内部连接垫列。导线113、115、117位于内部连接垫列的连接垫之间，并分别耦接至外部连接垫列的连接垫112、114、116。导线123、125分别耦接至内部连接垫列的连接垫122、124。由图示可看出，耦接于外部连接垫列的连接垫112、114、116的导线113、115、117的宽度受限于内部连接垫列的连接垫122、124。
此外，请参考图2，图2是图1中连接垫122的连接垫结构120的剖面示意图。如图所示，完整的连接垫结构120包含多层，其包含顶部金属层Mtop 123(即导线123)、连接垫122、用于将连接垫122与顶部金属层Mtop 123连接的通孔20以及透过通孔12及14连接至顶部金属层Mtop 123的金属层Mtop-1 123a。通孔的连接使顶部金属层Mtop 123与金属层Mtop-1 123a具有相同的电位。由图示可看出，连接垫122的位置与连接垫开窗(pad opening)相关，且顶部金属层Mtop 123与金属层Mtop-1 123a都比连接垫122宽。请注意，顶部金属层Mtop 123及金属层Mtop-1 123a其中之一可用于将信号传送至复合IC芯片100的电路。
导线(金属层123或123a)的尺寸(或宽度)可影响连接垫122提供给复合IC芯片100的功率量(amount ofpower)，利用较宽导线可以比利用较窄导线提供更多功率。如图1所示，若连接垫间距(相邻连接垫间的距离)增加，则导线宽度也可增加。复合IC芯片100的功率与连接垫数量之间，需要一种权衡(trade-off)。此外，若连接垫间距减小(连接垫的位置相互更接近)，则电迁移问题很可能发生。
发明内容
为了减小集成电路芯片连接垫间距并保持良好电迁移特性，特提供以下技术方案：
本发明实施例提供一种集成电路，包含衬底以及位于衬底上的连接垫阵列。所述连接垫阵列包含内部连接垫列、多个第一内部金属层、外部连接垫列以及多个第一外部金属层。所述内部连接垫列中每一内部连接垫的位置都与多个内部连接垫开窗相关；所述多个第一内部金属层分别耦接至所述内部连接垫列的多个内部连接垫，以在所述多个内部连接垫与内部电路间传送信号，其中至少一个第一内部金属层的宽度小于对应的内部连接垫的宽度；所述外部连接垫列中每一外部连接垫的位置都与多个内部连接垫开窗相关，且所述外部连接垫列与所述内部连接垫列相互交错；以及所述多个第一外部金属层分别耦接至所述外部连接垫列的多个外部连接垫，以在所述多个外部连接垫与所述内部电路间传送信号，其中至少一个内部连接垫与相邻的第一外部金属层重叠。
以上所述的集成电路能够通过交错排列连接垫而减小集成电路芯片连接垫间距，并保持良好电迁移特性。
附图说明
图1是现有技术中复合IC芯片一部分的结构的示意图。
图2是图1中连接垫的连接垫结构的剖面示意图。
图3是依本发明实施例的连接垫结构的剖面示意图。
图4是依本发明实施例的复合IC芯片的示意图。
具体实施方式
在说明书及权利要求书当中使用了某些词汇来指称特定的元件。所属技术领域的技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求书并不以名称的差异作为区分元件的方式，而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求项中所提及的「包括」为一开放式的用语，故应解释成「包括但不限定于」。此外，「耦接」一词在此包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表第一装置可直接电气连接于第二装置，或透过其它装置或连接手段间接地电气连接至第二装置。
本发明的目的之一是为复合IC芯片提供一种新的连接垫结构，其连接垫间距小、可增加功率供给，且不会增加电迁移。
一般来说，集成电路包含衬底以及位于衬底上的连接垫阵列。请参考图3，图3是依本发明实施例的连接垫结构300的剖面示意图。连接垫322的位置与连接垫开窗相关。连接垫322透过连接垫通孔320耦接至顶部金属层Mtop 323及次顶部(second top)金属层Mtop-1 323a。图3中仅画出了顶部金属层Mtop 323与次顶部金属层Mtop-1 323a，请注意，连接垫结构300可包含比图中所示更多的层。顶部金属层Mtop 323与次顶部金属层Mtop-1 323a透过通孔312及314相互耦接，从而保证两金属层的电位相同。此外，请注意，顶部金属层Mtop 323与次顶部金属层Mtop-1 323a其中之一可传送电流，即，两金属层其中之一可形成导线，而另一金属层可作为支撑层以减小连接垫结构300的应力。此外，所述另一金属层的形状可为空心环(hollow ring)等空心结构，或其它支撑结构。
如图3所示，与图2中现有技术的连接垫结构120相比，连接垫通孔320、顶部金属层Mtop323及次顶部金属层Mtop-1 323a的宽度实质上都有所减少。图示中连接垫通孔320的宽度与顶部金属层Mtop 323的宽度相同，但其宽度也可以比顶部金属层Mtop 323的宽度小。顶部金属层Mtop 323的宽度及次顶部金属层Mtop-1 323a的宽度并非仅限于相同。尽管顶部金属层Mtop 323的宽度有所减少，但并不会对导线产生很大影响，因为顶部金属层Mtop 323比其它金属层薄得多，从而能够承受比其它金属层更大的电流。
因此，上述结构可用于复合IC芯片的内部连接垫。内部连接垫与复合IC芯片中电路之间更短的距离，以及顶部金属层仍可承受足够大电流的状况，都不会对由内部连接垫提供的功率产生很大副作用(negative effect)。而且，上述复合IC芯片中内部连接垫的新结构可使外部连接垫能够传送更大电流，其详细解释如下。
请参考图4。图4是依本发明实施例的复合IC芯片400的示意图，其中内部连接垫322及324具有图3所示的结构。复合IC芯片400包含分别耦接至导线313、315及317的一列外部连接垫312、314及316。内部连接垫322、324分别耦接至导线323、325。
由于内部连接垫322、324的连接垫通孔(未画出)的宽度及导线323、325的金属层宽度都有所减少，因此外部连接垫312、314及316的导线313、315及317可延伸至相邻内部连接垫322及324的边缘外。图4中导线313的宽度W2受到如下限制：一个连接垫通孔只能与单一连接垫的金属层连接，否则就会发生短路。因此，只要连接垫322的连接垫通孔的宽度小于(或等于)导线323的宽度，导线313即可延伸至几乎接触到导线323的位置。应注意，上述连接垫结构可应用于任何多层(multi-tier)结构，例如三层(third-tier)或四层(quad-tier)结构。本领域的技术人员在阅读上述内容后应可实施不同的修饰，为简洁起见，在此不另赘述。
由于外部连接垫的导线宽度增加，电迁移问题(由电流路径过窄所导致)将不会发生。连接垫通孔的宽度及内部连接垫的金属层宽度的减少，可使内部连接垫能够与外部连接垫的导线重叠，从而减小连接垫间距。由于内部连接垫更接近IC芯片中的电路，以及顶部金属层因比其它金属层更薄而可承受更大的电流，因此，内部连接垫的导线中的电流不会受到宽度减小的不利影响。
因此，本发明所揭示的连接垫结构可为复合IC芯片提供一种连接垫阵列，所述连接垫阵列具有较小连接垫间距，且不会增加电迁移。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (8)

1.一种集成电路，包含：
衬底；以及
位于该衬底上的连接垫阵列，该连接垫阵列包含：
内部连接垫列，该内部连接垫列中每一内部连接垫的位置都与多个内部连接垫开窗相关；
多个第一内部金属层，分别耦接至该内部连接垫列的多个内部连接垫，以在该多个内部连接垫与内部电路间传送信号，其中至少一个第一内部金属层的宽度小于对应的内部连接垫的宽度；
外部连接垫列，该外部连接垫列中每一外部连接垫的位置都与多个外部连接垫开窗相关，且该外部连接垫列与该内部连接垫列相互交错；以及
多个第一外部金属层，分别耦接至该外部连接垫列的多个外部连接垫，以在该多个外部连接垫与该内部电路间传送信号，其中至少一个内部连接垫与相邻的第一外部金属层重叠。
2.如权利要求1所述的集成电路，还包含：
多个第二内部金属层，分别耦接至该多个第一内部金属层，其中至少一个第二内部金属层的宽度小于对应的内部连接垫的宽度；以及
多个第二外部金属层，分别耦接至该多个第一外部金属层。
3.如权利要求2所述的集成电路，其特征在于：该多个第二内部金属层及该多个第二外部金属层都具有空心结构，以分别支撑该多个第一内部金属层及该多个第一外部金属层。
4.如权利要求1所述的集成电路，其特征在于：该连接垫阵列还包含多个通孔，该多个通孔分别耦接于该多个第一内部金属层与该多个内部连接垫之间，每一通孔的宽度等于或小于对应的第一内部金属层的宽度，以及每一第一外部金属层的宽度都小于两相邻的通孔的距离。
5.一种集成电路，包含：
多个内部连接垫，该多个内部连接垫的位置与多个内部连接垫开窗相关；
多个第一内部金属层，分别耦接至该多个内部连接垫，以将该多个内部连接垫电连接至内部电路，其中至少一个第一内部金属层的宽度小于对应的内部连接垫的宽度；
多个外部连接垫，该多个外部连接垫的位置与多个外部连接垫开窗相关；以及
多个第一外部金属层，分别耦接至该多个外部连接垫，以将该多个外部连接垫电连接至该内部电路，其中至少一个内部连接垫与相邻的第一外部金属层重叠。
6.如权利要求5所述的集成电路，其特征在于：该集成电路还包含：
多个第二内部金属层，分别耦接至该多个第一内部金属层，其中至少一个第二内部金属层的宽度小于对应的内部连接垫的宽度。
7.如权利要求5所述的集成电路，其特征在于：该集成电路还包含：
多个第二内部金属层，分别耦接至该多个第一内部金属层，其中至少一个第二内部金属层的宽度小于对应的第一内部金属层的宽度。
8.如权利要求5所述的集成电路，其特征在于：该集成电路还包含：
多个通孔，该多个通孔分别耦接于该多个第一内部金属层与该多个内部连接垫之间，其中每一通孔的宽度等于或小于对应的第一内部金属层的宽度，以及每一第一外部金属层的宽度都小于两相邻的通孔之间的距离。
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